JPH1013307A - Digital delay locked loop - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain an excellent frequency and an phase tracking by controlling the phase of reference, early and delayed pseudo noise codes generated by a pseudo noise code generator. SOLUTION: A subtractor 45 subtracts a delayed inverted spread data signal V2 of a delay spread device 43 from an early inverted spread data signal V1 of an early correlation device 42 to generate a difference signal Y(τ), which is fed to a voltage controlled encoder(VCE) 46. A decision section 47 compares a binary code received from the VCE 46 with a minimum threshold level and a maximum threshold level and outputs, a phase ON decision signal ON, a phase advance decision signal AV or a phase retard decision signal RV selectively depending on the result of comparison. Then a controller 48 receiving the phase ON discrimination signal ON, the phase advance decision signal AV or the phase retard decision signal RV that is the comparison resulting signal from the discrimination section 47 generates a pseudo code decision signal to control phases of reference, early and delayed pseudo noise codes generated by a pseudo noise code generator 41.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum communication system, and more particularly, to an initial synchronization for a received spread data signal at a receiver of a spread spectrum communication system using a pseudo noise code generator. A digital delay lock loop that performs frequency and phase tracking operations without losing state.
ked loop (hereinafter, referred to as DLL).

[0002]

2. Description of the Related Art In general, a spread spectrum communication system is a system for improving the channel noise, jamming, and privacy characteristics by spreading a frequency band of a baseband voice signal to an arbitrary band. A direct sequence (DS) method can be used. In recent years, spread spectrum systems make heavy use of a technique called stored references (SRs). Thus, the spreading code signal is generated independently at the transmitter and the receiver. The main advantage of SR systems is that well-designed code signals are not predicted by monitoring transmissions. Since the same code must occur independently at more than one location, the code sequence must be conclusive even if it appears randomly to an unauthorized listener. The random appearance determination signal is a pseudo noise (p
It is called seudo noise (PN) or pseudo-random signal.

A DLL is a PLL using a variable delay line.
(phase locked loop). The DLL is a simple and versatile circuit that utilizes an analog delay line based on a sequence of voltage control elements.
The DLL detects a phase difference between clock signals having the same frequency, and generates an error voltage that changes according to the phase difference.
By feeding back the error voltage to control the variable delay line, the timing of one clock signal is advanced or delayed until the rising edge of the clock signal coincides with the rising edge of the reference signal.

[0004] The synchronization process of a spread waveform receiver generally has at least two modes: (A) an initial synchronization mode and (B).
The mode is divided into the track mode. The initial synchronization mode and the track mode require that the receiver have an accurate replica of the pseudo-noise sequence.

[0005] Once the initial synchronization process is completed, the receiver must maintain an accurate time alignment of the replica and received PN sequence that occurred within a fraction of a chip interval. FIG. 1 shows a conventional DLL circuit for synchronizing two PN code sequences. After the initial synchronization operation is completed, the input line 101 receives the signal s (t) spread in the pseudo noise frequency band.

The despreading correlator 102 is connected to the input line 1
When the signal s (t) spread through the pseudo noise frequency band received through the signal line 01 is received, the pseudo noise code c (t) generated by the pseudo noise code generator 103 is received through the input line 101. The received pseudo-noise band frequency signal s (t) is multiplied by a locally generated on-time pseudo-noise code c (t), and the received pseudo-noise frequency signal s (t) is multiplied by a baseband speech signal Z ( The data is despread to t) and supplied to the data demodulator 104.

[0007] The received spread data signal s (t)
Is calculated by the early correlator 105 and the delayed correlator 108.
The early and delayed PN codes E (t) and L (t) of the spread waveform generated by the code generator 103 are multiplied. The obtained early and delayed multiplied signals Z1 (t), Z2
(T) shows the first and second band pass filters 106 and 10
9, the error signal Y passes through the first and second square detectors 107 and 110 and is subtracted from each other by the subtractor 111.
(Τ). The first and second bandpass filters 106 and 109 function as integrators, and the output signals of the first and second square detectors 107 and 110 are the magnitude of the autocorrelation function of the PN sequence. The two signals are subtracted to form an error signal Y (τ). Early and late PN
If the code is exactly centered with respect to the received PN code, the low-pass portion of the error signal Y (τ) will be zero.
The correction voltage is obtained by low-pass filtering by the loop filter 112,
Rolled oscillator (hereinafter referred to as VCO) 113 is used for driving. The VCO 113 controls the chip rate of the PN code generator 103, and the relative timing of the multiplication signal changes to drive the error signal to the zero side according to the chip rate.

According to such a method, when the initial timing error is very small, the PN code generator 103
By tracking the received PN code, the despread correlator 102 accurately despreads the spread data signal received through the input line into a baseband signal and provides it to the data demodulator 104.

However, the DLL circuit has a problem that it cannot perform a frequency and phase tracking operation on a signal transmitted in a digital format because of an analog circuit.

In recent years, the data processing process in direct sequence spread spectrum communication tends to gradually change from an analog system to a digital system. Conventional DLL described above
Among the circuits, the despreading correlator, the early correlator, the delayed correlator, the first and second bandpass filters, the first and second square detectors, and the loop filter have been proposed to be implemented as digital circuits. A method for implementing a digital circuit that performs the same function as a pseudo noise generator and a VCO that controls pseudo noise generation has not been proposed.

An example of a digital DLL is James R.
U.S. Patent No. 4,617,530 (1.
(October 14, 986). U.S. Pat. No. 4,617,530 relates to a pseudo-random noise generator having an optionally long repetition rate. The pseudo-random noise generator includes a two-component pseudo-random noise generator, and a signal from one of the pseudo-random noise generators connected to an output terminal of the pseudo-random noise generator. -Utilizes a combination circuit consisting of a field effect transistor and a resistor that is modulated by a signal from another of the random noise generators.

Another example of a digital DLL is Yasum.
US Patent No. 5,243,3 by oto Murata
No. 03 (granted September 7, 1993). U.S. Pat. No. 5,243,303 relates to a pseudo-random noise signal generator for testing characteristics of communication equipment and audio systems. The conventional pseudo-random noise signal generator includes a generator having a shift register for performing a shift operation so that one bit is sequentially shifted to a next upper stage in an input stage. The exclusive OR circuit performs an exclusive OR operation between a pair of bits from a selected stage of the shift register and feeds back to an input stage of the shift register. The filter receives the pseudo-random data and outputs an analog signal.

The filter has an operational amplifier. Each output of the stages of the shift register is selectively supplied to the non-inverting and inverting inputs of the operational amplifier through respective resistors. However, U.S. Pat. Nos. 4,617,530 and 5,243,303 can track the frequency and phase of an analog spread data signal received by a spread spectrum communication system receiver, but not a digital spread data signal. Has a problem that the frequency and phase cannot be tracked.

[0014]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems of the prior art, and the technical problem of the present invention is to provide a spread spectrum communication system having a receiver for receiving spread data. An object of the present invention is to provide a digital DLL that performs a frequency and phase tracking operation so as not to lose an initial synchronization state for a signal.

[0015]

According to the present invention, there is provided a digital delay locked loop for tracking the frequency and phase of a received spread data signal at a receiver of a spread spectrum communication system, comprising: A reference pseudo-noise code whose phase is changed by a predetermined control is generated, and the reference pseudo-noise code is supplied to a despreading correlator of a receiver of a spread spectrum communication system. A pseudo-noise code generator for generating an early pseudo-noise code and a delayed pseudo-noise code whose phases are advanced and delayed, respectively, and an early pseudo-noise code generated by the pseudo-noise code generator and a received spread data signal. Early correlator for generating an early despread data signal on the basis of and calculating the magnitude of the generated early spread data signal Generating a delayed despread data signal based on the delayed pseudo noise code generated by the pseudo noise code generator and the received spread data signal, and calculating a magnitude of the generated delayed despread data signal; A correlator, and a reference pseudo-noise code, an early pseudo-noise code, and a delayed pseudo-noise code delayed by delaying the reference pseudo-noise code, the early pseudo-noise code, and the delayed pseudo-noise code generated by the pseudo-noise code generator, respectively. A delay circuit that supplies the despread correlator, the early correlator, and the delay correlator; A subtractor for subtracting the magnitude of the data signal to generate a difference signal; and a subtractor that is supplied as an input of the difference signal from the subtractor and corresponds to the difference signal. A voltage control encoder for generating a binary code, and storing at least one or more voltage values and binary codes corresponding to the at least one or more voltage values, and receiving the binary code from the voltage control encoder A comparing unit that compares the received binary code with a minimum threshold and a maximum threshold, and outputs a comparison result signal based on a result of the comparison; and generating the pseudo noise code based on the comparison result signal from the determination unit. And a controller for controlling the phases of the reference, early and delayed pseudo-noise codes generated by the transmitter, respectively, for tracking the frequency and phase of the received spread data signal at the receiver of the spread spectrum communication system. To provide a digital delay lock loop.

Preferably, the minimum threshold value and the maximum threshold value are within an allowable range of a phase deviation of the reference pseudo noise code generated by the pseudo noise code generator with respect to the received spread data signal.

Preferably, the delay circuit delays a reference pseudo noise code generated by the pseudo noise code generator and supplies a delayed reference pseudo noise code to the despreading correlator; A second delay unit that delays the early pseudo noise code generated by the pseudo noise code generator and supplies the delayed early pseudo noise code to the early correlator; and a delayed pseudo noise generated by the pseudo noise code generator. And a third delay unit for delaying the code and providing a delayed pseudo-noise code to the delay correlator.

Preferably, the magnitude of the early spread data signal and the delayed despread data signal, and the difference signal are one of a voltage and a current.

If the result of the comparison indicates that the binary code from the voltage control encoder is greater than or equal to the minimum threshold and less than or equal to the maximum threshold, the determination unit outputs the phase-on determination signal, and outputs the binary code. Is smaller than the minimum threshold, the phase advance determination signal is output, and if the binary code is larger than the maximum threshold, the phase retard determination signal is output.

Further, preferably, the determination unit is configured to store a binary code used in the control voltage encoder and a voltage value corresponding to the binary code, and a look-up table memory, A comparator for comparing the binary code with the minimum and maximum thresholds and outputting a comparison result signal based on a result of the comparison.

According to the present invention having such a configuration, in a DS spread spectrum communication, a DLL for performing a frequency and phase tracking operation of a pseudo noise code is constituted by a digital circuit, and the digital DS spread spectrum communication facilitates digital code tracking. Can be.

The above objects and other features and advantages of the present invention will become apparent from the following description of some preferred embodiments of the present invention to which reference is now made.

[0023]

Preferred embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are used for the same elements. FIG. 2 and FIG. 3 are schematic block diagrams of a spread spectrum communication system utilizing a direct sequence. FIG. 2 shows a transmitter, and FIG. 3 shows a receiver.

Referring to FIG. 2, the information signal represented by a (t) is modulated by modulator 210 to produce a modulated signal b (t).
Is output as The modulated signal b (t) is transmitted to the spreading unit 23.
Is multiplied by the PN code c (t) generated from the pseudo noise code generator 22 by the multiplier 231. The pseudo noise code generator 22 is driven by a clock signal from a reference clock generator 24. The chip rate of the PN code c (t) is higher than the data rate of the information signal a (t). Therefore, the spectrum band of the multiplier output signal s (t) is spread as compared with the modulation signal b (t). The multiplier output signal s (t) is converted by the frequency converter 25 into R
The signal is converted to an F signal, amplified by an amplifier 26, and transmitted through an antenna 27.

Referring to FIG. 3, in the receiver, the signal received by antenna 31 is amplified by RF amplifier 32 and converted to intermediate frequency signal s (t) by frequency converter 33. The signal s (t) converted to the intermediate frequency is
C generated from the transmitter side by the pseudo noise code generator 341
PN code c (t) having the same sequence as (t)
Is multiplied by The PN code generated by the pseudo noise code generator 342 must be synchronized with the PN code included in the received signal supplied as an input to the despreading correlator 35. For that purpose, a time discrimination control circuit 342 having a loop structure is used. The time discrimination control circuit 342 constitutes the synchronizing unit 34 together with the pseudo noise code generator 341. With the PN code removed from the despreading correlator 35, the output b (t) from the despreading correlator 35 returns to a narrow band signal modulated by the data, and is demodulated through the information demodulator 36 to obtain the information signal a. (T).

Since the time synchronization is performed by the despreading correlator 35 on the receiver side, the influence of time-delayed multipath fading may be reduced. Since the received signal is applied to the PN code generated by the PN code generator 341, the narrow band noise input of the receiving antenna and its influence are reduced.

As described above, the spread spectrum enables a communication with a wide bandwidth that is strong against multipath fading and narrow band noise, thereby performing more effective communication. FIG. 4 shows a configuration of a digital DLL 40 for tracking the frequency and phase of a received spread data signal in a receiver of a spread spectrum communication system according to an embodiment of the present invention.

Digital DLL 4 according to an embodiment of the present invention
0 is a pseudo noise code generator 41, an early correlator 42, a delay correlator 43, a delay circuit 44, a subtractor 45, a voltage controlled encoder (hereinafter, referred to as VCE) 46, a determination unit 47, and a controller 48. Is provided.

The pseudo noise code generator 41 includes a controller 48
Generates a reference pseudo-noise code whose phase changes under the control of the control circuit, and supplies the reference pseudo-noise code to the despread correlator 401 of the receiver through the first delay unit 441 of the delay circuit 44. An early and late pseudo noise code which advances or delays is generated, and the early correlator 4 is passed through the second and third delay units 442 and 443 of the delay circuit 44.
2 and the delay correlator 43.

The early correlator 42 generates an early despread data signal based on the early pseudo noise code generated by the pseudo noise code generator 41 and the received spread data signal, and generates the early spread data signal. Is supplied to the subtractor 45. The early correlator 42 multiplies the early pseudo noise code E (t) generated by the pseudo noise code generator 41 by the received spread data signal r (t) to generate a first multiplied signal Z (t). First multiplier 42
1 and the first multiplied signal from the first multiplier 421 is squared to generate the magnitude of the first multiplied signal, and the subtracter 45
, And a first square detector 423 that supplies the first squared detector 423. The early correlator 42 removes a high-frequency noise component included in the first multiplied signal from the first multiplier 421, generates a first multiplied signal from which the noise component has been removed, and generates the first squared signal. 423 provided to the first band-pass filter (BP
F) 422 is further provided.

The delay correlator 43 generates a delayed despread data signal based on the delayed pseudo noise code L (t) generated by the pseudo noise code generator 41 and the received spread data signal r (t). The magnitude of the generated delayed despread data signal is provided to the subtractor 45. The delay correlator 43 includes a delay pseudo noise code L (t) generated by the pseudo noise code and a received spread data signal r.
(T) to generate a second multiplied signal Z (t), and the second multiplied signal Z2 (t) from the second multiplier 431 is squared to form the second multiplied signal Z (t). It has a second square detector 433 that generates the magnitude of the multiplication signal and supplies it to the subtractor 45. The delay correlator 43 is configured to
A second band-pass filter that removes a high-frequency noise component included in the second multiplication signal from the multiplier 431, generates a second multiplication signal from which the noise component has been removed, and supplies the second multiplication signal to the second square detector 433. (BPF) 432 is further provided.

The delay circuit 44 is connected to an output terminal of the pseudo noise code generator 41 and is connected to the pseudo noise code generator 4.
1 is generated by delaying the reference pseudo-noise code, the early pseudo-noise code, and the delayed pseudo-noise code, respectively, so that the delayed reference pseudo-noise code c (t), the early pseudo-noise code E (t), and the delayed pseudo-noise code The code L (t) is supplied to the despreading correlator 401, the early correlator 42, and the delayed correlator 43, respectively. The delay circuit 44
The reference pseudo-noise code generated by the pseudo-noise code generator 41 is delayed to delay the reference pseudo-noise code c.
(T) is supplied to the despreading correlator 401. The first delay unit 441 delays the early pseudo noise code generated by the pseudo noise code generator 41 and delays the early pseudo noise code E (t). A second delay unit 442 for supplying the early correlator 42 and a delayed pseudo noise code L (t) delayed by delaying the delayed pseudo noise code generated by the pseudo noise code generator 41 to the delayed correlator 43. It has a third delay unit 443 for supplying.

The subtractor 45 is connected to the output terminals of the early correlator 42 and the delayed correlator 43, and
The magnitude of the delayed despread data signal V2 from the second square detector 433 of the delay spreader 43 is subtracted from the magnitude of the early despread data signal V1 from the second first square detector 423. , A difference signal Y (τ) is generated and VCE 46
To supply. The VCE 46 generates a binary code corresponding to the difference signal from the subtracter 45 and supplies the binary code to the determination unit 47.

As described in Table 1, the determination unit 47 stores at least one or more binary codes and a voltage value corresponding to the binary codes, and receives the binary codes from the VCE 46 and The received binary code is compared with the minimum and maximum threshold values, and one of a phase-on determination signal ON, a phase advance determination signal AV, and a phase retard determination signal RV is selectively output according to the comparison result. The determination unit 47 includes a lookup table memory 471 that stores the minimum and maximum thresholds, and a comparator 472 that compares the binary code from the VCE 46 with the minimum and maximum thresholds and outputs a comparison result signal based on the comparison result. Have. The phase-on determination signal ON is a signal for maintaining the phases of the reference, early, and delayed pseudo-noise codes generated by the pseudo-noise code generator 41 as they are. The phase advance determination signal AV is output from the pseudo noise code generator 4.
1 is a signal that advances the phase of the reference, early, and delayed pseudo-noise codes that occur. The phase retard determination signal RT is
References generated by the pseudo noise code generator 41, early,
And a signal for delaying the phase of the delayed pseudo noise code.

The controller 48 is connected to the output terminal of the judging section 47 and generates a phase on, advance and retard judging signal according to the comparison result signal from the judging section 47, and the pseudo noise code generator 41 generates. And controlling phases of the reference pseudo noise code, the early pseudo noise code, and the delayed pseudo noise code.

Table 1 shows an example of at least one or more binary codes stored in the look-up table memory 471 of the determination unit 47 and voltage values corresponding to the binary codes.

[Table 1]

Hereinafter, the operation of the digital DLL for tracking the frequency and phase of the received spread data signal in the receiver of the spread spectrum communication system according to the embodiment of the present invention will be described with reference to the accompanying drawings. explain.

The input line 400 of the digital DLL 40
Receives the signal r (t) spread to the pseudo noise frequency band after the initial synchronization operation is completed. The spread signal r (t) has a waveform as shown in FIG. 5A.

The despreading correlator 401 is connected to the input line 40
0 and the signal r (t) spread in the pseudo noise frequency band and the reference pseudo noise code c (generated by the pseudo noise code generator 41 and received through the first delay unit 441 of the delay unit 44. By multiplying by t)
The received pseudo noise spread data signal r (t) is despread into a baseband signal to generate a baseband despread data signal Z (t), which is supplied to a data demodulator 402. The despread data signal Z (t) of the base band is shown in FIG.
It has a waveform like B. The data demodulator 402 demodulates the despread data signal in the known band from the despread correlator 401 into an original signal before being modulated, and outputs it to the outside.

In the early correlator 42, the first multiplier 42
1 multiplies the early pseudo-noise code E (t) generated by the pseudo-noise code generator 41 and the received spread data signal r (t) to generate a first multiplication signal Z1 (t); The signal is supplied to the first band pass filter 422. The first band-pass filter 422 removes a high-frequency noise component included in the first multiplied signal Z1 (t) from the first multiplier 421, and removes the noise component from the first multiplied signal M1 (t). And supplies it to the first square detector 423. The first square detector 423 is connected to the first multiplier 4
21, the first multiplied signal M1 (t) from which the noise component has been removed is squared to obtain the magnitude V1 of the first multiplied signal.
Is generated and supplied to the subtractor 45.

In the delay correlator 43, the second multiplier 43
1 multiplies the delayed pseudo noise code L (t) generated by the pseudo noise code generator 41 by the received spread data signal r (t) to generate a second multiplied signal Z2 (t); The signal is supplied to the second band pass filter 432. The second bandpass filter 432 removes a high-frequency noise component included in the second multiplied signal Z2 (t) from the second multiplier 431, and removes the noise component from the second multiplied signal M2 (t). Is generated and supplied to the second square detector 433. The second square detector 433 is connected to the second multiplier 431.
Multiplied signal M2 from which the noise component has been removed from
(T) is squared to generate the magnitude V2 of the second multiplied signal and supply it to the subtractor 45.

A subtractor 45 is provided for the first correlator 42.
From the magnitude V1 of the early despread data signal from the square detector 423, the second square detector 43 of the delay spreader 43
3 is subtracted from the magnitude V2 of the delayed despread data signal to generate a difference signal Y (τ), which is supplied to the VCE 46.
The VCE 46 receives the difference signal Y from the subtractor 45.
(Τ) is received, a binary code corresponding to the received difference signal Y (τ) is generated and supplied to the determination unit 47.

As described in Table 1, the determination unit 47 determines whether the binary code from the VCE 46 and the minimum threshold T
HL and a maximum threshold THH, and the result of the comparison is that the binary code from the VCE 46 is
L and not more than the maximum threshold value THL (THL ≦ binary code ≦ 2THH), the phase-on determination signal O
N, when the binary code is less than the minimum threshold value THL, the phase advance determination signal AV is controlled, and when the binary code is greater than the maximum threshold value THH, the phase retard determination signal RT is controlled. To the unit 48.

The controller 48 determines the phases of the reference pseudo noise code, the early pseudo noise code, and the delayed pseudo noise code generated by the pseudo noise code generator 41 based on the comparison result signal from the determination section 47. Control.

FIG. 6 is a waveform diagram of each signal by the digital DLL shown in FIG. 4 in a state where the pseudo noise code is synchronized with the spread data signal. FIG. 7 shows FIG.
5 is an output waveform diagram of the first and second square detectors shown in FIG. 4 in the state of FIG.

As shown in FIG. 6, the reference pseudo noise code c (t) generated by the pseudo noise code generator 41 and received by the despreading correlator 401 through the first delay unit 441 of the delay circuit 44 is input to the input line. If the synchronization with the spread data signal r (t) received by the despreading correlator 401 through 400 is achieved, the received spread data signal r
(T) and the early pseudo noise code E (t) generated by the pseudo noise code generator 41 have a phase difference of-△, and the received spread data signal r (t) and the pseudo noise code generator 41 Pseudo-noise code L generated by
The phase difference of (t) is + △.

Therefore, the output magnitude V1 of the first square detector 107 and the magnitude V2 of the second square detector 110 are the same as shown in FIG. 7, and the output of the subtracter 45 is 0 volt.
CE46 is a binary code 100 corresponding to the 0 volt.
(2) is supplied to the determination unit 47. The determination unit 47 uses the look-up table memory 471 to make the voltage value V (2) = 0 corresponding to the binary code 100 (2) from the VCE 46.
１1 mV (Table 1), minimum threshold THL and maximum threshold THH
Compare. In the present invention, the minimum threshold value THL is -2 m
V and the maximum threshold THH is +2 mV. As a result of the comparison, since −3 mV ≦ V (2) ≦ + 3 mV, the determination unit 47 outputs the phase-on determination signal ON to the controller
To supply. Accordingly, the controller 48 receives the input of the phase-on determination signal ON from the determination unit 47, generates a phase-on control signal, controls the pseudo-noise code generator 41, and generates the current signal generated by the pseudo-noise code generator 41. The phase of the oscillating reference pseudo noise code c (t), the early pseudo noise code E (t), and the delayed pseudo noise code L (t) is maintained.

FIG. 8 is a waveform diagram of each signal by the digital DLL shown in FIG. 4 when the pseudo noise code c (t) is delayed from the spread data signal r (t) by the phase δ. FIG. 9 is an output waveform diagram of the first and second square detectors shown in FIG. 4 in the state of FIG.

As shown in FIG. 8, the reference pseudo-noise code c (t) generated by the pseudo-noise code generator 41 and received through the first delay unit 441 of the delay circuit 44 is transmitted through the input line 400 to the despread correlation code. Is delayed by a phase δ from the spread data signal r (t) received by the
The phase difference between the received spread data signal r (t) and the generated early pseudo noise code E (t) is + △ −δ,
The received spread data signal r (t) and the delayed pseudo noise code L generated by the pseudo noise code generator 41
The phase difference from (t) is-(△ + δ).

Therefore, as shown in FIG. 9, the output magnitude V1 of the first square detector 107 is smaller than the output magnitude V2 of the second square detector 110, and the output of the subtractor 45 is the phase difference −
A voltage corresponding to 2δ, for example, -3 millivolts. Then, the VCE 46 supplies a binary code 100 (2) corresponding to the above-mentioned -3 millivolt to the determination unit 47. The determination unit 47 compares the binary code 001 (2) from the VCE 46, that is, V (2) = − 3 mV with the minimum threshold value −2 mV and the maximum threshold value +2 mV. As a result of the comparison, V (2) <
Since the output is −2 mV, the determination unit 47 supplies the controller 48 with the phase advance determination signal AV. Accordingly, the controller 48 outputs the phase advance determination signal A from the determination section 47.
Upon receiving the input of V, the phase advance control signal is supplied to the pseudo noise code generator 41.

The pseudo noise code generator 41 is connected to the controller 4
The phase of the reference pseudo-noise code c (t), the early pseudo-noise code E (t), and the delayed pseudo-noise code L (t) generated with the phase δ delayed by the phase retardation determination signal from FIG. Thus, the received reference pseudo noise code c (t) is made in phase with the spread data signal r (t) received by the despreading correlator 401.

FIG. 10 is a waveform diagram of each signal by the digital DLL shown in FIG. 4 in a state where the pseudo noise code c (t) leads the spread data signal r (t) by the phase δ. FIG. 11 shows the first state shown in FIG. 4 in the state of FIG.
FIG. 7 is an output waveform diagram of a second square detector.

As shown in FIG. 10, the pseudo-noise code generator 41 generates the reference pseudo-noise code c (t) received through the first delay unit 441 of the delay circuit 44 and the despread correlator through the input line 400. If the received spread data signal r (t) is advanced by phase δ from the received spread data signal r (t), the phase difference between the received spread data signal r (t) and the generated early pseudo noise code E (t) is + Δ + δ, and the phase difference between the received spread data signal r (t) and the delayed pseudo noise code L (t) generated by the pseudo noise code generator 41 is − (４１−δ).

Therefore, as shown in FIG. 11, the output magnitude V1 of the first square detector 107 is larger than the output magnitude V2 of the second square detector 110, and the output of the subtractor 45 corresponds to the phase difference + 2δ. Voltage, for example, +3 millivolts. Then, the VCE 46 supplies the binary code 111 (2) corresponding to the +3 millivolt to the determination unit 47. The determination unit 47 outputs the binary code 111 (2) from the VCE 46,
That is, V (2) = + 3 mV is compared with the minimum threshold value −2 mV and the maximum threshold value +2 mV. The comparison result V (2)
Since <+2 mV, the determination unit 47 supplies the phase retard determination signal RT to the controller 48. As a result, the controller 48 outputs the phase retard determination signal RT from the determination section 47.
And supplies a phase retard control signal to the pseudo noise code generator 41.

The pseudo-noise code generator 41 generates a reference pseudo-noise code c (t), an early pseudo-noise code E (t) generated earlier by the phase δ according to a phase retardation determination signal from the controller 48, and a delay Pseudo noise code L (t)
Are delayed by δ so that the received reference pseudo-noise code c (t) is in phase with the spread data signal r (t) received by the despreading correlator 401.

Although the present invention has been described in detail with reference to the embodiments, the present invention is not limited to the embodiments, and any person having ordinary knowledge in the technical field to which the present invention belongs may depart from the spirit and spirit of the present invention. Rather, the invention could be modified or changed. Further, the present invention can be implemented by a computer program stored in a recording medium.

[0057]

As described above, according to the present invention, in the DS spread spectrum communication, the DLL for performing the frequency and phase tracking operation of the pseudo noise code is constituted by a digital circuit, and the digital DS spread spectrum communication is performed by the digital code tracking. There is an effect that can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a conventional analog DLL.

FIG. 2 is a block diagram showing a configuration of a transmitter of a direct sequence spread spectrum system applicable to the present invention.

FIG. 3 is a block diagram showing a configuration of a receiver of a direct sequence spread spectrum system applicable to the present invention.

FIG. 4 is a block diagram showing a configuration of a digital DLL according to an embodiment of the present invention.

FIG. 5 consists of A and B, where A is the spread signal r
It is a figure showing the spectrum distribution of (t), and B is a figure showing the spectrum distribution of the despread data signal Z (t).

FIG. 6 shows the digital DL shown in FIG. 4 in a state where the pseudo noise code and the spread data signal are synchronized.
FIG. 4 is a waveform diagram of each signal by L.

7 shows the first and second states shown in FIG. 4 in the state of FIG. 6;
FIG. 3 is an output waveform diagram of a square detector.

8 is a waveform diagram of each signal by the digital DLL shown in FIG. 4 in a state where the pseudo noise code is delayed from the spread data signal by the phase δ.

9 shows the first and second states shown in FIG. 4 in the state of FIG. 8;
FIG. 3 is an output waveform diagram of a square detector.

FIG. 10 shows that the pseudo-noise code has a phase δ from the spread data signal.
Digital DLL shown in FIG.
FIG.

11 is an output waveform diagram of the first and second square detectors shown in FIG. 4 in the state of FIG. 10;

[Explanation of symbols]

 23 Despread Correlator 24 Reference Clock Oscillator 25 Frequency Converter 34 Synchronizer 36 Information Demodulator 41 Similar Noise Code Generator 42 Early Correlator 43 Delayed Correlator 44 Delay Circuit 45 Subtractor 46 Voltage Control Encoder 47 Judgment Unit 48 Controller Reference Signs List 100 input line 104 data demodulator 106 band-pass filter 107 square detector 109 band-pass filter 110 square detector 201 information modulator 341 similar noise code generator 342 control circuit 400 input line 402 data demodulator 421 multiplier 422 band-pass filter 423 Square detector 431 Multiplier 432 Bandpass filter 433 Square detector 471 Look-up table memory storage 472 Comparator

Claims (10)

[Claims] 1. A digital delay lock loop for tracking a frequency and a phase of a spread data signal received by a receiver of a spread spectrum communication system, comprising: Supplying the reference pseudo-noise code to a despreading correlator of a receiver of a spread spectrum communication system, wherein the phase of the reference pseudo-noise code whose phase is set to be earlier and later, respectively, A pseudo-noise code generator for generating a delayed pseudo-noise code; and generating an early despread data signal based on the early pseudo-noise code generated by the pseudo-noise code generator and the received spread data signal. An early correlator for calculating the magnitude of the early spread data signal; and a delay generator generated by the pseudo noise code generator. A delay correlator that generates a delayed despread data signal based on a pseudo noise code and the received spread data signal, and calculates a size of the generated delayed despread data signal; and The generated reference pseudo-noise code, early pseudo-noise code and delayed pseudo-noise code are respectively delayed by delaying the reference pseudo-noise code, the early pseudo-noise code and the delayed pseudo-noise code by the despreading correlator and the early correlator. A delay circuit for supplying the delayed despread data signal to the delay correlator, and subtracting the magnitude of the early despread data signal from the delay spreader from the magnitude of the delayed despread data signal from the early correlator. A voltage control encoder that is supplied as an input of the difference signal from the subtractor and generates a binary code corresponding to the difference signal; At least one voltage value and a binary code corresponding to the at least one or more voltage values are stored, and the binary code is received from the voltage control encoder. And a determination unit that compares the minimum threshold value and the maximum threshold value, and outputs a comparison result signal based on the result of the comparison. A digital delay lock loop for tracking a frequency and a phase of a spread data signal received by a receiver of a spread spectrum communication system, the control section comprising: a control unit for controlling a phase of each pseudo noise code. 2. The method according to claim 1, wherein the minimum threshold value and the maximum threshold value are within an allowable range of a phase deviation of the reference pseudo noise code generated by the pseudo noise code generator with respect to the received spread data signal. The digital delay locked loop according to claim 1. 3. The first multiplier for multiplying the early pseudo-noise code generated by the pseudo-noise code generator and the received spread data signal to generate a first multiplied signal, and A first multiplier for squaring the first multiplied signal from the first multiplier to generate a magnitude of the first multiplied signal;
The digital delay locked loop according to claim 1, further comprising a square detector. 4. The apparatus according to claim 1, wherein the early correlator further includes a first band-pass filter for removing a high-frequency noise component included in the first multiplied signal from the first multiplier. Digital delay lock loop as described. 5. The second multiplier for multiplying the delayed pseudo-noise code generated by the pseudo-noise code by a received spread data signal to generate a second multiplied signal, and the second multiplier for generating a second multiplied signal. 2. The digital delay locked loop according to claim 1, further comprising a second square detector that receives the input of the second multiplication signal from a multiplier and generates a magnitude of the second multiplication signal. 6. The apparatus according to claim 1, wherein the delay correlator further includes a second band-pass filter for removing a high-frequency noise component included in the second multiplied signal from the second multiplier. Digital delay lock loop as described. 7. A first delay unit, wherein the delay circuit delays a reference pseudo-noise code generated by the pseudo-noise code generator and supplies a delayed reference pseudo-noise code to the despreading correlator; A second delay unit that delays the early pseudo noise code generated by the pseudo noise code generator and supplies the delayed early pseudo noise code to the early correlator; and a delayed pseudo noise code generated by the pseudo noise code generator. 3. The digital delay locked loop according to claim 1, further comprising: a third delay unit for providing a delayed pseudo noise code to the delay correlator by delaying the delay pseudo noise code. 8. The method of claim 1, wherein the magnitude of the early spread data signal and the delayed despread data signal and the difference signal are one of a voltage and a current. Digital delay lock loop. 9. When the binary code from the voltage control encoder is equal to or greater than the minimum threshold and equal to or less than the maximum threshold as a result of the comparison, the determination unit outputs the phase-on determination signal. When the binary code is less than the minimum threshold, the phase advance determination signal is output, and when the binary code is greater than the maximum threshold, the phase retard determination signal is output. 2. The digital delay lock loop according to 1. 10. A look-up table memory for storing a binary code used for the control voltage encoder and a voltage value corresponding to the binary code, wherein the binary code from the voltage control encoder is stored. 2. The digital delay locked loop according to claim 1, further comprising: a comparator for comparing the minimum and maximum thresholds with each other and outputting a comparison result signal based on a result of the comparison.