JPH098989A - Parallel data transfer system and electronic device - Google Patents

Abstract

PURPOSE: To increase the data transfer speed of data to a host computer by repeating write/read of parallel data to/from 1st and 2nd transmission buffers in pairs provided to an image scanner alternately and consecutively. CONSTITUTION: At first a write time to write image data by 8 bytes to a 1st transmission buffer 54 is required and each period from a timing T1 to a timing T2 and from the timing T2 to a timing T3 is an image data transmission time by 8 bytes, the read processing from the 1st transmission buffer 54 and a 2nd transmission buffer 55 is executed consecutively and alternately and no write processing time is included, then the data transmission speed is increased in response to the read processing time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel data transfer system and an electronic device provided with a host computer and an electronic device connected to the host computer with a connecting cord, and particularly to a transmission command transmitted from the host computer. The present invention relates to a device for increasing the transfer rate of data transmitted from an electronic device to a host computer in response to a signal.

[0002]

2. Description of the Related Art Conventionally, an image scanner as an electronic device optically reads image information drawn on a document by a reading mechanism to create image data, and transmits parallel image data to a host computer such as a personal computer. In general, a Centronics connector and a Centronics communication port are provided so that data can be transmitted to a host computer via a connecting cord. On the other hand, the host computer is provided with a Centronics connector and a Centronics communication port so that the parallel image data transmitted from the image scanner via the connecting cord can be received, and further created image data, The image data transmitted from the image scanner can be transmitted to, for example, a laser printer.

Recently, a Centronics communication system using a parallel interface of IEEE1284, which is a communication technology of the American Institute of Electrical and Electronics Engineers, has been put into practical use. That is, for example, in a data transfer system in which a host computer and an image scanner are connected by a connecting cord, image data of a document read by the image scanner is
When transmitting to the host computer byte by byte using the IEEE1284 parallel interface, as shown in FIG. 9, when the host busy signal H.Busy from the host computer falls at timing T10, the image scanner , Its host busy signal
In response to the fall of H.Busy, one byte of the image data of one line read in advance (“H”)
Only the 0th bit data D0 of the level is read out from the image data memory, once written in the transmission buffer having a buffer capacity of 1 byte, and at the same time read out and data is set, and output to the transmission circuit at timing T11. At the same time, the printer clock signal P.CLK falls.

Then, in response to the fall of the printer clock signal P.CLK, the host computer reads the parallel 1-byte image data transmitted from the image scanner and simultaneously processes the data, and the data processing is completed. At timing T12, the host busy signal is issued to command the transfer of the next 1-byte parallel data.
Turn off H.Busy. As described above, the host computer can accurately read the image data of each byte transmitted in the same manner hereinafter by the so-called handshake method.

[0005]

As described above, in the data transfer system in which the host computer and the image scanner are connected by the connecting cord, the image data is transmitted by using the so-called handshake method IEEE 1284 Centronics communication method. In this case, as shown in FIG. 9, on the image scanner side, from the timing T10 when the host busy signal H.Busy falls to the timing T11 when the data set is completed and the printer clock signal P.CLK falls, A write processing time (for example, about 10 μs) for writing one byte of image data read from the data memory into the transmission buffer and a read processing time (for example, about 20 μs) for reading the written data and setting the data. Processing time t10 for the added data set (for example, about 30 μ ) It requires. That is, it takes about 30 μs for each image data of 1 byte to be transmitted. Therefore, when transmitting grayscale data or color data having a data amount of several megabytes (MB),
Although the reliability of the transmission data is high, there is a problem that a long transmission time is required.

An object of the present invention is to alternately write and read parallel data to and from a pair of first and second transmission buffers provided in an electronic device, thereby increasing the data transfer rate to a host computer. It is an object of the present invention to provide a parallel data transfer system and electronic equipment capable of increasing the speed.

[0007]

A parallel data transfer system according to a first aspect of the present invention includes a host computer capable of transmitting a transmission command signal and receiving parallel data transmitted in response to the signal, and the host computer. In a parallel data transfer system, comprising: an electronic device connected to a computer and transmitting parallel data to be transferred, which is stored in a data memory, to a host computer in a predetermined amount in response to a transmission command signal. A first transmission buffer and a second transmission buffer that alternately receive the data read from the memory, and a predetermined amount of data in the data memory are read and written to the second transmission buffer during reading from the first transmission buffer. Write means for writing to the first transmission buffer during reading from the transmission buffer, and in response to the transmission command signal From the first transmission buffer and a second transmission buffer reads out data alternately, in which a reading transmission means for transmitting to the host computer.

According to a second aspect of the present invention, there is provided the parallel data transfer system according to the first aspect of the invention, wherein the electronic device is an image scanner for reading an image of an original document, and the transmission command signal is a host busy signal transmitted from a host computer. Use the falling and rising timings of. A parallel data transfer system according to claim 3 is
In the invention of claim 1 or 2, the first transmission buffer and the second transmission buffer are composed of a pair of buffers having an equal capacity of at least 1 byte or more.

According to another aspect of the present invention, there is provided an electronic device, which transmits a transmission command signal and transmits parallel data transmitted in response to the signal, to the host computer in the electronic device connected to the host computer capable of receiving the parallel data. Data memory for storing the data of, and data read from the data memory are alternately written, and the data is alternately read in response to a transmission command signal from the host computer. A buffer and writing means for reading a predetermined amount of data from the data memory, writing the data in the second transmission buffer during reading from the first transmission buffer, and writing in the first transmission buffer during reading from the second transmission buffer; In response to the transmission command signal, data is alternately read from the first transmission buffer and the second transmission buffer, and the data is read by the host computer. It is obtained by a reading transmission means for signals.

[0010]

In the parallel data transfer system according to the first aspect, the electronic device is provided with the first transmission buffer and the second transmission buffer which alternately receive the data read from the data memory, and the writing means is the data memory. Data is read by a predetermined amount, written into the second transmission buffer during reading from the first transmission buffer, and written into the first transmission buffer during reading from the second transmission buffer. Further, the read transmission means, in response to the transmission command signal, alternately reads the data from the first transmission buffer and the second transmission buffer,
Send to host computer.

That is, at first, it takes a write time to write data in either the first transmission buffer or the second transmission buffer, but after that, the written data is written in the first transmission buffer.
While the data is being read from either the transmission buffer or the second transmission buffer, the data is written to either the second transmission buffer or the first transmission buffer, so that the first reading is completed. The process of writing the data to the transmission buffer or the second transmission buffer and the process of reading the data from the other second transmission buffer or the first transmission buffer, which has been written, are simultaneously executed. Therefore, the read processing can be processed by hardware by using, for example, a DMA controller, and thus the control program is not required and the data transfer speed can be increased.

In the parallel data transfer system according to a second aspect of the present invention, the same operation as that of the first aspect is achieved, but the electronic device is an image scanner for reading an image of an original document, and the electronic device is an image scanner, and the transmission command signal is sent from a host computer. Since the timing of the falling edge and the rising edge of the transmitted host busy signal is used, when the image data of the original is transmitted in parallel data by the normal Centronics communication method, not only at the falling edge of the host busy signal but also at the rising edge timing. Data can be transmitted to the host computer, and the image reading process of an original by an image scanner and the image data transfer speed can be further increased.

In the parallel data transfer system according to claim 3, the same operation as that of claim 1 or 2 is achieved, but the first transmission buffer and the second transmission buffer are
Since it is composed of a pair of buffers having an equal capacity of at least 1 byte or more, when the write processing time of 1-byte data to the first transmission buffer and the second transmission buffer is substantially equal to the read processing time, the first transmission The writing process and the reading process for the buffer and the second transmission buffer can be alternately and continuously performed in substantially the same processing time, and the data transmission speed is increased according to the writing processing time (reading processing time). can do.

Further, when the reading process is slower than the writing process of the 1-byte data, the reading processes from the first transmission buffer and the second transmission buffer are continuously and alternately executed. The speed can be increased according to the read processing time. On the other hand, when the writing process is slower than the reading process of the 1-byte data, the writing processes to the first transmission buffer and the second transmission buffer are continuously executed alternately, and the data transmission speed is The speed can be increased according to the write processing time.

In the electronic apparatus according to the fourth aspect, the data to be transmitted to the host computer is stored in the data memory, the data read from the data memory is written alternately, and the written data is alternated. A first transmission buffer and a second transmission buffer to be read out are provided, and the writing means reads the data in the data memory by a predetermined amount and writes the data in the second transmission buffer during the reading from the first transmission buffer. Write to the first transmit buffer while reading from the transmit buffer. Further, the read transmission means, in response to the transmission command signal, alternately reads the data from the first transmission buffer and the second transmission buffer and transmits the data to the host computer.

That is, at first, it takes a write time to write data into either the first transmission buffer or the second transmission buffer, but after that, the written data is written into the first transmission buffer.
While the data is being read from either the transmission buffer or the second transmission buffer, the data is written to either the second transmission buffer or the first transmission buffer, so that the first reading is completed. The process of writing the data to the transmission buffer or the second transmission buffer and the process of reading the data from the other second transmission buffer or the first transmission buffer, which has been written, are simultaneously executed. Therefore, the read processing can be processed by hardware by using, for example, a DMA controller, and thus the control program is not required and the data transfer speed can be increased.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, as shown in FIG. 1, the present invention is applied to an image data transfer system 1 in which a host computer 10 and an image scanner 30 as an electronic device for reading an image of an original are connected by a connecting cord 2. belongs to.

First, the control system of the host computer 10 is basically constructed as shown in the block diagram of FIG. The input / output interface 22 of the controller 17 is a CRT controller (CRT) that outputs character and symbol data to a CRT type display (CRTD) 12.
C) 13 and floppy disk drive (FD
D) A floppy disk controller (FDC) 15 for driving and controlling the keyboard 14, a keyboard 16 and the like are connected.

The control device 17 basically includes a CPU 18 and
This CPU 18 has a control bus 2 such as an 8-bit data bus.
An input / output interface 22 connected via 3;
An R that stores various data processing controls and a control program that performs transmission / reception processing of image data in a parallel transfer method based on the IEEE 1284 communication interface
OM 19, RAM 20 provided with various memories necessary for data processing, and DMA (Direct Memory Access) for high-speed data transfer without intervention of CPU 18.
It is composed of a controller 21. Further, a transmission / reception circuit 24 having a Centronics communication port capable of transmitting / receiving image data in a parallel transfer system based on an IEEE 1284 communication interface is connected to the control bus 23 between the control bus 23 and the image scanner 30. . The Centronics connector 11 is connected to the transmission / reception circuit 24.
1 to the image scanner 30 via the connecting cord 2.
Is connected.

On the other hand, as shown in FIG. 2, the image scanner 30 includes a document table 3 on which a plurality of documents can be stacked and placed.
2 is provided inside the main body frame 31 for picking up one by one from a lower original among a plurality of originals stacked on the original table 32 and discharging the originals through a predetermined conveyance path. A document transport mechanism (not shown) is provided, and a large number of CCDs are provided in the middle of the transport path for reading the image of the document.
A reading sensor 40 (see FIG. 4) in which (charge coupled devices) are arranged in a row is provided. Furthermore, the body frame 31 has
A power switch 34 is provided, an operation panel 33 is provided on the upper surface of the main body frame 31, and the operation panel 33 is provided.
Is provided with operation switches such as a copy command switch and the like.

Next, the control system of the image scanner 30 is
It is configured as shown in the block diagram of FIG. Output from the switches of the operation panel 33 and the reading sensor 40 to the input / output interface 55 of the controller 50,
S for converting the serial image data binarized (digital data) by the binarization circuit 41 into parallel image data
The / P converter 42, the drive circuit 44 for the document feed motor 43 that drives the document transport mechanism, and others are not shown,
A light source for reading a document, a cover open detection switch, etc. are connected.

The control device 50 basically has a CPU 51.
An input / output interface 57 connected to the CPU 51 via a control bus 58 such as a data bus;
M52 and RAM53 and its image data memory 53a
A pair of the first transmission buffer 54 and the second transmission buffer 55 which alternately receive the image data read from the memory and store the image data of an equal capacity of 8 bytes;
It is composed of a DMA controller 56 for high speed operation without the intervention of U51. Here, these first and second
The transmission buffers 54 and 55 are each composed of a FIFO memory (first-in first-out memory) having an equal capacity of 8 bytes.

Here, the DMA controller 56 has a read buffer pointer for alternately switching the first transmission buffer 54 and the second transmission buffer 55 to read image data, and a fall and rise of the host busy signal H.Busy. Various registers such as a read address pointer that is incremented at each timing are provided.
A controller control unit is provided. A transmission / reception circuit 59 having a Centronics communication port capable of transmitting / receiving image data in a parallel transfer system based on the IEEE 1284 communication interface is connected to the control bus 58 between the control bus 58 and the host computer 10. . The Centronics connector 35 is connected to the transmission / reception circuit 59.
5 to the host computer 1 via the connecting cord 2.
0 is connected.

In the ROM 52, a drive control program for driving the original feeding mechanism, and a control program for image data transmission control, which will be described later and peculiar to the present application, for transmitting image data in a parallel transfer system based on the communication interface of IEEE1284. Etc. are stored. RAM
The 53 is provided with various memories necessary for reading the image data, such as an image data memory 53a for storing the image data for one line read by the reading sensor 40.

Here, based on the IEEE 1284 communication interface described above, a control signal used when transmitting parallel image data of each byte from the image scanner 30 to the host computer 10 via the connection code 2. Will be briefly described. An active signal ACT, a host clock signal H.CLK, a host busy signal H.Busy, etc. are used as control signals output from the host computer 10 to the image scanner 30, and the active signal ACT activates the communication interface of IEEE1284 and Set the data transfer direction by the data bus, and the host clock signal H.CLK is
The command data transfer timing is instructed, and the host busy signal H.Busy is used to instruct the data transfer timing.

On the other hand, as control signals output from the image scanner 30 to the host computer 10, a printer clock signal P.CLK, a printer busy signal P.Busy, a data avail signal DAV, and a select (X flag) signal XFLG.
The printer clock signal P.CLK indicates the timing of data transfer and the printer busy signal P.CLK.
Busy indicates the busy state of the image scanner 30, and the data avail signal DAV indicates that transfer data exists.

Next, the controller 5 of the image scanner 30.
Regarding the image data transmission control routine executed at 0,
This will be described based on the flowcharts of FIGS. still,
Reference numeral Si (i = 10, 11, 12, ...) In the drawing represents each step. When the image scanner 30 is powered on, after various initialization processes are executed, the image data transmission control shown in FIG. 5 is started. First, in the idle state, whether or not an image data transmission command is received ( S10:
No), is repeatedly determined. Then, when the image data transmission command is received from the host computer 10 (S10: Yes), the image transfer data obtained by adding header information to the image data for one line transferred from the reading sensor 40 is subjected to the image reading control (not shown). Creation process is executed, and the image transfer data is created in RAM.
It is stored in the image data memory 53a of 53 (S11).

Next, of the image transfer data stored in the image data memory 53a, the first 1-byte data is read and first written in the first transmission buffer 54 (S12). Next, when the first transmission buffer 54 is not in the buffer full state (S13: No), when the written data is not the page end code for instructing the end of the image data for one page (S14: No). If there is further image transfer data to be transmitted to the image data memory 53a (S15: Yes), S12 to S15 are repeatedly executed.

When all the image data in the image data memory 53a have been written in the first transmission buffer 54 (S15: No), the image transfer data for the next one line is created (S11). . Then, when 8 bytes of image data is written in the first transmission buffer 54 and the first transmission buffer 54 is in the buffer full state (S13: Yes), the terminal count from the DMA controller 56 that controls the data transfer. On the basis of the DMA end signal according to the above, it is judged whether or not the image data read from the second transmission buffer 55, that is, the data transmission is completed (S16), and when it is not completed (S16: N
o), wait until the transmission is completed.

When the transmission is completed (S
16: Yes), the read start address of the image data to be transmitted written in the first transmission buffer 54 is set in the register of the DMA controller 56, and data transmission is instructed (S17). As a result, the 8-byte image data written in the first transmission buffer 54 by the DMA controller 56 is transferred to the host computer 10.
The read pointer is incremented by one at each falling and rising timing of the host busy signal H.Busy transmitted from the host busy signal H.Busy, so that each byte designated by the read pointer is sequentially transmitted to the host computer 10. On the other hand, at the same time as this transmission processing, the next S18 to S24
Thereby, the writing of the image data to the other second transmission buffer 55 is executed.

That is, the 1-byte data next to the last data written in the first transmission buffer 54 is read from the image data memory 53a and written in the second transmission buffer 55 (S18). Next, similarly, when the second transmission buffer 55 is not in the buffer full state (S19: N
o), when the written data is not the page end code (S20: No), and when there is image data to be transmitted to the image data memory 53a (S21: Yes).
), S18 to S21 are repeatedly executed. by the way,
For all the image data in the image data memory 53a,
When the writing to the second transmission buffer 55 is completed (S21: No), the image transfer data for the next one line is created (S22), and the process returns to S18.

When 8 bytes of image data has been written in the second transmission buffer 55 and the second transmission buffer 55 is in the buffer full state (S19: Yes), D
Based on the DMA end signal from the MA controller 56, it is judged whether or not the transmission of the image data of the first transmission buffer 54 is completed (S23), and when it is not completed (S23: No), the transmission is completed. Wait until. And
When the transmission is completed (S23: Yes), the read start address of the image data to be transmitted written in the second transmission buffer 55 is set in the register of the DMA controller 56 and the data transmission is instructed ( S2
4), S12 and subsequent steps are repeatedly executed.

As a result, the 8-byte image data written in the second transmission buffer 55 by the DMA controller 56 is generated at every fall and rise timing of the host busy signal H.Busy transmitted from the host computer 10. By incrementing the read pointer by one, each byte designated by the read pointer is sequentially transmitted to the host computer 10. On the other hand, at the same time as this transmission process, the writing of the image data to the first transmission buffer 54 is repeatedly executed by the steps S11 to S15.

Next, the operation of the image data transmission control for transmitting the image data of the original read by the image scanner 30 to the host computer 30, that is, the writing processing to the first transmission buffer 54 and the second transmission buffer 55,
Read processing (transmission processing) by the DMA controller 56
The operation of and will be described based on FIGS. 7 and 8. Here, the fall and rise of the host busy signal H.Busy from the host computer 10 is recognized as a transmission command signal, and the printer clock signal P.CLK output from the image scanner 30 transmits image data. Inverted at the timing, and printer busy signal
P.Busy becomes "H" level only during the period from the reception of the transmission command signal represented by the host busy signal H.Busy to the transmission timing of the image data.

First, when the read processing (transmission processing) is slower than the write processing for both transmission buffers 54 and 55,
As shown in FIG. 7, from the timing T0 when the transmission command signal of the host busy signal H.Busy which is inverted to the first "L" level is received, first, the image data of 8 bytes is written in the first transmission buffer 54. From the timing T1 when the processing is executed and the writing is completed, the read processing of the image data written in the first transmission buffer 54 is executed by the DMA controller 56 and the second transmission buffer 5 is also executed.
The writing process of 8 bytes of image data to 5 is executed.

Similarly, the timing T at which the reading is completed is completed.
From 2, the reading process of the image data written in the second transmission buffer 55 is executed, and the writing process of the 8-byte image data in the first transmission buffer 54 is executed. That is, first, it takes a writing time to write 8 bytes of image data in the first transmission buffer 54, but after that, from timing T1 to timing T2,
Further, each period from the timing T2 to the timing T3 is an image data transmission time of 8 bytes, and the reading process from the first transmission buffer 54 and the second transmission buffer 55 is continuously and alternately executed. Since the write processing time is not included, the data transmission speed can be increased according to the read processing time.

On the other hand, when the writing process is slower than the reading process for both transmission buffers 54 and 55, as shown in FIG. 8, the host busy signal H.Bu which is inverted to the "L" level is used.
From the timing T5 when the transmission command signal of sy is received, first, the writing processing of the image data of 8 bytes is executed in the first transmission buffer 54, and the writing is completed at the timing T.
From 6, the read process of the image data written in the first transmission buffer 54 is executed by the DMA controller 56, and the write process of the 8-byte image data in the second transmission buffer 55 is executed.

Similarly, the timing T when the writing is completed
From 7, the reading process of the image data written in the second transmission buffer 55 is executed, and the writing process of the 8-byte image data in the first transmission buffer 54 is executed. That is, first, it takes a writing time to write image data of 8 bytes into the first transmission buffer 54, but after that, from timing T6 to timing T7, and from timing T7 to timing T8. The period is an image data transmission time of 8 bytes, and these first transmission buffer 54 and second transmission buffer 5
Since the write processing to 5 is continuously and alternately executed and the read processing time is not included, the data transmission speed can be increased according to the write processing time.

In this way, the image scanner 30
A pair of first transmission buffers 54 having an equal capacity for bytes
And the second transmission buffer 55 are provided, and it takes a writing time to first write 8 bytes of image data into the first transmission buffer 54, but after that, the first transmission buffer 5
The image data in the image data memory 53a is written in the second transmission buffer 55 during the reading of the image data from the image data No. 4, and the image data in the image data memory 53a is read during the reading of the image data from the second transmission buffer. Are written in the first transmission buffer 54. Therefore, the DMA controller 5
6, the first transmission buffer 54 and the second transmission buffer 5
Since the image data is read from 5 alternately, the host computer 1 does not only have the timing of the fall of the host busy signal H.Busy but also the timing of the rise thereof.
The image data can be transmitted to 0, and the image data transfer speed can be increased.

Incidentally, the control device 50 of the image scanner 30.
First transmission buffer 54 and second transmission buffer 55 provided in
To be composed of a pair of buffers of equal capacity of 1 byte or more, or to transmit the image data from the image scanner 30 in response to the fall or rise of the host busy signal H.Busy from the host computer 30. For example, various modifications may be made to the above-described embodiment based on existing technology or technology obvious to those skilled in the art.

[0041]

According to the parallel data transfer system of the first aspect, in the data transfer system including the host computer and the electronic device, the electronic device is provided with the first and second transmission buffers, the writing means, and the reading means. And transmitting means for writing to the second transmission buffer during reading from the first transmission buffer, writing to the first transmission buffer during reading from the second transmission buffer, and alternating from the first transmission buffer and the second transmission buffer. Since the data is read, a writing time for writing the data into either the first transmission buffer or the second transmission buffer is required at first, but after that, the written data is transmitted to the first transmission buffer and the second transmission buffer. Writing data to either the second transmission buffer or the first transmission buffer of the other while reading from either one of the buffers Et al., The write processing of data to the first transmission buffer or the second transmission buffer read is completed,
The data read processing from the other second transmission buffer or the first transmission buffer on which the writing has been completed is executed at the same time, and the read processing can be processed by hardware by using, for example, a DMA controller. Therefore, the control program is not required and the data transfer rate can be increased.

According to the parallel data transfer system of the second aspect, the same effect as that of the first aspect is obtained, but the electronic device is an image scanner for reading an image of an original document, and the host computer is used as the transmission command signal. Since the fall and rise timings of the host busy signal transmitted from are used, when the image data of the original is parallel data communicated by the normal Centronics communication method, not only the fall and rise timings of the host busy signal In this case, data can be transmitted to the host computer, and the image data transfer speed can be further increased.

According to the parallel data transfer system of the third aspect, the same effect as that of the first or second aspect is obtained, but the first transmission buffer and the second transmission buffer have an equal capacity of at least 1 byte or more. Of the first transmission buffer and the second transmission buffer, the write processing time of the 1-byte data and the read processing time of the 1-byte data are substantially equal to each other. The data writing process and the data reading process can be alternately and continuously performed, and the data writing time can be reliably eliminated. Also,
Similarly, when the writing processing time of 1-byte data is shorter than the reading processing time, the data writing time can be surely eliminated. On the other hand, when the writing processing time of 1-byte data is longer than the reading processing time, the reading processing time is only extended by the reading waiting time until the writing is completed.

According to the electronic device of the fourth aspect, the data memory, the first and second transmission buffers, the writing means, and the reading transmission means are provided, and the second transmission is performed during the reading from the first transmission buffer. Since the data is written to the buffer and written to the first transmission buffer during reading from the second transmission buffer, and the data is alternately read from the first transmission buffer and the second transmission buffer, the first transmission buffer or the second transmission buffer is read first. It takes a write time to write data to either one, but after that, while the written data is being read from either the first transmission buffer or the second transmission buffer, the other second transmission buffer is read. And the first transmission buffer, the data writing is executed, so that the data writing process to the first transmission buffer or the second transmission buffer whose reading has been completed is performed. The data read processing from the other second transmission buffer or the first transmission buffer on which the writing has been completed is executed at the same time, and the read processing can be processed by hardware by using, for example, a DMA controller. Therefore, the control program is not required and the data transfer rate can be increased.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image data transfer system including a host computer and an image scanner according to an embodiment of the present invention.

FIG. 2 is a perspective view of an image scanner according to an exemplary embodiment of the present invention.

FIG. 3 is a block diagram of a control system of a host computer.

FIG. 4 is a block diagram of a control system of the image scanner.

FIG. 5 is a part of a schematic flowchart of a routine of image data transmission control.

FIG. 6 is a part of a schematic flowchart of a routine of image data transmission control.

FIG. 7 is a time chart of various signals when the reading process (transmission process) is slower than the writing process.

FIG. 8 is a time chart of various signals when the writing process is slower than the reading process.

FIG. 9 is a time chart of control signals and transmission data according to a conventional technique.

[Explanation of symbols]

 1 Image Data Transfer System 10 Host Computer 30 Image Scanner 50 Control Device 51 CPU 52 ROM 53 RAM 53a Image Data Memory 54 First Transmission Buffer 55 Second Transmission Buffer

Claims (4)

[Claims] 1. A host computer capable of transmitting a transmission command signal and receiving parallel data transmitted in response to the signal, and a parallel transfer target connected to the host computer and stored in a data memory. Parallel data transfer system including an electronic device that transmits a predetermined amount of data to a host computer in response to a transmission command signal, the electronic device alternately receiving data read from the data memory. The buffer, the second transmission buffer, and the data in the data memory are read by a predetermined amount each, and the first data is read.
Writing means for writing to the second transmission buffer during reading from the transmission buffer and writing to the first transmission buffer during reading from the second transmission buffer; and a first transmission buffer and a second transmission buffer in response to the transmission command signal.
A parallel data transfer system, comprising: a reading and transmitting means for alternately reading data from a transmission buffer and transmitting the data to a host computer. 2. The electronic device is an image scanner for reading an image of a document, and uses the timing of falling and rising of a host busy signal transmitted from a host computer as the transmission command signal. Item 1. The parallel data transfer system according to Item 1. 3. The parallel data transfer system according to claim 1, wherein the first transmission buffer and the second transmission buffer are composed of a pair of buffers having an equal capacity of at least 1 byte or more. . 4. An electronic device connected to a host computer capable of transmitting a transmission command signal and receiving parallel data transmitted in response to the signal, the data memory storing data to be transmitted to the host computer. A first transmission buffer and a second transmission buffer in which the data read from the data memory are written alternately, and the data is read alternately in response to a transmission command signal from the host computer; Read the data by a predetermined amount and
Writing means for writing to the second transmission buffer during reading from the transmission buffer and writing to the first transmission buffer during reading from the second transmission buffer; and a first transmission buffer and a second transmission buffer in response to the transmission command signal.
An electronic device, comprising: a reading and transmitting unit that alternately reads data from a transmission buffer and transmits the data to a host computer.