JPH0981465A - Main storage controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a storage controller which has high reliability and is capable of performing a high speed operation. SOLUTION: The operations of first and second bus switches are controlled by a memory check controller 4 and a bus switch controller 5 so that plural storage modules 11 to 13 may be provided and an ECC circuit 6 may perform an error detection correction for the data of the storage modules except the storage module to which an MPU 1 performs access. When a parity error is produced in the data of the storage module to which the MPU 1 performs access, the operation of the MPU 1 becomes 'WAIT' state. The controller 4 saves the data from the storage module for which an error check is performed in a register, executes the correction of the data in which the parity error is produced, outputs the corrected data to the MPU 1 and stores the data in the storage module. Subsequently, the controller 4 recovers the data saved in the register and restarts the error check of the storage module for which the error check is interrupted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to parity check and ECC in data transfer between an MPU and a main memory.
The present invention relates to a main memory control device for increasing the reliability of data.

[0002]

2. Description of the Related Art Computer systems are required to have higher reliability and higher speed as the amount of information processing increases and the service form develops into online real-time processing. For this purpose, a storage controller having high-speed data storage and input / output operations and high reliability is required.

A parity check is generally used for detecting an error bit in data transfer between the MPU and the main memory, and an ECC check is generally used for detection / correction. That is, as shown in FIG. 5, the data requested to be read from the MPU 26 is read from the storage module 20, and after the error detection and correction by the ECC circuit 28,
It is supplied to the MPU 26.

Further, in JP-A-62-242258 and JP-A-55-77097, as shown in FIG. 6, a storage module 20 in which error detection / correction bits and parity bits coexist is used, and parity is used. Check circuit 27
Therefore, the error detection / correction circuit 28 corrects the data only when the parity error is detected.
The corrected data is supplied to the MPU 26. As a result, high reliability and high-speed operation at the time of partial writing are realized at the same time.

[0005]

Problems to be Solved by the Invention
There are various types of correction circuits, but the main memory requires data reliability, so 1-bit error correction
A 2-bit error detection code is often used. However, even if this error detection / correction code is used, time is required for error detection / correction, which is a major obstacle to speeding up data reading of the storage device.

On the other hand, the method of detecting an error by the parity check can speed up the access time during the normal operation, but since only error detection is performed, the system may be down due to a parity error. Therefore, a highly reliable main memory device cannot be realized. This is because when a parity error is detected, error detection or content reporting and storage is performed, and the subsequent operation is temporarily terminated.

Further, in the conventional example shown in FIG. 6, M
Only the data accessed by the PU corrects the error data. Therefore, if an error occurs in the data that is not accessed, the error can be detected and corrected if the data is accessed with a small number of errors. However, if the non-accessed period becomes long, more error data may be generated and the number of errors may increase. When the number of error data is large, there is a high possibility that the error correction of the data cannot be performed and the reliability of the system is deteriorated.

An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to realize a storage controller having high reliability and high-speed operation.

[0009]

In order to achieve the above object, the present invention is configured as follows. In the main memory control device, a plurality of main memory modules in which data, error detection / correction bits, and parity bits are stored, a main processor that processes information read from the main memory module, and parity of information read from the main memory module. A parity check means for performing a check, an error detection and correction means for performing error detection and correction of information read from the main storage module, and a bus switch for connecting any of the plurality of main storage modules to the main processor or the error detection and correction means. , A memory check controller that controls the error detection / correction means to detect and correct information in any of the storage modules of the plurality of main storage means, an access request from the main processor, and information read from the memory check controller Main on request A storage module that connects to processors, as a main memory module connected to the memory check controller are different, comprises a bus switch controller for controlling the operation of the bus switch, the.

Preferably, in the main memory control device, the main processor interrupts the information processing operation when the parity check means detects that the information read from the main memory module has a parity error, and the memory The check controller stops reading information from the main memory module during the error detection and correction operation, executes error detection and correction of the information in which the parity error has occurred, supplies the corrected information to the main processor, and generates the parity error. The corrected information is stored in the main memory module, and the information reading from the main memory module that stopped the information reading is restarted.

Further, preferably, in the above main memory control device, the memory check controller has an error counter, counts the number of times of occurrence of a parity error for each of the plurality of main memory modules, and the counted number is equal to or more than a predetermined number. Is supplied to the main processor and the bus switch controller, and the bus switch controller selects the storage module whose count number is equal to or more than a predetermined number according to the command signal from the memory check controller. Stop things.

Further, preferably, the main memory control device further comprises a replacement judging section for judging whether or not the storage module whose count number has become a predetermined number or more is replaced with a new storage module, The replacement determination unit notifies the bus switch controller that the storage module has been replaced.

[0013]

A main memory control device using a plurality of main memory modules in which error detection / correction bits and parity bits coexist with data, and an error detection / correction circuit is provided in parallel with main memory access of an MPU (main processor). It is a storage device that is operated.

The memory check controller always reads the information from the storage module of the MPU in parallel with it.
The information in the plurality of storage modules is sequentially read to perform error detection / correction. By checking the constant storage module, the maximum value of the existence period of 1-bit error is limited, the probability of error of 2 bits or more can be reduced, and the reliability of the system can be improved. Since the storage modules have independent buses, they can operate in parallel for access from the MPU and access from the memory check controller, except when the same storage module is accessed, with high reliability. Moreover, it becomes possible to simultaneously perform high-speed operation.

[0015]

Embodiments of the present invention will now be described with reference to the accompanying drawings. FIG. 1 is a schematic configuration diagram of a storage control device according to a first embodiment of the present invention. In FIG. 1, the storage control device includes an MPU (main processor) 1, an address latch circuit 2, a parity check circuit 3, a memory check controller 4, a bus switch controller 5, and E.
CC (error detection and correction) circuit 6 and first bus switch 8
A second bus switch 9, a storage module A11,
The storage module B12 and the storage module C13 are provided.

In the storage modules 11, 12, and 13, the error detection / correction bit and the parity bit coexist with the data, and the error detection / correction bit, the parity bit, and the data are written when the data is written or read. Output at the same time.

Further, the address latch circuit 2 includes the MPU 1
Each time the memory module 11, 12, or 13 is accessed, the address to be accessed is latched via the address bus 23, and the data after the error correction is written back to the corresponding memory module 11, 12 or 13. use. The parity check circuit 3 checks the parity of the data read by the MPU 1 and, if there is a 1-bit error, generates a WAIT signal 21 to the MPU 1 to request time for correcting the 1-bit error. .

The memory check controller 4 is an ECC
The circuit 6 is used to check the data in each module in order from the smallest address of the storage module A11, the storage module B12, and the storage module C12, and when an error is detected, the error is corrected. Further, the bus switch controller 5 controls the first bus switch 8 to connect the bus to the storage module A11 when the MPU 1 accesses the storage module A11, for example. When accessing the storage module B12, the bus switch controller 5 releases the connection with the storage module A11 and then connects with the bus of the storage module B12.

For example, the memory check controller 4
Checks the storage module A11 for errors,
1 accesses the storage module B12,
Both these accesses are done by independent buses, so M
There is no overhead in accessing the storage module of PU1. That is, the bus switch controller 5
Since U1 can detect which storage module to access, it controls the second bus switch 9,
Storage module and ECC not accessed by MPU1
The circuit 6 is connected.

When the MPU 1 accesses the storage module B12 and a parity error occurs while reading data, the parity check circuit 3 supplies an error notification signal 22 to the memory check controller 4. Then, the memory check controller 4 uses the ECC
The circuit 6 corrects the data in which the error has occurred, and the MPU 1 takes in the corrected data via the MPU bus 24. In this case, the processing of the MPU 1 is interrupted, but the data to be corrected is stored in the data latch circuit 7,
Since the ECC circuit 6 only has to correct the data latched by the data latch circuit 7, the data correction can be executed without the data access to the storage module.

FIG. 2 is an operation flowchart of the example of FIG. In this flowchart, it is assumed that the MPU 1 is accessing the storage module B12 and the memory check controller 4 is performing an error check of the storage module A11 by the ECC circuit 6.

In step 100 of FIG. 2, the MPU 1
The data read request is started, and in step 101, the address latch circuit 2 latches the address output by the MPU 1. Then, in step 102,
The data latch circuit 7 latches the data read from the storage module B12.

Next, in step 103, the parity check of the data read by the parity check circuit 3 is performed. Then, in step 104, it is checked whether or not there is an error, and if there is no error, the data is M
The processing is sent to PU1 and the processing is completed.

If there is an error in step 104, the process proceeds to step 105, the parity check circuit 3 supplies the WAIT signal 21 to the MPU 1, and the process proceeds to step 201. In step 201, the error memory check controller 4 checks whether or not there is a parity error on the MPU 1 side. If it is a parity error, the process proceeds to step 210, and the memory check controller 4 saves the register in the memory check controller.

Next, in step 211, the address stored in the address latch circuit 2 is fetched. And
In step 212, the data is fetched from the data latch circuit 7, and in step 213, the error is corrected. Next, in step 214, the corrected data is output to the MPU 1 via the bus 24.

Now, returning to step 105, the MPU 1
Cancels the WAIT state and moves to the next processing. Further, the memory check controller 4 proceeds to step 215.
At, the operation of writing back the corrected data to the memory module B is performed based on the address fetched from the address latch circuit 2. At this time, the memory check controller 4
Instructs the bus switch controller 5 to connect the connected storage module to the storage module B12 and perform the write-back operation of the corrected data. After that, the storage module to be connected is set to the storage module A11. Then, in step 216, the memory check controller 4 restores the saved register and continues the error check of the storage module A11.

If no parity error is found in step 201, the process proceeds to step 202. In step 202, the data in the storage module A11 is read out, and in step 203, an ECC check is performed. Then, in step 204, it is determined whether or not there is an ECC error. If there is no ECC error, the process proceeds to step 208.

In this step 208, the address of the data for which the ECC check is executed is the storage module A
If it is the final address of No. 11, if it is the final address, the error check of the storage module A is ended and the error check of the storage module B is started. If it is not the final address, the process proceeds to step 209, the address is incremented, the process returns to step 201, and the error check of the storage module A is performed again.

If there is an ECC error in step 204, the flow advances to step 205 to increase the error count, and in step 206 the data is corrected. Then, in step 207, the corrected data is written back to the storage module A11. Then, it progresses to step 208 and after that, the same operation as the above is performed.

As described above, according to the first embodiment of the present invention, the plurality of storage modules 11, 12, 13 are provided, and the data of the storage module other than the storage module accessed by the MPU 1 is detected as an error. Controlled by the memory check controller 4 to be corrected, M
The ECC operation is executed in parallel with the data processing of PU1. Therefore, the number of errors that occur is suppressed from increasing until the error cannot be corrected, the reliability is high,
In addition, it is possible to realize a storage control device that can operate at high speed.

FIG. 3 is an operation flowchart in the second embodiment of the present invention. In the second embodiment, the device configuration is equivalent to that of the example of FIG. The steps common to the example of FIG. 3 and the example of FIG. 2 are given the same numbers. 3 is different from the example of FIG. 2 in that in the example of FIG. 3, steps 201A to 201C are added between steps 201 and 210 of the example of FIG. Then steps 216A and 216
B is joining.

In the second embodiment, the memory check controller 4 internally includes the storage modules 11, 12,
It has an error counter for each 1-bit error occurrence. When an error occurs more than the specified number of times, the MPU is sent via the bus switch controller 5.
Report to 1. Then, the connection to the bus of the storage module in which the error occurs more than the specified number of times is prohibited, and the connection to the spare storage module is switched.

That is, in step 201 of FIG.
If it is determined to be a parity error, step 201
In step A, the memory check controller 4 counts up the number of times a parity error has occurred for each storage module. Next, in step 201B, the memory check controller 4 determines whether or not the counted-up error count number has reached a predetermined prescribed number. If the specified number of times has been reached, step 201C
Then, the error flag for the corresponding storage module is set to "1". Subsequently, the process proceeds to step 210.
Proceed to. In step 201B, when the error count number has not reached the specified number, the process proceeds to step 210. Thereafter, steps 210 to 216 described above are executed.

Then, from step 216 to step 21
6A, the bus switch controller 5 determines whether the error flag is "1". If the error flag is "1", the process proceeds to step 216B, and the MPU 1 is notified that a parity error has occurred a specified number of times or more in the corresponding storage module. Then, it returns to step 201. In step 216A, the error flag is "1"
If not, the process returns to step 201 without passing through step 216B.

As described above, also in the second embodiment of the present invention, the same effect as in the first embodiment can be obtained, and
Counts the number of parity error occurrences, and M counts the number of parity error occurrences above the specified number.
Since it is configured to notify the PU1, the MPU1 can recognize the fact and execute a procedure such as accessing only another storage module, and the reliability of data processing can be improved.

FIG. 4 is a schematic configuration diagram of the third embodiment of the present invention, in which the same parts as those of the example of FIG. 1 are designated by the same reference numerals. In the example of FIG. 4, a replacement determination unit 25 is added to the example of FIG. In the example of FIG. 4, similarly to the example of FIG. 3, it is determined whether or not the number of occurrences of the parity error has reached the specified number. Then, it is determined whether or not the storage module in which the number of occurrences of the parity error has reached the specified number has been replaced with a new storage module, and if it has been replaced, it is notified to the MPU 1 via the bus switch controller 5. It is configured to do.

That is, in FIG. 4, the storage module 1
Any one of 1, 12, 13 is provided as a spare storage module. Here, the storage module C13 is a spare storage module. In the diagnosis of the storage module A11 or the storage module B12 by the memory check controller 4, when the 1-bit error occurs more than the specified number of times by the counter inside the memory check controller 4, the memory check controller 4 determines the storage module A11 or the storage module B12. Determines that the reliability of the storage module A11 is low and issues an interrupt report to the MPU1.
Transfer to 3.

Then, when the MPU1 tries to access at the address assigned to the storage module A11 after that, the bus switch controller 5 does not connect the physical bus to the MPU1 and the storage module A11 but the MPU1 and the storage module C13. And are connected,
Data transfer is started. As a result, the storage module in which the error has occurred the specified number of times or more is disconnected from the system.

In this case, each storage module is provided with an exchange flag storage area, and the exchange flag is set to "0" when the number of occurrences of parity errors is less than the specified number. Then, when the number of times of occurrence of the parity error becomes equal to or more than the specified number, the exchange judging section 25 sets the exchange flag of the storage module to "1".

The exchange judging section 25 checks the exchange flag for the storage module in which the number of occurrences of the parity error has exceeded the specified number. If the replacement flag is "0", that is, if the storage module is replaced with a new storage module, the replacement determination unit 25 detects this and notifies the MPU 1 via the bus switch controller 5. As a result, the MPU 1 and the bus switch controller 5 recognize that the storage module A11 has been replaced, and start using the replaced storage module.
The error count value in the memory check controller 4 for the replaced new storage module is
It has been returned to "0".

As described above, according to the third embodiment of the present invention, the same effect as the second embodiment can be obtained. Furthermore, according to the third embodiment, it is possible to automatically determine that the storage module has been replaced with a new storage module and automatically return to the operation when the storage module is healthy.

[0042]

Since the present invention is constructed as described above, it has the following effects. The memory check controller is controlled so that the data of a storage module provided with a plurality of storage modules other than the storage module accessed by the MPU is error-corrected, and the ECC operation is executed in parallel with the data processing of the MPU. To be done. Therefore, it is possible to realize a highly reliable storage control device capable of suppressing the increase in the number of errors that occur until the error cannot be corrected and operating at high speed.

If the number of parity error occurrences is counted and the storage module in which the number of parity error occurrences is equal to or greater than the specified number is notified to the MPU,
The MPU recognizes this and can perform a procedure such as accessing only another storage module, and the reliability of data processing can be improved.

Further, if the storage module is constituted so as to automatically judge that the storage module has been replaced with a new storage module and transmit it to the bus switch controller, the storage module will be sound when the storage module is replaced. You can automatically return to the case.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram of a first embodiment of the present invention.

FIG. 2 is an operation flowchart of the example of FIG.

FIG. 3 is an operation flowchart of the second embodiment of the present invention.

FIG. 4 is a schematic configuration diagram of a third embodiment of the present invention.

FIG. 5 is a diagram showing an example of a conventional storage control device.

FIG. 6 is a diagram showing another example of a conventional storage control device.

[Explanation of symbols]

 1 MPU 2 Address Latch Circuit 3 Parity Check Circuit 4 Memory Check Controller 5 Bus Switch Controller 6 ECC Circuit 7 Data Latch Circuit 8 First Bus Switch 9 Second Bus Switch 11 Storage Module A 12 Storage Module B 13 Storage Module C 21 WAIT Signal 22 error notification signal 23 address bus 24 MPU data bus 25 exchange determination unit

Claims (4)

[Claims] 1. A plurality of main memory modules in which data, error detection / correction bits, and parity bits are stored, a main processor for processing information read from the main memory module, and information read from the main memory module. A parity check means for performing a parity check, an error detection / correction means for performing error detection / correction of information read from the main memory module, and one of the plurality of main memory modules are connected to the main processor or the error detection / correction means. A bus switch, an error detection / correction means, a memory check controller for controlling which storage module of a plurality of main storage means performs error detection / correction, an access request from the main processor, and a memory check controller To read information from Then,
A main memory control device comprising: a bus switch controller that controls an operation of a bus switch so that a memory module connected to a main processor and a main memory module connected to a memory check controller are different from each other. 2. The main memory control device according to claim 1, wherein the main processor interrupts the information processing operation when the parity check means detects that a parity error is present in the information read from the main memory module. Then, the memory check controller stops reading information from the main memory module during the error detection and correction operation, executes error detection and correction of the information in which the parity error occurs, and supplies the corrected information to the main processor. A main memory control device, wherein corrected information is stored in a main memory module in which a parity error has occurred, and information reading is restarted from the main memory module that stopped reading the information. 3. The main memory control device according to claim 1, wherein the memory check controller has an error counter, counts the number of times a parity error has occurred for each of the plurality of main memory modules, and the counted number is predetermined. To the main processor and the bus switch controller, which supplies a command signal indicating the storage module that has exceeded the number of
The main memory control device, wherein the bus switch controller stops selecting the storage module having the count value of a predetermined number or more in accordance with a command signal from the memory check controller. 4. The main storage control device according to claim 3, further comprising a replacement determination unit that determines whether or not the storage module whose count number has become a predetermined number or more has been replaced with a new storage module. The main storage control device, wherein the replacement determination unit notifies the bus switch controller that the storage module has been replaced.