JPH0951288A - Spread spectrum receiving device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a synchronization acquisition time by varying the number of stages of matched filters corresponding to a reception state in the spread spectrum receiver used for mobile communication so as to enhance the general- purpose performance of the receiver. SOLUTION: A synchronization detection circuit 24 of the spread spectrum receiver receives a correlation output from a matched filter 1 and a synchronization/asynchronization state signal fed from a delay locked loop DLL 5. When the synchronization detection circuit 24 detects an asynchronous state, the circuit 24 gives a correlation output to a threshold level generating circuit 22 and a 1-tip delay circuit 24, then the 1-tip delay circuit 23 gives the correlation output of one preceding tip to the threshold level generating circuit to receive a current correlation output. The threshold level generating circuit 22 compares the received correlation output with the correlation output of one preceding tip to decide the number of stages of SR for the matched filter. In the case of taking synchronization, a high correlation output is obtained earlier depending on the small/high stage numbers to have provision for the change in a spread rate thereby enhancing the general-purpose performance.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a spread spectrum receiver used for mobile communication, for example.

Spread spectrum communication systems are also being considered for application to mobile communication systems. Along with this,
Since there is a demand for simplification, high functionality, and high performance of the circuit that performs despreading processing, it is necessary to shorten the synchronization acquisition time in this circuit and increase the versatility of the device.

[0003]

2. Description of the Related Art FIG. 8 is a block diagram of a conventional example, FIG. 9 is an explanatory diagram of FIG. 8, (a) is a block diagram of a delay lock loop (DLL), and (b) is a block diagram.
FIG. 9 is an operation explanatory diagram of FIG. 8.

Below, data (eg, 1,
The operation of the figure will be described on the assumption that (0) is multiplied by a spread code to spread the spectrum and transmit it to the receiving side. In FIG. 8, using a master clock (hereinafter, abbreviated as MCK) having the same cycle as the cycle of the spreading code on the transmitting side, a spreading code on the receiving side having the same pattern as the spreading code on the transmitting side (hereinafter, referred to as despreading code) Is latched in a shift register composed of flip-flops FF ₂₁ , FF ₂₂ , FF _23, ... (Hereinafter, referred to as despreading code SR) (see FIG. 9 (b-)).

On the other hand, on the receiving side, after removing interference waves and noise from the received signal, analog / digital (A
/ D) The conversion section digitizes the data, and the serial / parallel (S / P) conversion section 32 converts it into, for example, four sequences of transmission side spreading codes (hereinafter referred to as spread codes).

Then, the spread codes of these four sequences are flip-flop FF ₃₁ ,
In addition to the corresponding SR of the spread code SR composed of FF ₄₁ , FF _51, FF _61, ..., The spread code SR is shifted one stage at a time.

Then, the correlation between the output of each stage of the despreading code SR and the output of each corresponding stage of the spread code SR (for example, EX
-NOR) is taken at the same timing and the correlation result is added
Repeat sending to 33.

The adder 33 adds the input correlation results and sends a correlation output having a peak value as shown in FIG. 9B to the delay lock loop (DLL) 5 and the demodulation circuit 4. Here, the direction of the peak value is opposite when the correlation is obtained at "0" and when the correlation is obtained at "1". Further, as shown in FIG. 8, when one despreading code is used to correlate with four spread codes, there is a high possibility that the number of correlations to be obtained will increase as compared with the case where there is one spread code, and the correlation will increase. The possibility of erroneous determination is reduced when determining whether or not it has been taken.

FIG. 9A is a block diagram of the delay locked loop (DLL) 5, in which the correlation output from the matched filter 3 is squared.
51 is squared, part is inverted by the inverter (INV), and the rest is delayed by one chip length (Tc) at the delay part 52, then the addition part
The output of the modified S-shape as shown in Fig. 9 (b)-
Hereafter, it is called S curve).

[0010] Here, the square is "0" as described above.
When the correlation between "1" and "1" is obtained, the appearance of the peak is reversed. However, since they are the same in that they agree, I squared them so that they would be on the same side.

Further, the output of the voltage controlled oscillator (VCO) 56 is sent to the matched filter 3 as the master clock MCK described above, but a part of the output is divided by the frequency division part 57 to obtain a sampling pulse 54 as a sampling pulse. Add to. The sampling section 54 takes out the value of the S curve at the rising point of the sampling pulse as a sampling value, converts it into an analog signal in the digital / analog (D / A) conversion section 55, and adds it to the VCO 56 as a VCO control signal.

Here, the frequency dividing portion 57 and the sampling portion 5
Since the loop composed of 4, D / A conversion part 55, VCO 56, and frequency division part 57 constitutes a negative feedback loop, the VCO control signal becomes, for example, 0 (at the point A on the S curve, Like) VC
Change the oscillation frequency of O 56. In this state, the despread code and the spread code have the same phase (see FIG. 9).
(b)-, see).

Further, as shown in FIG. 9 (a), the Δ width generation portion 58 is composed of a flip-flop (FF) and an inverter, and FF is the rising point of the master clock MCK and the correlation output from the matched filter. Take in the peak value of and output "1" from the Q terminal.

Then, at the next MCK, the value of the correlation output of almost 0 is taken in and "1" is output from the inverted Q terminal of the FF.
Reset this output by returning it to FF. Then, a negative pulse having a width equal to the width Δ of the slope of the S curve is sent from the output of the inverter INV to the gate portion 59 (see FIGS. 9 (b) -˜,).

On the other hand, the gate portion 59 is composed of an AND gate (not shown), and when the negative pulse is applied from the Δ width generating portion 58, the sampling pulse (solid line pulse).
Cannot pass through this gate, but can pass through when it is positive.

In the latter case, the sampling pulse (dotted line pulse) is out of the slope of the S curve, so this sampling pulse is inverted and sent out as an out-of-sync signal (FIG. 9 (b)-, See).

Further, in the demodulation circuit 4 of FIG. 8, the master clock MCK from the DLL 5 and the correlation output from the matched filter are output.
(Data from which the influence of spreading code has been removed) has been added, so MCK is divided to generate data CK, and data CK
Data synchronized with

..

As described above, since the spreading code pattern is fixed (that is, the number of SR stages is fixed) and the spreading factor = (chip rate / data rate) is fixed, the data rate is Naturally decided. This uniquely determines the applied system.

Further, when the number of SR stages is large (for example, 128), there are two problems that the time until synchronization is taken (synchronization acquisition time) becomes long. The present invention makes the spreading code pattern variable (the number of SR stages variable) to make the spreading factor variable,
The purpose is to increase the versatility of the device and shorten the synchronization acquisition time.

[0020]

The first aspect of the present invention has a configuration in which the number of stages of the matched filter is changed in accordance with the reception state.

The second aspect of the present invention determines the synchronous / asynchronous state from the input state of the out-of-sync signal, and when the determination result is the asynchronous state, the input correlation output and the correlation output of one chip before are used to perform the correlation. Synchronous detection / threshold value generating means for generating and transmitting a threshold value corresponding to the output, the input initial operation condition of the second shift register and the threshold value, and the number of stages of the second shift register. And a stage number control means for transmitting a corresponding stage number control signal to the matched filter.

Further, the matched filter is provided with a stage number switching means for switching the stage number of the second shift register in response to the input stage number control signal. According to a third aspect of the present invention, when the synchronization detection / threshold value generation means performs synchronization protection using an out-of-synchronization signal and an output of the synchronization protection portion indicates an out-of-synchronization state, the above correlation is obtained. A synchronization detection / delay unit including a synchronization detection unit having a gate unit for transmitting an output, and a delay unit for delaying the correlation output by one chip, an initial setting stage number, a correlation output and one chip before. It has a built-in first storage part in which threshold values of the correlation output corresponding to various combinations with the correlation output are stored, and corresponds to when the initial setting stage number, the correlation output and the correlation output of one chip before are applied. A threshold generator for transmitting a threshold value is provided.

According to a fourth aspect of the present invention, the stage number control means sets the first shift register corresponding to a combination of various values of the threshold value of the correlation output, the initial set value and the stage number variable width. A second storage portion in which the number of stages is stored and a serial / parallel conversion portion for converting an input stage number control signal into a parallel signal are provided.

When the threshold value of the correlation output, the initial setting value, and the step number variable width are applied, the second storage means takes out the corresponding step number control signal (SW control signal) and converts the serial / parallel conversion portion. In addition to the above switching means, the number of stages of the second shift register is switched.

[0025]

FIG. 1 is a diagram for explaining the principle of the present invention. As shown in the figure, the correlation output sent by the matched filter 1 and the synchronous / asynchronous state sent by the delay locked loop (DLL) 5 are added to the sync detection circuit 24.

Therefore, when the synchronization detecting circuit 24 determines that the synchronous / asynchronous state is the asynchronous state, it sends the correlation output to the threshold value generating circuit 22 and the 1-chip delay circuit 23. Sends the correlation output of the previous chip to the threshold value generation circuit and captures the current correlation output.

The threshold value generation circuit 22 compares the input correlation output with the correlation output one chip before, and when the input correlation output> the correlation output one chip before, the SR of the matched filter is formed. Increase the number of steps. That is,
Since the synchronization condition has become better than it was one chip ago, the number of SR stages is lengthened and finally the number of stages is set to the normal number. SR when input correlation output <correlation output 1 chip before
Shorten the number of steps.

That is, since the synchronization state is worse than that of one chip before, the number of SR stages is shortened. That is, at the time of synchronization, the number of SR stages may be shortened to obtain a low correlation output, so that the correlation output can be obtained quickly. If a low correlation output is obtained, the number of SR stages is increased to obtain a high correlation output.

This makes it possible to deal with variable spreading factor, so that the versatility of the device can be enhanced and the synchronization acquisition time can be shortened.

[0030]

FIG. 2 is a block diagram of an embodiment of the present invention (variable length matched filter), FIG. 3 is a block diagram of a sync detection circuit of the embodiment of the present invention, and FIG. 4 is a threshold value of the embodiment of the present invention. FIG. 5 is a configuration diagram of a generation circuit, FIG. 5 is an operation explanatory diagram of FIG. 4, FIG. 6 is a configuration diagram of a stage number control circuit of an embodiment of the present invention, and FIG. 7 is a processing procedure explanatory diagram of the embodiment of the present invention.

Here, the same reference numerals denote the same objects throughout the drawings. The drawings will be described below, but the portions described in detail above will be briefly described, and the portions of the present invention will be described in detail. The despread SR and the spread SR correspond to the first and second SRs in the claims. Further, in the embodiment, the matched filter is called a variable length matched filter.

First, as shown in FIG.
Filter 1 is flip-flop FF ₁₁, FF₁₂, FF₁₃・ ・
Diffusion shift register (SR) composed of
・ Flop FF₀₁, FF₀₂, FF₀₃..Despreading composed of
Shift register (SR), switch SW₁, SW₂.., EX-N
.. and an addition section 15.
 Then, in order to synchronize the despread code with the spread code,
The same as the spreading code on the transmitting side using the star clock (MCK)
Latch the despread code of the pattern in the despread SR.

On the other hand, the master clock (MCK) is used to
As in the above, the spread code is set to FF₁₁, FF ₁₂, FF₁₃..Composed of
In addition to the diffused SR that has been
SR for despreading corresponding to FF output in (dotted line)
EX-NOR of the FF output in the EX-NOR gate 11, 12, 13 ...
And send the output of this gate (correlation result) to summing section 15.
Put out.

Therefore, the adding section 15 adds the correlation results to take out the correlation output, digitizes the correlation output, and delay-locks the loop (DLL) 5, demodulation circuit 4, and synchronization detection circuit as shown in FIG. It is sent to 24 (see Fig. 7-S1 to S4).

As a result, as described in detail above, the delay lock loop 5 sends the information on the synchronous / asynchronous state to the synchronous detection circuit 24, and the demodulation circuit 4 synchronizes with the data clock (CK) and this CK. Send the data (see Figure 7-S5).

Here, as shown in FIG. 3, the synchronization detection circuit 24 is composed of a square portion 241, a front / rear protection portion 242, and an AND gate 243, so that it is digitized from a variable length matched filter. The correlation output (eg, 8 bits) is squared by the squared part 241 and added to the above AND gate 243.

On the other hand, the synchronous / asynchronous state information from the delay locked loop (DLL) is, for example, a counter (not shown).
Is added to the front / rear protection portion 242 having. When the synchronization information is input n times consecutively, the protection part 242 judges that the synchronization is established and outputs "0", and when the synchronization information is not input m times consecutively, the synchronization is lost. It is configured to judge and send the output of "1".

Therefore, the digitized correlation output squared at the time of out-of-synchronization (hereinafter referred to as the digitized squared correlation output) is sent to the threshold value generation circuit 22 and the one-chip delay circuit 23. However, in the synchronous state, the AND gate is turned off, so that the digitized squared correlation output is not output from the AND gate 243.

The threshold value generation circuit 22, as shown in FIG.
It consists of ROM 221, and digitized squared correlation output from the sync detection circuit 24 and 1 from the 1-chip delay circuit 23.
The digitized squared correlation output before the chip is applied as an address to the ROM 221 (see Figure 7-S6 and S7).

The ROM 221 stores the number of stages of initialization, the threshold values of the digitized squared correlation output corresponding to various combinations of the digitized squared correlation output A and the digitized squared correlation output B one chip before. .

Therefore, in the case of FIG. 5, when the current digitized squared correlation output is A ₁ and the digitized squared correlation output B one chip before is B ₁ , the difference is + (A ₁ -B ₁ ). So
The threshold value of the digitized squared correlation output is read from the ROM 221 from the initially set number of stages and this difference and sent to the stage number control circuit.

In the case of, the difference becomes-(A ₂ -B ₂ ) because of (A ₂ <B ₂ ), and the threshold value becomes lower than that of one chip before, and in the case of (A ₃ = B ₃ ), the difference becomes 0 and the threshold value does not change. In case of (0 <B ₄ ), the difference becomes −B ₄
And the threshold value drops as well as (see Figure 7-S8).

Further, the ROM 221 is adapted to input the initially set number of stages. This is how much the number of SR stages at the time of obtaining the initial correlation is set.
If 128 steps, halve it to 64 steps.

The stage number control circuit 21, as shown in FIG.
1 and a serial / parallel (S / P) conversion part 212 that converts serial data read from the ROM to parallel.
In 211, the set number of stages of the spread code SR corresponding to various combinations of the digitized squared correlation output threshold value, the initial set value, and the stage number variable width is stored.

Therefore, when the threshold value of the digitized squared correlation output, the initial setting value, and the step number variable width are determined, the step number control signal (SW control signal) corresponding to the step number of the corresponding spread SR.
Is read out and added to the S / P conversion section 212.

The S / P conversion section 212 converts the SW control signal into a parallel signal and drives the corresponding SW, respectively. Therefore, for example, the SW to which the SW control signal of "1" is applied is turned on and the dotted line state. Therefore, the SW to which the SW control signal of "0" is applied remains off (see S9 and S2 in Fig. 7).

As a result, it becomes possible to control the number of stages of the spread code SR, and at the time of synchronization, the number of stages of SR can be shortened to obtain a low correlation output, so that a correlation output can be obtained quickly. To do. If a low correlation output is obtained, SR
It is possible to shorten the synchronization acquisition time by increasing the number of stages to obtain a high correlation output.

Further, since it is possible to deal with the above-mentioned variable diffusion rate, the versatility of the device can be improved.

[0049]

As described in detail above, according to the present invention, the versatility of the apparatus can be enhanced and the synchronization acquisition time can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram (variable length matched filter) of an embodiment of the present invention.

FIG. 3 is a configuration diagram of a synchronization detection circuit according to an embodiment of the present invention.

FIG. 4 is a configuration diagram of a threshold value generation circuit according to an embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of FIG. 4;

FIG. 6 is a configuration diagram of a stage number control circuit according to an embodiment of the present invention.

FIG. 7 is an explanatory diagram of a processing procedure according to the embodiment of this invention.

FIG. 8 is a configuration diagram of a conventional example.

9 is an explanatory diagram of FIG. 8, where (a) is a delay locked loop (DL
FIG. 9B is a configuration diagram of L), and FIG.

[Explanation of symbols]

1 Matched filter (variable length) 4 Demodulation circuit 5 Delay lock loop 21 Number of stages control circuit 22 Threshold value generation circuit 23 1 chip delay circuit 24 Sync detection circuit

Claims (4)

[Claims] 1. In a spread spectrum receiving apparatus for performing despreading processing on a received transmission side spread spectrum code using a matched filter to take out a signal in a state where spectrum spreading is not performed, the number of stages of the matched filter is set to the receiving state. A spread spectrum receiver having a variable configuration corresponding to the above. 2. The receiving side spreading code having the same pattern and the same cycle as the transmitting side spreading code is stored in the first shift register, and the received transmitting side spreading code is input to the second shift register, A matched filter that outputs the correlation output obtained by taking the correlation between the spreading code on the receiving side and the spreading code on the transmitting side of the same stage of the first and second shift registers and adding the correlation output, and the output of the built-in voltage controlled oscillator A clock with the same period that is synchronized with the spreading code on the transmission side is generated by using, but in a spread spectrum receiver with a delay lock loop that sends an out-of-sync signal when out of sync When the status is judged and the judgment result is asynchronous, it is 1 with the input correlation output.
Synchronous detection / threshold generation means for generating and transmitting a threshold value corresponding to the correlation output by using the correlation output before the chip, initial operation condition of the input second shift register and the threshold value. The value is used to determine the number of stages in the second shift register,
A stage number control means for sending a corresponding stage number control signal to the matched filter, and a stage number switching means for switching the stage number of the second shift register corresponding to the input stage number control signal are provided in the matched filter. The spread spectrum receiver according to claim 1, wherein 3. A synchronization protection part, wherein said synchronization detection / threshold value generation means performs synchronization protection using an out-of-sync signal,
A sync detection part having a gate part for sending out the above correlation output when the output of the sync protection part indicates an out-of-sync state;
A correlation detection / delay unit including a delay unit for delaying the correlation output by one chip, and a correlation output corresponding to various combinations of the initial setting stage number, the correlation output, and the correlation output one chip before. It has a first storage part in which a threshold value is stored, and has a threshold value generation part which sends out a corresponding threshold value when an initial setting stage number, a correlation output and a correlation output one chip before are applied. The spread spectrum receiver according to claim 2, wherein 4. The stage number control means stores the set stage number of the first shift register corresponding to a combination of various values of the correlation output threshold value, the initial set value, and the stage number variable width. And a serial / parallel conversion unit for converting an input stage number control signal into a parallel signal, wherein the second storage unit has a correlation output threshold value, an initial set value, and a variable stage number. When the width is applied, the corresponding step number control signal (S
3. The spread spectrum receiver according to claim 2, wherein the W control signal) is taken out and added to the switching means via the serial / parallel conversion portion to switch the number of stages of the second shift register.