JPH0936826A - No-hit switching device of transmission line and method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten a time required from the occurrence of a fault to the completion of a switching by executing the switching retroactively to the data block on the side of a reserve transmission line where a bit error does not exist before a certain data block immediately after the bit error is detected in this data block. SOLUTION: Each of bit error detection circuits 56 and 66 independently performs parity check operations for all bits from the frame of the previous time up to just before the byte of the frame of this time and detects the presence or absence of a bit error. When the bit error of an active transmission line is detected, the presence or absence of the bit error of a reserve transmission line 61 is checked. When the bit error does not exist in the reserve transmission line 61, the switch from the active transmission line 51 to the reserve transmission line 61 is performed. Namely, even when a sudden bit error is produced in the certain data block of the active transmission line 51, the switching is executed without hit retroactively to the normal data block on the reserve transmission line 61.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for continuously switching transmission lines in digital communication, and more particularly to an SDH (Synchronous Digital Hierarchy) transmission system and SONET (Synchronous Optical Network).
Transmission system, ATM (Asynchronous Transfer Mode)
The present invention relates to an apparatus and a method suitable for switching a transmission path in a transmission system without interruption.

[0002]

2. Description of the Related Art In order to secure the reliability of communication, a redundant system is used in which one spare transmission line is arranged for one or a plurality of working transmission lines.

FIG. 1 is a block diagram showing an example of a conventional redundant system. In the figure, two terminal stations 1 and 2
In between, a working transmission line 3 and a backup transmission line 4 having a plurality of regenerators REP are provided. Working transmission line 3
If any failure occurs in the communication, the communication between the terminal stations 1 and 2 can be continued by switching from the working transmission path 3 to the backup transmission path 4.

In this type of conventional system, switching from the working transmission line to the standby system usually involves interruption of the main signal. That is, the actual switching process requires a series of processes such as notification of failure information from the receiving side to the transmitting side, confirmation of the availability of the backup transmission line and normal operation, switching operation, and synchronization recovery operation of the main signal. Therefore, it is generally accompanied by interruption (instantaneous interruption) of a signal for a short time. Data loss due to momentary interruption increases with an increase in the transmission bit rate of the main signal, which is a serious problem.

FIG. 2 shows a conventional system proposed to solve such a problem. This is disclosed in Japanese Patent Laid-Open No. 5-344104 by Uematsu et al., And FIG. 2 shows a receiving terminal station of a transmission system.

Input main signals from the working transmission line 11 and the backup transmission line 21 are supplied to interface circuits 13 and 23 via input terminals 12 and 22, respectively. The interface circuits 13 and 23 perform the identification reproduction processing after performing the photoelectric conversion of the received main signal, and output the output.
It is supplied to the signal termination processing circuits 14 and 24, respectively. The signal termination processing circuits 14 and 24 perform main signal termination processing such as frame detection and bit error detection by parity check, and supply the outputs to the delay circuits 15 and 25. The delay circuits 15 and 25 provide delays longer than the time required for frame phase matching of the main signals of both systems,
Give to these signals. When the signal disconnection detection circuits 16 and 26 respectively connected to the interface circuits 13 and 23 detect an abnormality in the input main signal, the switching circuit 30
Send a switching control signal to. The switching circuit 30 switches to the backup transmission line if an abnormality occurs in the working transmission line.

[0007]

The transmission line switching device shown in FIG. 2 uses an alarm signal issued from the signal disconnection detection circuits 16 and 26 or the signal termination processing circuit 14 or 24 as a switching trigger to detect a sudden failure. In the same way, there is no interruption switching. Alarms used as switching triggers include interruption of main signal light input, loss of frame synchronization, deterioration of transmission line quality, etc., but all require a protection time to determine a failure. Taking the case of frame synchronization as an example, the frame synchronization pattern existing in the frame is continuously lost and a certain number of times is set so that synchronization is not easily lost with random errors that occur on the transmission line in the middle. When it exceeds, it recognizes that it is out of sync (generally called forward protection) and issues an out-of-frame alarm. In addition, the quality deterioration of the transmission path is determined as a failure when the bit error rate within a preset superframe is calculated by a parity check and a bit error rate exceeding a predetermined threshold is detected over a certain continuous frame. are doing. At this time, when the threshold value of the bit error rate is 1 × 10 ⁻⁶ , the superframe length needs to be at least 1 × 10 ⁶ bits. This sets the bit rate of the main signal to 155.52.
In the case of Mbit / s, this corresponds to a time length of 6.4 ms. When a bit error is continuously detected for several frames in the 6.4 ms superframe, it is determined that the quality deterioration occurs. Therefore, the quality deterioration also needs a time that cannot be ignored for the detection. As seen above, in the conventional method that uses the alarm signal as the switching trigger,
Since the protection time is required to confirm the failure, the time required from the occurrence of the failure to the execution of switching becomes very long. Within this time, the data affected by the failure or the data having the bit error will be transmitted to the device on the downstream side.

An object of the present invention is to provide a non-instantaneous interruption switching device and method in which the time required from the occurrence of a failure to the completion of switching is shortened. In the hitless switching device according to the present invention, even if the occurrence of a failure is not fixed, as soon as a bit error is detected in a certain data block, the data block on the backup transmission line side having no bit error, which precedes this data block, is immediately detected. Switch back in time.

Another object of the present invention is to provide a hitless switching device and method with less bit errors.

[0010]

In order to achieve the above object, the present invention provides, as a flow of a data block containing bit error check information, the same main signal arriving through a first transmission line and a second transmission line. Is received, switched without interruption, and supplied to the third transmission line, thereby
And a second transmission path as a working transmission path and the other as a standby transmission path.
A first signal termination processing circuit connected to the first transmission line, receiving one of the same main signals, and outputting the first main signal as a first main signal; and connecting to the second transmission line, A second signal termination processing circuit that receives the other of the same main signals and outputs it as a second main signal, and a bit error of the first main signal based on the bit error check information. A first bit error detection circuit for detecting each block, a second bit error detection circuit for detecting a bit error of the second main signal for each data block based on the bit error check information, A phase difference detection circuit for detecting a phase difference between the first main signal data block and the second main signal data block; and a phase difference detection circuit for compensating for the phase difference detected by the phase difference detection circuit. 1 main signal data A phase compensation circuit that matches the phases of a lock and the data block of the second main signal, and outputs the first main signal data block and the second main signal data block that are in phase, and the phase compensation circuit A first delay circuit delaying the first main signal output from the circuit for at least one data block length, and a second delay signal output from the phase compensation circuit for at least one data block length. A second delay circuit for delaying, and the first delay circuit
Switching for selectively supplying one of the first main signal output from the second delay circuit and the second main signal output from the second delay circuit to the third transmission path. Circuit, the first transmission path is a working transmission path, and the second transmission path is a backup transmission path, the first bit error detection circuit stores a bit in a data block containing the first main signal. When an error is detected and the second bit error detection circuit does not detect a bit error in the corresponding data block of the second main signal, a switching control signal is supplied to the switching circuit to cause the second delay. And a correlation monitoring circuit that supplies the second main signal output from the circuit from the switching circuit to the third transmission path.

The signal termination processing circuit has a failure detecting means for monitoring the main signal to detect a failure upstream of the first transmission path and the second transmission path, and the correlation monitoring circuit. If a failure is detected in the first transmission line when the first transmission line is the working transmission line and the second transmission line is the backup transmission line, the presence or absence of a bit error for each data block Regardless of the above, the switching control signal is generated to switch the second transmission line to the working transmission line and the first transmission line to the backup transmission line.

The data block is a data block having the bit error check information as a head.

The correlation monitoring circuit, immediately after the bit error detection circuit transmits the bit error check information,
The switching control signal is generated.

The above-mentioned failure is caused by ITU-T Recommendation G. 70X
And ANSI (American National Standards Instit
ute) LOS (Loss Of
Signal), LOF (Loss Of Frame), AIS (Alarm
Indication Signal) and other alarm signals.

The bit error check information is ITU-
T. Recommendation G. It is characterized by being B3 byte defined in SONET by 70X and ANSI.

The bit error check information is ITU-
T. Recommendation G. It is characterized in that it is B2 byte defined in SONET by 70X and ANSI.

The data block is ITU-T recommendation.
G. FIG. It is characterized by being a VC (Virtual Container) frame defined in 70X.

The data block is ITU-T recommendation.
G. FIG. 1VC beginning with B3 byte defined in 70X
A data block having a frame length, wherein the correlation monitoring circuit generates the switching control signal immediately after the bit error detection circuit receives the B3 byte.

The data block is an S according to ANSI.
STS SPE (Synchronous Tr
ansport Signal Synchronized Payload Environment)
It is characterized by being a frame or a VT (Virtual Tributary) SPE frame.

The data block is S based on ANSI.
It is a data block of 1 frame length starting from B3 byte defined in ONET, and the correlation monitoring circuit generates the switching control signal immediately after the bit error detection circuit receives the B3 byte. Characterize.

The data block is ITU-T recommendation.
G. FIG. 70X STM (Synchronous Transpor)
t Module) frame.

The data block is ITU-T recommendation.
G. FIG. 1ST beginning with B2 byte defined in 70X
It is a data block having an M frame length, and the correlation monitoring circuit generates the switching control signal immediately after the bit error detection circuit receives the B2 byte.

The data block is an STS frame defined in ANSI.

The data block is S based on ANSI.
A data block having a 1-frame length beginning with B2 byte defined in ONET, wherein the correlation monitoring circuit generates the switching control signal immediately after the bit error detection circuit receives the B2 byte. And

The data block is ITU-T recommendation.
I. It is characterized in that it is an ATM cell defined in 432.

The bit error check information is ITU-
Recommendation T. I. HEC in ATM cell defined in H.432
(Header Error Control) bytes.

The bit error check information is the AT
The contents of the header area and the information area of the M cell are data obtained by executing the bit interleave parity operation.

Further, according to the present invention, as the flow of the data block including the bit error check information, the same main signal arriving through the first transmission path and the second transmission path is received and switched without interruption, 3 is a non-interruption switching method in which one of the first transmission path and the second transmission path is used as a working transmission path and the other is used as a backup transmission path by supplying the same transmission path to the same main path. A step of receiving one of the signals and outputting it as a first main signal; a step of receiving the other of the same main signals and outputting it as a second main signal; A step of detecting a bit error for each data block based on the bit error check information, and a bit error of the second main signal is detected for each data block based on the bit error check information. process A step of detecting a phase difference between the data block of the first main signal and a data block of the second main signal, and compensating for the phase difference detected by the phase difference detection circuit, Aligning the phase of the data block of the main signal and the data block of the second main signal,
Outputting the first main signal data block and the second main signal data block in phase;
Delaying the in-phase first main signal for at least one data block length, and the in-phase second
Delaying the main signal for at least one data block length, and any one of the delayed first main signal and the delayed second main signal are transferred to the third transmission line. In the process of selectively supplying, when the first transmission line is the working transmission line and the second transmission line is the backup transmission line, the first bit error detection circuit outputs the first main signal A bit error is detected in a certain data block, and the second
When the bit error detection circuit of does not detect a bit error in the corresponding data block of the second main signal,
Generating a switching control signal and supplying the delayed second main signal to the third transmission line.

According to the present invention, the bit error check method (parity check or CRC (Cyclic Redundancy) is independently applied to both the working transmission line and the protection transmission line.
Check) code or the like) is used to check a bit error, and if a bit error occurs in even one bit in the working transmission line, the standby transmission line in which no one bit is in error is switched to without interruption. As a result, only data having no bit error is sent downstream of the transmission path switching device.

According to the present invention, as soon as a bit error of the first data block at the time of a sudden failure is detected within the above-mentioned protection time, immediately before this data block, the data block of the backup transmission line having no bit error is formed. I go back and try to switch. Therefore, the correct data can be transmitted to the downstream device regardless of the protection time until the failure is determined.

Further, according to the present invention, instead of the data block of the working transmission line having a bit error, the data block of the protection transmission line having no bit error is transmitted to the downstream device, so that even a random bit error of the transmission line is generated. Can be corrected. Therefore, the bit error rate of data transmitted downstream can be improved.

Further, by providing the bit error check information of the immediately preceding data block at the head of the data block, the time from the bit error detection to the switching can be minimized.

[0033]

Embodiments of the present invention will be described below in detail with reference to the drawings.

Embodiment 1 FIG. 3 is a block diagram showing a first embodiment of a transmission path hitless switching apparatus according to the present invention. This switching device corresponds to the receiving unit of the terminal device 1 or 2 shown in FIG. In the figure, the main signals S1 and S11 arriving via the working transmission path 51 and the backup transmission path 61 are supplied to signal termination processing circuits 53 and 63 via input terminals 52 and 62.

FIGS. 4 and 5 show signals S1 and S11.
It is a figure which shows the frame structure of. This is an STM (Synchronous Transfer Mode) frame defined by ITU-T recommendation SDH (Synchronous Digital Hierarchy), and SONET (Synchronouou) by ANSI in the United States.
s Optical Network).

In FIG. 4, an STM frame (to be exact, an STM-1 frame, but hereinafter, simply referred to as an STM frame) 80 has a total of 243 of 270 bytes × 9 lines 243.
This is a frame consisting of 0 bytes. This frame includes an SOH (Section OverHead) information area 81 for accommodating 9 bytes of operation and maintenance information from the beginning of each line, and 1 for each line.
It is composed of a user information area (Payload) 82 from the 0th byte to the 270th byte. This user information area 82 is a VC frame (Virtual Container Frame).
) Is an area for housing. The SOH information area 81 further includes RSOH (Regenerato) of the first 9 bytes of lines 1-3.
r Section Overhead) 81a and AUPTR (Administrative Unit Pointer) 81b of the first 9 bytes of the 4th line
And the first 9 bytes of MSOH (Multiplex Se
ction overhead) 81c. Among them, the AUPTR 81b is composed of H1 byte, H2 byte, and H3 byte, and H1 and H2 bytes are V
It indicates the beginning of the C frame 82 (see FIG. 5). Note that VC
The frame is allowed to float within the user information area 82. Further, the RSOH 81a includes a B1 byte as a bit error monitoring byte of the relay section, and the MSOH 81c includes a B2 byte as a bit error monitoring byte of the multiplexing section and K1 bytes and K2 bytes described later. Has been.

As shown in FIG. 5, the first byte of each row of the VC frame 82 containing the user information is POH (Path
Overhead) 82a, with the J1 byte at the beginning. The B3 byte on the second line is provided as a bit error monitoring byte for the VC path. This STM frame 80 starts from the first byte of the first row, then the second row, the third row. . . Will be sent in that order. Therefore, SO
Excepting the H information area 81, focusing only on the VC frame 82, as shown in FIG. 5, starting from the first line starting with the J1 byte, the second line starting with the B3 byte.
line,. . . Then, 261 bytes are sequentially sent, and when the 9th line is sent, the transmission of the 1VC frame is completed.

Returning to the explanation of FIG. Signal termination processing circuit 53
And 63, upon receiving the main signals S1 and S11 having such a frame structure, establish frame 80 synchronization. That is, first, the A1 and A2 bytes of the SOH information area 81 are detected to recognize the head of the STM frame, and then the AUPTR 81b is detected to detect the head byte J1 of the VC frame indicated by H1 and H2. .

The J1 byte reception time information detected by the signal termination processing circuits 53 and 63 is supplied to the phase difference detection circuit 70 as VC frame phase display signals S5 and S15. The phase difference detection circuit 70 compares the J1 byte reception time information of both systems to detect the phase difference of the VC frames 82 of both systems, and outputs the control signal S20 indicating this phase difference to the phase compensation circuits 54 and 64. Supply. This phase difference is mainly due to the difference in transmission line length between the working transmission line and the protection transmission line.

FIG. 6 is a diagram for explaining the phase compensation operation by the phase compensation circuits 54 and 64. As shown in the figure,
The phase compensation circuit 54 for the working transmission path gives a certain fixed delay to the main signal S2 supplied from the signal termination processing circuit 53 and outputs it as a signal S3. On the other hand, the phase compensation circuit 64 for the backup transmission line includes the signal termination processing circuit 63.
A variable delay of the phase difference supplied from the phase difference detection circuit 70 + the certain fixed delay, which is supplied from the phase difference detection circuit 70, is added to the main signal S12, and the main signal S12 is output as the main signal S13. In this way, the phase compensating circuits 54 and 64 of both systems output the main signals S3 and S13 in which the frame phases are matched, and are supplied to the delay circuits 55 and 65, respectively. These fixed and variable delay additions are performed using the memories included in the phase compensation circuits 54 and 64.

Main signals S3 and S having the same frame phase
13 is supplied to the delay circuits 55 and 65, respectively. Delay circuits 55 and 65 have main signals S3 and S1.
3 is given a certain delay and is supplied to the switching circuit 71 as the main signals S4 and S14. This delay time must be set to be longer than the time required to detect a bit error for each data block of the signals S2 and S12.

The VC frame data series including the B3 byte or the STM frame data series including the B2 byte output from the signal terminating circuits 53 and 63 is the bit error detecting circuits 56 and 66 as the signals S6 and S16. Is supplied to. Bit error detection circuit 56
And 66 detect the bit error for each system by comparing the BIP operation and the operation result with the B2 or B3 byte, and supply the detection result to the correlation monitoring circuit 75 as signals S7 and S17. Various alarms output from the signal termination processing circuits 53 and 63 such as optical input disconnection and loss of frame synchronization are supplied to the correlation monitoring circuit 75 as control signals S8 and S18. These alerts are received by S
This occurs when an abnormal state of an OH or POH byte is detected over the protection stage. Next, the role of these bytes in SDH will be described.

(1) H1 and H2 bytes ITU-T recommendation G. H1 and H2 are V in 70X
It is specified that the first byte of the C frame is designated. In addition, 2.3.2 stipulates that all bits of H1 and H2 are set to "1" as an AIS (Alarm Indication Signal) that informs a downstream of a fault occurring in the upstream. In other words, the H1 and H2 bytes in which all the bits are "1" indicate that there is some failure upstream.

(2) B2, B3 bytes ITU-T Recommendation G. STM frame 80 for 70X
B2 byte is MSOH for parity check of
It is described that it is provided in 81c. Also, Bit Interleaved Parity
Is calculated for all bits of the immediately preceding STM frame 80 except RSOH 81a, and is stored in the B2 byte of the immediately following STM frame.

ITU-T Recommendation G. 70X describes that the B3 byte is provided in the POH 82a of the VC frame for the parity check of the VC frame 82. Also, Bit Interlea
It is specified that ved Parity is calculated for all bits of the immediately preceding VC frame and is stored in the immediately following B3 byte.

These parity checks are obtained by bit interleaved parity operation. For example, regarding the B3 byte, on the transmitting side, all bytes in the VC frame are
It is obtained by dividing the bit into eight, performing a parity operation separately for each division, and writing the result in the B3 byte of the next frame. The receiving side performs the same calculation as the transmitting side, and compares the result with the B3 byte of the next frame to detect a bit error.

(3) K2 byte ITU-T recommendation G. In 70X, it is stipulated that bits 6, 7 and 8 of the K2 byte are set to "1" as an AIS that informs a downstream of a failure that occurred in the upstream. In other words, the K2 byte whose 6, 7, and 8 bits are "1" indicates that there is some failure upstream.

The correlation monitoring circuit 75 is provided with the signals S7, S17,
By S8 and S18, it is determined whether or not the switching between the working transmission path and the protection transmission path is executed, and the switching control signal S21 is sent to the switching circuit 71.

The switching circuit 71 is a non-instantaneous-interruption switching circuit capable of switching within 1 bit time, and outputs either the signal S4 from the delay circuit 55 or the signal S14 from the delay circuit 65 as an output terminal S22. It outputs from 72 to the transmission line 73.

FIG. 7 is a diagram schematically showing the operation of the switching circuit 71 based on the bit error detection. The data blocks have data block numbers # 1, # 2, # 3, # 4.
It is given like. Therefore, even if there is a phase difference between the signals on the working transmission path and the protection transmission path, it can be recognized that they are the same data block. Information A, B, C, D is stored in these data blocks.

The signals S1 and S11 sent from the upstream device are respectively switched to the non-instantaneous interruption mode through the 0-system transmission line (active transmission line in FIG. 3) and the 1-system transmission line (standby transmission line in FIG. 3). Input to the device. In the switching device, bit error detection is performed independently on the working transmission path and the protection transmission path by parity check or CRC. It is now assumed that a bit error is detected in data block # 2 on the 0-system transmission line and a bit error is detected on data block # 3 in the 1-system transmission line. In this case, the switching circuit 71 first outputs the # 1 data block of the 0-system transmission line as the main signal S22, and then outputs the # 2 data block of the 1-system transmission line. Then, the # 3 data block of the 0-system transmission line is output, and subsequently the # 4 data block of the 0-system transmission line is output. That is, the switching circuit 71 sets the 0-system, 1-system, 0-system, and 0-system transmission paths as the working transmission paths for the passage of the data blocks # 1 to # 4, and always transmits error-free frames downstream. To do.

FIG. 8 is a diagram for explaining the actual switching operation of the present embodiment based on the bit error detection, (A)
Shows a switching method in 1VC frame length data block units with the J1 byte as a head, and (B) shows a 1VC frame length data block unit switching method with B3 bytes as a head.

As described above, the receiving side detects the bit error by comparing the B3 byte with the result of calculating the parity for the bits of the entire previous VC frame. Therefore, at time t4 in FIG. 8A, that is, when the reception of the latest B3 byte is completed, it is determined whether or not there is a bit error in the previous frame. in this case,
The bit error detection circuits 56 and 66 in FIG. 3 independently perform a parity check operation on all bits from J1 of the previous frame to immediately before the J1 byte of the current frame, and compare the result with the B3 byte of this time. hand,
Detects the presence of bit errors. Therefore, when processing a data block having the J1 byte at the head, it takes time T1 (= t4−t1) to detect a bit error.
On the other hand, as shown in FIG. 8B, if switching is performed in data block units starting with B3 bytes, it is possible to detect bit errors more quickly. As is clear from FIG. 8B, the bit error detection time in this case is T
2 (= t3−t1), but this time t3 is the time t
4, the time is earlier by one line (260 bytes) of the VC frame. Therefore, T3 (= T1
The delay time of the delay circuits 55 and 65 can be shortened by −T2 = t4−t3). Further, the reduction of the delay time for one row of the VC frame means reduction of the memory amount for giving the delay time. That is, the method of FIG. 8B can reduce the delay time and the memory for one row of the VC frame more than the method of FIG. 8A. With respect to the STM frame, the same action and effect can be obtained by setting the beginning of the data block to B2 bytes.

FIG. 9 is a flow chart showing the operation of the correlation monitoring circuit 75 of FIG. The correlation monitoring circuit 75 executes the switching in consideration of both the failure and the bit error. Here, failure means that the optical input is cut off, the frame is out of sync, and the AIS
It means an alarm issued with protection time such as reception.
These faults are generated when, for example, no optical signal is input to the optical receiving element or that frame synchronization is lost for a certain protection time, so they are more accurate than bit errors. This is high information. Therefore, in this switching control operation, the detection of a failure is prioritized as the switching trigger over the detection of a bit error, and the switching control is performed. FIG. 9 shows the principle of such switching control.

When a failure of the backup transmission line is detected in step SP1 of FIG. 9, switching from the working transmission line to the backup transmission line is prohibited in step SP7. If there is no failure in the backup transmission line, in step SP2,
The prohibition of switching from the working transmission path to the protection transmission path is released.
Next, when a failure of the working transmission line is detected in step SP3, the working transmission line is switched to the protection transmission line in step SP6. If there is no failure in the working transmission line, the presence / absence of a bit error in the working transmission line is checked in step SP4. If there is no bit error, the process returns to step SP1. When a bit error in the working transmission line is detected, it is checked in step SP5 whether there is a bit error in the protection transmission line. If there is no bit error in the protection transmission line, in step SP6, the protection transmission from the working transmission line is performed. Switching to the road is performed. That is, when a bit error occurs in the working transmission line and there is no bit error in the protection transmission line, the working transmission line is switched to the protection transmission line. On the other hand, in step SP5, when a bit error is also detected in the backup transmission line, the process directly returns to step SP1 and system switching is not performed.

FIG. 10 is a flow chart when a bit error is detected by using the B3 byte. In this case, the data block corresponds to a VC frame. Since the operation shown in this flowchart is clear from FIG. 9, its explanation is omitted. According to this processing, VC frames can be switched and protected without interruption.

FIG. 11 is a flow chart when a bit error is detected by using the B2 byte. In this case, the data block corresponds to the STM frame. The operation shown in this flowchart is also apparent from FIG. According to this processing, the STM frame can be switched and protected without interruption.

Embodiment 2 FIG. 12 is a block diagram showing a second embodiment of the hitless switching apparatus according to the present invention. The difference between this embodiment and the first embodiment is as follows.

(1) The point where the signal supply lines to the bit error detection circuits 56 and 66 are removed from the signal termination processing circuits 53 and 63.

(2) From the phase compensation circuits 54 and 64 to the bit error detection circuits 56 and 66, the phase-compensated signal S
3 and S13 are supplied. This is because the bit error is detected after the phases of the main signals received from the working and protection transmission lines are matched.

Even with such a structure, the same operation and effect as those of the first embodiment can be obtained. That is, the transmission path non-interruption switching apparatus according to the present invention traces back to the corresponding normal data block on the backup transmission path without any interruption even if a bit error suddenly occurs in a data block on the working transmission path. Since the switching is performed in step 1, the normal signal can be always transmitted to the downstream device regardless of the protection time required for determining the failure.

Further, in the transmission path non-interruption switching apparatus according to the present invention, it is possible to always select an error-free frame unless two transmission paths connected to the input side simultaneously fail. Therefore, it is possible to provide an extremely reliable transmission path. For example, the transmission path error rate of each VC frame of the working transmission path and the protection transmission path is 1 × 10.
^{When set to -11} , the probability that VC frames of both systems will simultaneously generate bit errors is 3.53 × 10 ^-14 . That is, it is possible to provide a highly reliable transmission line in which only one bit error occurs in about 112 years.

The first and second embodiments described above are examples in which the present invention is applied to SDH recommended by ITU-T.
ANSI standard SONET (Synchronous Optical Network)
The same applies to ork. The main equivalent items in SDH and SONET are as follows.

SDH level SONET level STM-1 STS-3 VC-4 STS-3C SPE VC-21 VT-6 SPE RSOH Section Overhead MSOH Line Overhead POH Path Layer Overhead H1, H2 H1, H2 B2 B2 K1, K2 K1, K2 J1 J1 B3 B3 NOTE: SPE = Synchronized Payload Environment If these equivalences are used, the present invention can be applied to a SONET frame, and the same actions and effects as in the first and second embodiments can be obtained.

Further, instead of the STS frame defined by ANSI, the VT (Virtual Tribu
tary) SPE frame or STS SPE frame can also be used.

Embodiment 3 FIG. 13 shows an apparatus for switching a transmission line without interruption according to the present invention.
It is a figure for demonstrating the example applied to TM (Asynchronous Transfer Mode), and has shown the structure of the ATM cell.

ITU-T Recommendation I. 432 describes an error correction function and an error detection function using HEC bytes in an ATM network. The ATM performs data transmission in units of data blocks called cells of 53 bytes as shown in FIG. The fifth byte from the beginning of the cell is called a header, and the destination address of the cell and various control information are stored. Actual information (Information Field) is stored in the remaining 48 bytes.

In ATM, since an address is given to each cell, if a bit error occurs in the header, the destination of the cell may be wrong and accurate transmission may not be possible. Therefore, at the 5th byte, HEC (Header Error)
Control) byte is arranged, the 4-byte data of the header excluding the HEC byte is subjected to a block check using the CRC code, and the calculation result is stored in the HEC byte. On the receiving side, using this HEC byte,
CRC calculation is performed to detect and correct errors in the header.

Therefore, by utilizing this function, the switching control between the working transmission path and the protection transmission path can be performed in the same manner as the bit error detection in the above-mentioned embodiment. Further, the bit error detection function using the HEC byte has an automatic error correction function up to 1 bit, so when an error of 2 bits or more occurs and self error correction cannot be performed, it is recognized as a bit error of the header. Then, the system can be switched.

Furthermore, bit error check information is obtained by performing a bit interleave parity operation over the entire bytes of the header area of the ATM cell and the bytes of the information area and writing the result in the header. You can

[0071]

According to the present invention, a bit error check method (parity check or CRC (Cyclic Redundancy Check) is performed on both the working transmission line and the protection transmission line.
) Code, etc.), the bit error is independently checked, and when a bit error is detected in the working transmission line even if it is 1 bit, the protection transmission line is switched to the backup transmission line in which 1 bit is not mistaken without interruption. As a result, only data having no bit error is sent downstream of the transmission path switching device.

Further, according to the present invention, even within the above-mentioned protection time, immediately after detecting the bit error of the first data block at the time of a sudden failure, immediately before this data block,
Switching is performed by going back to the data block of the backup transmission line having no bit error. Therefore, the correct data can be transmitted to the downstream device regardless of the protection time until the failure is determined.

Further, according to the present invention, instead of the data block of the working transmission line having a bit error, the data block of the protection transmission line having no bit error is transmitted to the downstream device, so that even a random bit error of the transmission line is generated. Can be corrected. Therefore, the bit error rate of the data transmitted to the downstream device can be improved.

Further, by providing the bit error check information of the immediately preceding data block at the head of the data block, the time from the bit error detection to the switching can be minimized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a conventional redundant system.

FIG. 2 is a block diagram showing a configuration of a main part of a conventional transmission path switching device.

FIG. 3 is a block diagram showing a first embodiment of a transmission path hitless switching apparatus according to the present invention.

FIG. 4 is a diagram showing a frame structure in an SDH system.

FIG. 5 is a diagram showing a frame structure in an SDH system.

FIG. 6 is a diagram illustrating a phase compensation operation by the phase compensation circuit of FIG.

FIG. 7 is a diagram schematically showing the operation of the switching circuit based on bit error detection.

FIG. 8 is a diagram for explaining an actual switching operation of the present embodiment based on bit error detection.

FIG. 9 is a flowchart showing the operation of the correlation monitoring circuit.

FIG. 10 is a flowchart showing a switching operation when a bit error is detected by comparing a B3 byte for parity check of a VC frame with a parity check calculation result in the own system.

FIG. 11: B2 for parity check of STM frame
7 is a flowchart showing a switching operation when a bit error is detected by comparing a byte and a parity check calculation result in the own system.

FIG. 12 is a block diagram showing a second embodiment of a hitless switching device according to the present invention.

FIG. 13 is a block diagram showing a transmission line non-interruption switching device according to the present invention,
It is a figure for demonstrating the Example applied to TM (Asynchronous Transfer Mode), and has shown the structure of the ATM cell.

[Explanation of symbols]

 1, 2 Terminal equipment 3 Working transmission line 4 Backup transmission line 11 Working transmission line 12, 22 Input terminal 13, 23 Interface circuit 14, 24 Signal termination processing circuit 15, 25 Delay circuit 16, 26 Signal loss detection circuit 21 Backup transmission Path 30 Switching circuit 51 Working transmission path 61 Backup transmission path 52,62 Input terminal 53,63 Signal termination processing circuit 54,64 Phase compensation circuit 55,65 Delay circuit 56,66 Bit error detection circuit 75 Correlation monitoring circuit 70 Phase difference detection Circuit 77 Overhead detection circuit 80 STM frame 81 Section OverHead (SOH) information area 81a RSOH 81b AUPTR 81c MSOH 82 VC frame

Claims (19)

[Claims] 1. A third transmission line, which receives the same main signal arriving through a first transmission line and a second transmission line as a flow of a data block containing bit error check information and switches without interruption. By supplying to the first
Of the same main signal, which is connected to the first transmission line and is configured to use one of the second transmission line and the second transmission line as a working transmission line and the other as a standby transmission line. A first signal termination processing circuit that receives one of the two and outputs it as a first main signal; and a second main signal that is connected to the second transmission line and receives the other of the same main signals. A second signal termination processing circuit for outputting as a signal, a first bit error detection circuit for detecting a bit error of the first main signal for each of the data blocks based on the bit error check information, A second bit error detection circuit for detecting a bit error of the second main signal for each of the data blocks based on the bit error check information; a data block of the first main signal; and a second main signal Between the data blocks of A phase difference detection circuit for detecting a difference, compensating for the phase difference detected by the phase difference detection circuit, and aligning the phase of the data block of the first main signal with the data block of the second main signal, The first that matched
Of the main signal data block and the second main signal data block, and a first main signal output from the phase compensation circuit for delaying at least one data block length Delay circuit, a second delay circuit for delaying the second main signal output from the phase compensation circuit for at least one data block length, and the first delay circuit output from the first delay circuit. Main signal,
And a switching circuit that selectively supplies one of the second main signal output from the second delay circuit to the third transmission line, and the first transmission line as a current transmission line, When the second transmission path is used as a backup transmission path, the first bit error detection circuit detects a bit error in a data block having the first main signal, and the second bit error detection circuit detects the bit error. Second
When a bit error is not detected in the corresponding data block of the main signal, the switching control signal is supplied to the switching circuit, and the second main signal output from the second delay circuit is switched to the switching circuit. And a correlation monitoring circuit for supplying the third transmission line to the third transmission line. 2. The signal termination processing circuit has a failure detection means for monitoring the main signal to detect a failure upstream of the first transmission path and the second transmission path, and the correlation detection circuit includes: When the monitoring circuit uses the first transmission line as a working transmission line and the second transmission line as a backup transmission line and a failure is detected in the first transmission line, a bit error for each data block is detected. 2. The transmission according to claim 1, wherein the switching control signal is generated to switch the second transmission line to a working transmission line and the first transmission line to a standby transmission line regardless of whether or not Roadless switching device. 3. The hitless switching apparatus for a transmission line according to claim 1, wherein the data block is a data block having the bit error check information as a head. 4. The non-transmission path according to claim 3, wherein the correlation monitoring circuit generates the switching control signal immediately after the bit error detection circuit transmits the bit error check information. Instantaneous interruption switching device. 5. The ITU-T Recommendation G. 70
X and ANSI (American National Standards Inst
LOS (Loss O defined by SONET by itute)
f Signal), LOF (Loss Of Frame), AIS (Alar
(m IndicationSignal) or other alarm signal. 6. The bit error check information is ITU
-T Recommendation G. SONET by 70X and ANSI
The non-interruption switching apparatus for a transmission line according to claim 5, wherein the B3 byte is defined by B3. 7. The bit error check information is ITU
-T Recommendation G. SONET by 70X and ANSI
6. The non-instantaneous-interruption switching device for a transmission path according to claim 5, wherein the B2 byte is defined by B2. 8. The data block is defined by ITU-T Recommendation G.264. VC (Virtual Container) defined in 70X
The non-interruption switching device for a transmission line according to claim 1, wherein the switching device is a frame. 9. The data block is ITU-T Recommendation G. 1V with B3 byte defined in 70X as the head
9. The transmission line according to claim 8, wherein the transmission path is a data block having a C frame length, and the correlation monitoring circuit generates the switching control signal immediately after the bit error detection circuit receives the B3 byte. No-interruption switching device. 10. The data block is an STS SPE (Synchronouou) defined in SONET by ANSI.
s Transport Signal Synchronized PayloadEnvironment
) Frame or VT (Virtual Tributary) SP
The non-instantaneous switching device for a transmission path according to claim 1, which is an E frame. 11. The data block is a one-frame-length data block having a B3 byte defined in SONET according to ANSI as a head, and the correlation monitoring circuit receives the B3 byte by the bit error detection circuit. 11. The non-interruption switching device for a transmission path according to claim 10, wherein the switching control signal is generated immediately after. 12. The data block is ITU-T Recommendation G. 70X STM (Synchronous Tran)
sport module) frame.
The transmission line non-interruption switching device described in. 13. The data block is defined by ITU-T Recommendation G.264. 1 with the B2 byte specified in 70X as the head
13. The transmission path according to claim 12, wherein the transmission path is a data block having an STM frame length, and the correlation monitoring circuit generates the switching control signal immediately after the bit error detection circuit receives the B2 byte. No-interruption switching device. 14. The data block is an STS frame defined by ANSI.
The transmission line non-interruption switching device described in. 15. The data block is a one-frame-length data block beginning with B2 bytes defined in SONET according to ANSI, and the correlation monitoring circuit comprises:
The transmission path non-interruption switching apparatus according to claim 14, wherein the switching control signal is generated immediately after the bit error detection circuit receives the B2 byte. 16. The data block is ITU-T Recommendation I.T. The transmission line non-interruption switching apparatus according to claim 1, wherein the ATM cell is an ATM cell defined by H.432. 17. The bit error check information is IT
UT Recommendation I. H in the ATM cell defined in 432
17. The transmission path hitless switching device according to claim 16, which is an EC (Header Error Control) byte. 18. The bit error check information is data obtained by executing a bit interleave parity operation on the contents of the header area and the information area of the ATM cell. A non-instantaneous switching device for the described transmission path. 19. As a flow of a data block including bit error check information, the same main signal arriving through a first transmission line and a second transmission line is received and switched without interruption to a third transmission line. By supplying one of the first transmission path and the second transmission path as an active transmission path and the other as a backup transmission path, A step of receiving one and outputting it as a first main signal; a step of receiving the other of the same main signals and outputting it as a second main signal; and a bit error of the first main signal, Detecting each data block based on the bit error check information; detecting a bit error of the second main signal for each data block based on the bit error check information; First Detecting a phase difference between the main signal data block and the second main signal data block, and compensating for the phase difference detected by the phase difference detection circuit to obtain the first main signal data. The phase of the block and the data block of the second main signal are matched, and the first phase is matched.
The step of outputting the main signal data block and the second main signal data block, the step of delaying the phase-matched first main signal for at least one data block length, and the phase match Delaying the second main signal for at least one data block length, and using one of the delayed first main signal and the delayed second main signal for the third In the process of selectively supplying to the transmission path, and when the first transmission path is the working transmission path and the second transmission path is the backup transmission path, the first bit error detection circuit A bit error is detected in a data block having a main signal, and the second bit error detection circuit detects the second error.
When a bit error is not detected in the corresponding data block of the main signal, the switching control signal is generated and the delayed second main signal is supplied to the third transmission line. A method for switching a transmission line without interruption.