JPH09326426A - Apparatus and method for testing wafers - Google Patents

Abstract

PROBLEM TO BE SOLVED: To accurately and reliably test integrated circuit chips at once by providing a test head having probe units having plural probes. SOLUTION: A test head 52 comprises many probe units 56 disposed parallel in through-holes at the center of a disk-like support 58 as the number of lines of integrated circuit chips 24 on a wafer 22. Each probe unit 56 has probes 62 at the chuck top. The number of the units 56 is greater than that of outer electrodes of all the integrated circuit chips 24 arranged in line under test. After aligning an origin mark of the head 52 with a second position mark 28 of the wafer 22, a Z-stage is driven to lift the chuck top by specified length to press all terminals of the wafer 22 on the chuck top to the probes 62, thereby measuring electric characteristics of the chips 24 in this condition.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for inspecting electrical characteristics of multiple integrated circuit chips on a wafer.

[0002]

2. Description of the Related Art An electronic circuit die, that is, an integrated circuit chip formed on a wafer is subjected to a current test by a wafer prober or a wafer inspection apparatus using an inspection head generally called a probe card or a probe board. Be seen. Since the conventional wafer inspection apparatus only uses the inspection head in which a plurality of probe needles are radially arranged on the disk-shaped support, it is possible to inspect several integrated circuit chips on the wafer at the same time. It is only possible, and therefore, it takes a lot of time to inspect a single wafer on which a large number of integrated circuit chips are formed, and a large area for moving the wafer is required.

As one of the inspection heads for solving the above-mentioned problems, an inspection head provided with a plurality of probe units in which a plurality of probe needles are arranged at the lower end edge of a flat plate-shaped support extending horizontally is proposed. (Japanese Patent Laid-Open No. 7-201
935). If this inspection head is used, it is possible to simultaneously inspect a large number of integrated circuit chips at the same time, and the range in which the wafer is moved becomes narrow.

[0004]

SUMMARY OF THE INVENTION An object of the present invention is to enable a plurality of integrated circuit chips to be collectively and accurately inspected at the same time.

[0005]

An inspection apparatus according to the present invention includes an inspection head having a plurality of probes and at least a wafer around a vertical axis of the wafer for detecting a first alignment mark formed on the wafer. Coarse alignment means for roughly aligning the wafer by rotating the wafer and at least two-dimensionally moving the wafer to detect two or more second alignment marks formed at intervals on the wafer. Precision alignment means for performing precise alignment of the wafer. The precision alignment means includes a pressing means for bringing the terminal portion of the integrated circuit chip into contact with the probe so as to collectively measure the electrical characteristics of the integrated circuit chips formed on the wafer. The inspection head includes a plurality of probe units each having a plurality of probes.

The wafer is roughly aligned by first detecting the first alignment mark such as a notch, a notch like an orientation flat, or an optical mark while rotating the wafer about its vertical axis. Then, at least the wafer is two-dimensionally moved and fine alignment is performed by detecting the plurality of second alignment marks. After that, the electrical characteristics of the plurality of integrated circuit chips are collectively measured by an inspection head including a plurality of probe units each having a plurality of probes. All the integrated circuit chips formed on one wafer may be measured simultaneously, or all the integrated circuit chips formed on one wafer may be measured several times.

Therefore, according to the present invention, a large number of integrated circuit chips formed on a wafer can be inspected accurately and reliably with a small number of times.

In a preferred embodiment, the inspection head further includes a support base having a through hole, and the probe unit is arranged in parallel with the through hole.

It is preferable that the inspection head has more probes than the total number of terminal portions of the integrated circuit chips formed on the wafer. As a result, all the integrated circuit chips formed on the wafer can be accurately and reliably inspected at one time, and it is not necessary to move the wafer largely during the inspection. However, the inspection head may have a plurality of probe groups corresponding to each integrated circuit chip in order to inspect all the integrated circuit chips formed on the wafer 2 to 4 times.

The rough aligning means includes a plurality of guides having an outer peripheral edge portion of the wafer spaced apart from each other, a rotating means for rotating the wafer around the vertical axis of the wafer in a state of abutting the guide. Detecting means for detecting the first alignment mark of the wafer being processed. In this case, the wafer is rotationally moved to a position where the detection means detects the first alignment mark and stopped at that position.

In a preferred embodiment, the precision alignment means further includes an origin mark formed on the inspection head and the second alignment mark corresponding to the second alignment mark.
Of the alignment mark, the chuck top for receiving the wafer, and the position of the chuck top about an axis perpendicular to the wafer.
A stage, a Z stage for adjusting the position of the chuck top in the direction of the axis perpendicular to the wafer using a fluid cylinder mechanism, and an XY stage for adjusting the position of the chuck top in a plane parallel to the wafer. . The pressing means is the Z stage.

The coarse alignment means and the fine alignment means may be arranged in the same station, or the coarse alignment means may be arranged in the coarse alignment station and the fine alignment means may be arranged in the fine alignment station. It may be placed at. In the latter case, it is preferable to include a delivery machine for delivering the wafer.

The inspection head is provided with a probe unit which is equal to or larger than the total number of rows of integrated circuit chips formed on the wafer, and each probe unit is equal to or larger than the total number of terminal portions of the integrated circuit chips for one row formed on the wafer. Can have.

The method of inspecting a wafer according to the present invention comprises rotating the wafer at least about its vertical axis to electrically or mechanically detect the first alignment mark formed on the wafer. Rough alignment,
Then two or more second spaced apart wafers are formed.
Precision alignment of the wafer by at least two-dimensionally moving the wafer in order to detect the alignment mark, and then to collectively measure the electrical characteristics of a plurality of integrated circuit chips formed on the wafer. Contacting the terminal portion of the integrated circuit chip with the probe of the inspection head.

The second alignment mark is one reference mark for alignment, and the origin mark is the other reference mark for alignment. The first and second alignment marks are formed outside or inside the pattern area of the wafer.

[0016]

1 to 3, an inspection apparatus 10 includes a cassette station in which two wafer cassettes 12 and 14 are arranged and a rough alignment station in which a rough alignment mechanism 16 is arranged. And a precision alignment station / inspection station in which the precision alignment mechanism 18 is arranged, and a delivery station in which a wafer delivery robot or a wafer delivery machine 20 is placed.

Each wafer 22 has a circular shape as shown in FIG. A large number of electronic circuit dies or integrated circuit chips 24 are formed in a matrix on the wafer 22. Each chip row of the wafer 22 has a plurality of integrated circuit chips 24 in the illustrated example. Each wafer 2
2 is a first alignment mark 2 formed on the outer periphery of the first alignment mark 2
6 and a plurality of (a pair in the illustrated example) second alignment marks 28 formed at intervals on the surface to be inspected.

In the illustrated example, the first alignment mark 26 is a small notch or notch formed on the outer peripheral portion of the wafer 22, but it may be a large notch such as an orientation flat. Both the notch and the orientation flat are notches formed on the existing wafer.
Reference numeral 6 may be a notch formed in the wafer other than the notch and orientation flat.

The second alignment mark 28 is one reference mark that serves as a reference for alignment, and may be a cross-shaped mark that can be photographed by a television camera. Such a second alignment mark 28 is provided on the integrated circuit chip 2
4 can be formed in the same manner as the integrated circuit chip 24. In the illustrated example, two second alignment marks 28 are formed on each wafer 22, but, for example, 3, 4 or more second alignment marks 28 may be formed on each wafer 22. .

The second alignment mark 28 is, in the illustrated example, outside the effective area or pattern area including the integrated circuit chips 24 and the cut areas (scribe lines) that divide them, and is symmetrical with respect to the center of the wafer 22. Is formed in position. However, the second alignment mark 2
8 may be formed in the pattern area, or the wafer 2
It may be formed in an asymmetric position with respect to the center of 2.

When the second alignment mark 28 is formed in the pattern area, the cross-shaped intersection of the cutting area may be used as the second alignment mark, or if it can be photographed by the television camera. An appropriate part in one or more integrated circuit chips 24 may be used as the second alignment mark, and further, instead of forming the integrated circuit chip 24, the second alignment mark may be formed in that part. Good. Second
The wafer can be effectively used if the alignment mark of 1 is formed outside the pattern region or the cross-shaped intersection of the cutting region is used as the second alignment mark.

One wafer cassette 12 accommodates a plurality of uninspected wafers 22, and the other wafer cassette 1
4 stores a plurality of inspected wafers 22. The wafer cassettes 12 and 14 are installed in cassette elevators 30 and 32 that adjust the height position of the wafer 22 with respect to the delivery machine 20, respectively.

The coarse alignment mechanism 16 includes a coarse alignment stage 34, a θ stage 36 installed on the coarse alignment stage, a disc-shaped turntable 38 rotated by the θ stage, and a coarse alignment. A pair of guides 40 provided at intervals on the stage 34, and a sensor 42 for sensing the first alignment mark 26 of the wafer 24 on the turntable 38 are provided.

The turntable 38 receives the wafer 24 horizontally. The θ stage 36 has a rotation source that rotates the turntable 38 once or more around its central axis. The guide 40 has the shape of a cylindrical roller protruding upward from the turntable 38, and is separated from the central axis of the turntable 38 by a distance equal to the radius of the wafer 24.

The sensor 42 is an optical sensor having a light emitting element and a light receiving element. The light ray from the light emitting element is directed to the outer periphery of the back surface of the wafer 24 on the turntable 38, and the light ray reflected from the wafer 24 is reflected. Is detected by the light receiving element. Both guides 40 and the sensor 42 are provided so that each is located in the corner part of a triangle.

The precision alignment mechanism 18 includes a gripping means or a chuck top 44 for horizontally receiving and gripping the wafer 24, a θ stage 46 for angularly rotating the chuck top about its central axis, and the θ stage. Z stage 48 for moving the Z axis in the direction of the central axis (vertical direction), an XY stage 50 for two-dimensionally moving the Z stage in a horizontal plane, and an inspection head arranged above the circular chuck top 44. 52 and a pair of alignment cameras 54 for photographing the second alignment mark 28. The Z stage 48 includes a cylinder mechanism as a drive source.

In the inspection head 52, the same number of rows of integrated circuit chips 24 formed on the wafer 22, that is, the same number of chip rows as the probe units 56, are arranged in parallel with a through hole formed in the center of a disk-shaped support 58. And a pair of origin marks 60 corresponding to the second alignment marks 28 of the wafer 24.

Each probe unit 56 corresponds to a chip row of the wafer 22, and the chuck tops 44 are provided with a number of probes 62 which is equal to or larger than the number of external electrodes, that is, terminal portions of all the integrated circuit chips 24 constituting the corresponding chip row. Have on the side of. Each terminal portion individually corresponds to the probe 62. As each probe unit 56, Japanese Patent Laid-Open No. 7-201
Those described in Japanese Patent No. 935 can be used.

Each origin mark 60 is the other reference mark which serves as a reference for alignment, and the second alignment mark 28.
The cross-shaped mark is the same as, and is provided at a position corresponding to the position of the second alignment mark 28 on the wafer 24. Each origin mark 60 is formed by forming a cross-shaped mark on a transparent plate such as a transparent glass plate and arranging and fixing the transparent plate in a through hole formed at a predetermined position of the support base 58. To be done.

Each alignment camera 54 is a television camera, particularly a dual focus camera, and is attached to the frame of the inspection device so that the tip 54b of the lens barrel 54a, which is the optical system thereof, is directly above the origin mark 60. ing.

The delivery machine 20 includes a drive mechanism 62 and a delivery arm 64 driven by the drive mechanism. The transfer machine 20 transfers the wafer 22 to the wafer cassette 12
To the turntable 38, from the turntable 38 to the chuck top 44, and from the chuck top 44 to the wafer cassette 14, the wafer 22 is transferred between them.

Although not shown, the inspection apparatus 10 includes a rough alignment mechanism 16, a fine alignment mechanism 18, and a delivery machine 2.
0, the cassette elevators 30, 32, the sensor 42, the inspection head 52, the alignment camera 54, and the like, and a control device that processes signals from them.

At the time of inspection, first, the wafer 22 in the wafer cassette 12 is taken out from the delivery arm 64 and transferred onto the turntable 38 of the rough alignment mechanism 16. At this time, the wafer 22 is arranged so that the outer peripheral surface thereof abuts on both guides 40. Thereby, the wafer 22
Of the turntable 38 coincides with the axis of the turntable 38.

Next, the sensor 42 of the coarse alignment mechanism 16
The turntable 38 is rotated by the θ stage 36 about its axis until is sensed by the first alignment mark 26 on the wafer 22. First alignment mark 26
Is sensed by verifying in the controller that reflected light from the wafer 22 is no longer incident on the sensor 42. The rotation of the turntable 38 is stopped when the first alignment mark 26 is sensed. This completes the alignment of the wafer 22 with respect to the central axis of the turntable 38, that is, the rough alignment.

Next, the wafer 2 for which the rough alignment has been completed
2 is transferred from the turntable 38 to the chuck top 44 of the precision alignment mechanism 18 by the delivery arm 64.
Since the rough alignment of the wafer 22 on the chuck top 44 has already been completed, the wafer 22 is placed so that the second alignment mark 28 of the wafer 22 substantially coincides with the origin mark 60 of the inspection head 52. To be done.

Then, the focus of each alignment camera 54 is focused on the origin mark 60, and each origin mark 60 is photographed by the alignment camera 54. The image signals output from both alignment cameras 54 are supplied to the control device. This control device obtains the coordinate position of the origin mark 60 by an image processing technique based on the input image signal, and stores the obtained coordinate position in a memory.

Next, the focus of each alignment camera 54 is focused on the second alignment mark 28, and each second alignment mark 28 is photographed by the alignment camera 54. The image signals output from both alignment cameras 54 are also supplied to the control device and used in the control device for calculating the coordinate position of the second alignment mark 28.

The control device compares the coordinate position of the origin mark 60 with the coordinate position of the second alignment mark 28, and controls the θ stage 46 and the XY stage 50 of the precision alignment mechanism 18 so that they match. Drive it. When the coordinate position of the origin mark 60 and the coordinate position of the second alignment mark 28 match, the precision alignment of the wafer 22 ends.

Then, the Z stage 48 of the precision alignment mechanism 18 is driven to raise the chuck top 44 by a predetermined amount. As a result, the wafer 22 on the chuck top 44 has all its terminal portions pressed by the probe 62 of the inspection head 52, and in this state, inspection is performed to measure the electrical characteristics of the integrated circuit chip 24. At this time, since the Z stage 48 has a cylinder mechanism as a drive source,
All the terminal portions formed on one wafer 22 are surely pressed by the probe 62 with a predetermined pressure.

Next, the wafer 22 on the chuck top 44 is transferred to the wafer cassette 32 by the transfer arm 64.
Moved to. In parallel with the precision alignment and the inspection in the precision alignment mechanism 18, the next coarse / dense alignment of the wafer 22 is performed in the rough alignment mechanism 16.

In the above-mentioned apparatus, the inspection head 52 has the probes 62 which are equal to or more than the total number of terminal portions formed on one wafer 22, and each terminal portion corresponds to the probe 62, so that one wafer 22 is provided. All the integrated circuit chips formed on the substrate can be inspected accurately and surely at one time.

Further, since all the integrated circuit chips formed on one wafer 22 can be inspected at once at the same time, all the integrated circuit chips formed on one wafer are inspected in multiple times. Wafer 2 compared to the case
The range in which the XY stage 50 of the precision alignment mechanism 18 moves the 2 is narrowed, and the inspection can be performed in a short time.

Further, since the Z stage 48 uses the cylinder mechanism as a drive source, the pressing force between the probe and the terminal portion does not become insufficient, and as a result, one wafer 22
Since all of the terminal portions formed on the probe 62 can be reliably pressed against the probe 62, more accurate and reliable inspection can be performed. On the other hand, when the electric motor is used as the drive source of the Z stage, the pressing force between the probe and the terminal portion is insufficient,
As a result, the terminal portion may not be pressed against the probe with a predetermined force.

FIG. 4 shows that, instead of the origin mark 60 shown in FIG. 3, the tip end 5 of the lens barrel 54a of the alignment camera 54 is used.
This is an example in which 4b is used as an origin mark. Cutting edge 5
4b is arranged and fixed in a through hole provided in the support base 58. In the example shown in FIG. 4, the second alignment mark 28 is formed at a position different from the example shown in FIGS. 1 to 3, and therefore the origin mark, that is, the lens barrel 54b is also formed in FIG.
-It is arrange | positioned in the position different from the example shown in FIG.

At the time of inspection, the lens barrel 5 of the alignment camera 54
4a is connected to the corresponding leading edge 54b and the wafer 22
The second upper registration mark 28 is photographed. The image signal output from the alignment camera 54 is used to calculate the coordinate position of the second alignment mark 28. The calculated coordinate position is used to control the precision alignment mechanism 18 so that the second alignment mark 28 comes to a predetermined position.

The present invention is not limited to the above embodiment. For example, instead of optically detecting the notch of the wafer, it may be magnetically, electrically or mechanically detected. Similarly, instead of using an alignment camera to detect the second alignment mark on the wafer, other means may be used to detect it optically, electrically or mechanically. Further, instead of forming one notch in the wafer, a plurality of notches may be formed in the wafer to detect them, or a plurality of locations in one notch may be detected.

As long as the first alignment mark is a mark which can be detected optically, magnetically, electrically or mechanically by rotating the wafer, it is formed on the outer peripheral portion of the wafer as in the above embodiment. It may be a mark other than the cutout portion. For example, a linear or V-shaped mark or recess formed inside or outside the pattern area of the wafer may be used as the first alignment mark.

Further, an inspection head may be used which inspects all the integrated circuit chips formed on one wafer in two or three times. In this case, the chuck top is lowered by the Z stage, then moved by the XY stage in the direction of the chip row or at a right angle to it, and then raised again by the Z stage, before the next group of inspections. The terminals of the next group of integrated circuit chips are pressed against the probe of the inspection head.

[Brief description of drawings]

FIG. 1 is a diagram showing one embodiment of an inspection apparatus of the present invention.

FIG. 2 is a diagram showing an example of a positional relationship between a wafer and an inspection head in the inspection apparatus of FIG.

3 is a perspective view showing an embodiment of a positional relationship among a wafer, an inspection head, and an alignment camera in the inspection apparatus of FIG.

FIG. 4 is a perspective view showing another embodiment of the positional relationship among the wafer, the inspection head, and the alignment camera.

[Explanation of symbols]

 10 Inspection Device 16 Coarse Alignment Mechanism 18 Precision Alignment Mechanism 20 Wafer Transfer Machine (Robot) 22 Wafer 24 Integrated Circuit Chip 26 First Alignment Mark 28 Second Alignment Mark 36 θ Stage 38 Turntable 40 Guide 42 Second 1 Alignment mark detection sensor 44 Chuck top 46 θ stage 48 Z stage 50 XY stage 52 Inspection head 54 Alignment camera 56 Probe unit 58 Support base 60 Origin mark 54a Lens barrel 54b Cutting edge of lens barrel as origin mark

Claims (8)

[Claims] 1. An inspecting head having a plurality of probes, and rough alignment of a wafer by rotating at least the wafer about its vertical axis to detect a first alignment mark formed on the wafer. Coarse alignment means for performing precise alignment of the wafer by at least two-dimensionally moving the wafer to detect two or more second alignment marks formed at intervals on the wafer. The precision alignment means includes a pressing means for contacting the terminal portion of the integrated circuit chip with the probe in order to collectively measure the electrical characteristics of the plurality of integrated circuit chips formed on the wafer. Prepare,
The inspection head includes a plurality of probe units, each of which has a plurality of probes. 2. The inspection apparatus according to claim 1, wherein the inspection head further includes a support base having a through hole, and the probe unit is arranged in parallel with the through hole. 3. The inspection apparatus according to claim 1, wherein the inspection head has probes which are equal to or more than the total number of terminal portions of integrated circuit chips formed on a wafer. 4. The rough alignment means includes a plurality of guides having an outer peripheral edge portion of the wafer spaced apart from each other, and a rotating means for rotating the wafer around a vertical axis of the wafer while the wafer is in contact with the guide. The inspection apparatus according to claim 1, further comprising: a detection unit that detects the first alignment mark of the rotating wafer. 5. The double focus for photographing the origin mark formed on the inspection head and the second alignment mark corresponding to the second alignment mark, the precision alignment means further comprising: A camera, a chuck top that receives the wafer, a θ stage that adjusts the position of the chuck top around an axis that is perpendicular to the wafer, and a position of the chuck top in the axial direction that is perpendicular to the wafer by using a fluid cylinder mechanism. 5. A Z stage for adjusting the chuck top and an XY stage for adjusting the position of the chuck top in a plane parallel to the wafer, wherein the pressing means is the Z stage. Inspection equipment. 6. The inspection apparatus according to claim 1, wherein the first and second alignment marks are formed outside or inside the pattern area of the wafer. 7. Coarse alignment of the wafer by rotating at least the wafer about its vertical axis to electrically or mechanically detect a first alignment mark formed on the wafer, and then Fine alignment of the wafer by at least two-dimensionally moving the wafer to detect two or more second alignment marks formed at intervals on the wafer, and then multiple integrations formed on the wafer. A method of inspecting a wafer, comprising contacting a terminal portion of the integrated circuit chip with a probe of an inspection head so as to collectively measure electrical characteristics of the circuit chip. 8. The inspection method according to claim 7, wherein the first and second alignment marks are formed outside or inside the pattern region of the wafer.