JPH09319474A - Power source controller for multiprocessor system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption at the time of degenerate operating at a multiprocessor system. SOLUTION: A managing table 10 stores valid/invalid information with which it is shown by a disconnection control program 11 whether respective CPU 1-3 are valid or invalid. Based on the contents in the managing table 10, a power source control program 13 sets a valid/invalid bit showing whether the respective CPU 1-3 are valid or invalid to a register inside a power source control part 12. Based on the valid/invalid bit set to the register, the power source control part 12 determines any CPU to stop power supply. Namely, the CPU of which the valid/invalid bit is made invalid (the CPU disconnected from the system) is defined as the CPU to stop power supply. According to that determination, a power source unit 5 is controlled and the power supply to the disconnected CPU is stopped.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system for performing a degenerate operation by disconnecting a faulty processor, and more particularly to a multiprocessor system for controlling power supply to each CPU constituting the multiprocessor system. Power control device.

[0002]

2. Description of the Related Art Conventionally, in a multiprocessor system, a CPU in which a failure has occurred is separated and a degenerate operation is performed (for example, Japanese Patent Laid-Open No. 4-18).
1438).

FIG. 4 is a block diagram showing the configuration of the above-mentioned conventional multiprocessor system. The conventional multiprocessor system shown in FIG. 4 has three CPUs 1.
3 to 3 share the processing, and are provided with a common memory 4, a power supply unit 5 ', and a logging memory 9 composed of a non-volatile memory.

The common memory 4 stores an error processing program 6, a hardware diagnostic program 7, an intermittent failure detection program 8, a management table 10 and a disconnection control program 11.

The management table 10 has entries corresponding to the CPUs 1 to 3, and each entry has CPUs 1 to 3.
Validity / invalidity information indicating whether is valid or invalid and the assigned processing content are set.

The error processing program 6 runs on the CPU 1 and performs predetermined error processing such as error display processing and system down processing, and processing for writing failure information in the logging memory 9.

The hardware diagnostic program 7 runs on each of the CPUs 1 to 3 when the power is turned on, and controls the disconnection.
The PU (CPU1 in this example) is notified of the diagnosis result.

The intermittent failure detection program 8 is run by the CPU 1 when the power is turned on. If the CPU in which the intermittent failure has occurred is recorded by searching the logging memory 9, the intermittent control program 11 will experience the intermittent failure. The CPU number of the CPU that made the notification is notified.

The disconnection control program 11 is the CPU 1
CP running in a car and suffering from hardware failure or intermittent failure
By setting valid / invalid information indicating invalidity in the entry of the management table 10 corresponding to U, the CPU in which the hardware fault or the intermittent fault has occurred is separated.

Next, the operation will be described.

When a processing request is issued to each of the CPUs 1 to 3,
After referring to the management table 10 to recognize the requesting CPU and storing the processing request content in the common memory 4, the requesting CPU
Interrupt After receiving the interrupt, the CPU stores the processing result in the common memory 4 after performing the predetermined processing, and notifies the requesting CPU of the completion of the processing.

The above operation is performed when each of the CPUs 1 to 3 is normal. However, if any of the CPUs fails,
The following operation is performed.

When a fault such as a parity error occurs in any of the CPUs, the faulty CPU recognizes the CPU (CPU1) that performs the error processing and interrupts the CPU1. The CPU 1 that has received the interrupt runs the error processing program 6. As a result, the error processing program 6 performs predetermined error processing, reads out failure information from the CPU 3 in which the failure has occurred due to inter-processor communication, and records it in the logging memory 9.

After that, the restart process is performed, and the following process is performed in the initialization process. First, each C
The PUs 1 to 3 run the hardware diagnostic program 7 to diagnose each part of the hardware and notify the CPU 1 in charge of processing of the diagnostic result via the common memory 4.

Upon receipt of the notification, the CPU 1 runs the disconnection control program 11. When the disconnection control program 11 detects a faulty CPU based on the diagnosis result, it sets invalid information in the entry corresponding to the faulty CPU in the management table 10 to invalidate the CPU. Due to this invalidation, the CPU is disconnected.

Subsequently, the CPU 1 runs the intermittent failure detection program 8. The intermittent failure detection program 8 searches the logging memory 9 and, if information indicating that an intermittent failure has occurred in a certain CPU is recorded, the C of that CPU is recorded.
The PU number is disconnected and the control program 11 is notified. As a result, the disconnection control program 11 causes the management table 1 to operate similarly to the disconnection processing when a hardware failure occurs.
0 is updated and the CPU is disconnected.

[0017]

As described above, in the conventional multiprocessor system, the C in which the failure has occurred.
It just disconnects the PU, and does not perform processing such as stopping the power supply to the disconnected CPU. For this reason, there is a problem that useless power consumption is performed by the CPU having the failure.

Therefore, an object of the present invention is to provide a power supply control device in a multiprocessor system which can reduce power consumption during degenerate operation.

[0019]

In order to achieve the above object, the present invention provides a multiprocessor system in which a CPU having a failure is disconnected and a degenerate operation is performed. A power supply unit capable of individually supplying electric power to the CPU and a CPU separated from the other CPUs by controlling the power supply unit
And a power supply control unit for stopping the power supply to the.

When the faulty CPU is disconnected, the power supply controller controls the power supply unit to stop the power supply to the disconnected CPU.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. In the multiprocessor system shown in the figure, the three CPUs 1 to 3 share the processing, and are provided with a common memory 4, a power supply unit 5, a logging memory 9, and a power supply control unit 12.

The common memory 4 stores an error processing program 6, a hardware diagnostic program 7, an intermittent failure detection program 8, a management table 10, a disconnection control program 11, and a power supply control program 13. Here, the error processing program 6, the hardware diagnosis program 7, the intermittent failure detection program 8, the management table 1
The 0 and the separation control program 11 are the same as those shown in the conventional example of FIG. Power control program 1
After the processing by the disconnection control program 11 is completed, the CPU 3 reads the valid / invalid information of each CPU 1 to 3 from the management table 10, and registers each CP in the register in the power control unit 12.
Set the valid / invalid bit indicating the valid / invalid of U.

The power supply unit 5 is a power supply unit capable of individually supplying power to the CPUs 1 to 3.

The power supply controller 12 controls the power supply unit 5 to control the power supply to the CPUs 1-3. FIG. 2 is a block diagram showing a configuration example of the power supply control unit 12, which is composed of a register 14 and a control circuit 15.

The register 14 is a 3-bit register in which valid / invalid bits indicating valid / invalid of the CPUs 1 to 3 are set, and the first bit to the third bit are C respectively.
It corresponds to PU1-3. In this embodiment, “1” = valid,
"0" = invalid. The control circuit 15 has a register 1
Based on the valid / invalid bit set to 4, the CPU to stop the power supply is determined, and the power supply unit 5 is controlled according to the determination.

Next, the operation of this embodiment will be described.

If there is no fault in each of the CPUs 1 to 3, the same operation as that of the conventional example described above is performed, but if a fault occurs in any of the CPUs 1 to 3, the process shown in the flowchart of FIG. 3 is performed.

When a hardware failure or an intermittent failure occurs in any of the CPUs 1 to 3 (step 1
00), the faulty CPU performs error processing C
A PU (CPU1) is recognized and an error interrupt is issued to the CPU1 (step 101).

The CPU 1 which has received the interrupt runs the error processing program 6. As a result, the error processing program 6 performs predetermined error processing, reads out the failure information from the CPU in which the failure has occurred through inter-processor communication, and records it in the logging memory 9 (step 102).

After that, when the reboot is started (step 103), each CPU 1 to 3 runs the hardware diagnostic program 7 to diagnose each part of the hardware,
The diagnosis result is notified to the CPU 1 in charge of processing via the common memory 4 (step 104).

Upon receipt of the notification, the CPU 1 runs the disconnection control program 11. When the disconnection control program 11 detects a failed CPU based on the diagnosis result, it sets invalid information in the entry corresponding to the failed CPU in the management table 10 and disconnects the CPU from the system (step 105). .

Subsequently, the CPU 1 runs the intermittent failure detection program 8. As a result, the intermittent failure detection program 8 searches the logging memory 9 and, if information indicating that an intermittent failure has occurred in a certain CPU is recorded, notifies the CPU number of that CPU to the control program 11. (Step 106). When the CPU number is notified, the disconnection control program 11 causes the management table 10
The CPU in which the intermittent failure has occurred is separated by writing invalid information in the entry corresponding to the CPU number in the inside (step 107).

When the processing by the disconnection control program 11 is completed, the CPU 1 causes the power supply control program 13 to run. As a result, the power supply control program 13 reads valid / invalid information indicating validity / invalidity of each of the CPUs 1 to 3 from the management table 10, and the register 1 in the power supply control unit 12 is read.
A valid / invalid bit (valid = “1”, invalid = “0”) indicating valid / invalid of each of the CPUs 1 to 3 is set to each bit of 4 (step 108).

The control circuit 15 in the power supply controller 12 determines the CPU to stop the power supply based on the value of each bit of the register 14 (step 109). That is, "0"
The CPU corresponding to the bit for which is set (disconnected CPU) is the CPU that stops the power supply.

After that, the control circuit 15 controls the power supply unit 5
To the CPU to stop the power supply to the separated CPU (step 110). This completes the power supply control. In this way, by stopping the power supply to the separated CPU, the power consumption can be saved accordingly.

In the above-described embodiment, the multiprocessor system having three CPUs has been described as an example, but the number of CPUs is not limited to this.

[0038]

As described above, according to the present invention, since the power supply control unit for stopping the power supply to the CPU disconnected due to the occurrence of the failure is provided, the power consumption during the degenerate operation of the multiprocessor system is disconnected. CPU
There is an effect that you can save only the amount that was consumed.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of a power supply control unit 12.

FIG. 3 is a flowchart illustrating a processing example of the embodiment.

FIG. 4 is a block diagram of a conventional example.

[Explanation of symbols]

 1-3 ... CPU 4 ... Common memory 5 ... Power supply unit 6 ... Error processing program 7 ... Hardware diagnostic program 8 ... Intermittent failure detection program 9 ... Logging memory 10 ... Management table 11 ... Disconnection control program 12 ... Power supply control unit 13 ... Power supply control program 14 ... Register 15 ... Control circuit

Claims (3)

[Claims] 1. A multiprocessor system for performing a degenerate operation by disconnecting a faulty CPU, and a power supply unit capable of individually supplying electric power to each CPU constituting the multiprocessor system, A power supply control device in a multiprocessor system, comprising: a power supply control unit for controlling a power supply unit to stop power supply to a separated CPU among the CPUs. 2. The power supply control unit includes a register in which information indicating validity / invalidity of each CPU is set, and a control circuit which controls the power supply unit based on the information set in the register. The power supply control device in the multiprocessor system according to claim 1, wherein 3. The power supply control device in a multiprocessor system according to claim 2, wherein the failure is a hardware failure or an intermittent failure.