JPH09269896A - Booting method for firm cpu - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a booting method for firm CPU unnecessitating ROM for boostrap. SOLUTION: At the time of starting power supply, main CPU 1 is made to operate and CPU 2 of a firm is made into a resetting state. In the state, CPU 1 expands the program of CPU 2 from a main memory to a common memory 6. After expansion, CPU 1 releases the resetting of CPU 2. When resetting is released, CPU 2 activates CS0 to access to the common memory 6 to start boot processing. CPU 2 makes the chip select of its own memory 7 to be CS1 and copies all the contents of the common memory 6 in its own memory 7 within CPU 2. After finishing copying, CPU 2 makes its own memory 7 the same address as he common memory 6 and moves the address of the chip select CS0 of the common memory 6 to an area where its own memory 7 originally exists.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a firmware CPU boot method for loading a program from a main CPU to a firmware CPU in a multiprocessor system.

[0002]

2. Description of the Related Art There is an apparatus or method for bringing a target state by a first few instructions. Conventionally, in the multiprocessor system, when a program is loaded from the main CPU to the firmware CPU, the firmware CPU needs a ROM for booting. In a computer, a short program for reading a program is read by a shorter program. Such a short program is called a bootstrap and is written in the ROM.

[0003]

However, the conventional boot method has a problem that the boot ROM is required for each firmware CPU, and the mounting space and cost are increased. Also, it was necessary to create and manage two programs, firmware and a boot program.

The present invention has been made in view of the above circumstances, and an object thereof is to provide a boot method for a firmware CPU that does not require a ROM for bootstrap.

[0005]

In order to solve the above-mentioned problems, in the boot method of the firmware CPU of the present invention, firmware C is used.
The boot ROM of the PU is replaced with the common memory of the main CPU. Specifically, the following steps were performed.

When the power of the apparatus is turned on, the main CPU 1 operates and the firmware CPU 2 is in a reset state in the first stage. In this state, the main CPU 1 expands the program of the firmware CPU 2 from the main memory 8 to the common memory 6. Second stage, after the second stage the main CPU1 releases the reset of the firmware CPU2, and the third stage. When the reset is released, the firmware CPU2 activates the chip select CS0 and the common memory 6 is accessed to boot. Fourth stage of starting processing, the firmware CPU2 sets the chip select of its own memory 7 to CS1, and sets the contents of the common memory 6 to the firmware CPU2.
5th step of copying all to the own memory 7 in the internal memory, 6th step of making the own memory 7 the same address as the common memory 6 after the completion of copying, and the address of the chip select CS0 of the common memory 6 to the own memory 7. 7th stage to move to the area where 7 was.

Thus, the program can be loaded from the main CPU to the firmware CPU in the multiprocessor system without preparing a boot ROM.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION

[Configuration] FIG. 1 shows a configuration diagram of a multi-CPU using one embodiment of the present invention. CPU 1 in the line management unit
It becomes U and writes a program or the like to the common memory 6 from the external storage device such as a hard disk (not shown) or the ROM / RAM in the line management unit via the man-machine I / F control unit, and the data is stored in the firmware. It is loaded into its own memory 7 of the CPU 2, which is the CPU. At that time, CP
U2 is reset and released by I / O in the line management unit.
Do with. 1

[Operation] FIG. 2 shows the operation of one embodiment of the present invention.
It will be described based on. (1) When the power is turned on, the main CPU 1 (hereinafter, unit C
PU1) is in operation, and firmware CPUs 2 (hereinafter referred to as unit CPU1) to 5 are in reset state. (2) The CPU 1 loads the program of the CPU 2 from the ROM / RAM into the common memory 6. (3) CPU1 cancels the reset of CPU2. (4) When the reset is released, the CPU 2 activates the chip select CS0 and the common memory 6 is accessed to start the boot process (FIG. 2A) q (5) The contents of the common memory 6 are stored in the CPU 2 Own memory 7
Copy everything to. In this case, the chip select of the own memory 7 is CS1. (6) After completion of copying, the own memory 7 is set to the same address as the common memory 6. At this point, the common memory 6 is preferentially accessed (FIG. 2B). (7) Set the address (CS0) of the common memory 6 to the own memory 7
Move to the area where there was (Fig. 2 (b)). (8) With the above, the startup of the CPU 2 is completed, and the CPU 2 notifies the completion to the CPU 1 through the common memory 6. (9) Upon recognizing the completion, the CPU 1 sequentially releases the reset of the CPUs 3 to 5 and performs the boot process, similarly to the case of performing the process to the CPU 2. (11) The common memory 6 will be used as a communication means with the firmware thereafter.

(Structure of Line Measuring Device) Next, the structure of the line measuring device using the present invention will be described with reference to FIG. The line measuring device includes a man-machine interface (man-machine I / F) control unit 10, a line management unit 20, and four line control units 30. Man-machine I / F
The control unit 10 allows the operator to set various test operation modes for line testing, set and display test condition data, display test results, and the like. The line management unit 20 is a man-machine I /
Parameters such as a call control sequence and a test condition are received from the F control unit 10, and each line control unit 3 receives the parameters according to the conditions.
0 is managed. The line control unit 30 performs measurement under the control of the line management unit 20.

The line management unit 20 includes a line management CPU 21,
The line management CPU 21 is a circuit including a multi-port RAM 22, a ROM 23, and a RAM 24.
And the multi-port RAM 22 corresponds to the common memory 6. The line management unit 20 gives an instruction to each line control unit according to the test conditions. Test status, result is multiport R
It is received from the line control unit 30 through the AM 22, the total is calculated, and the man-machine I / F control unit 10 is notified.

The line control unit 30 includes a line control CPU 31,
It is composed of a memory (RAM) 32, eight signal processing units 33, and a line unit 34 of 16. In addition, each signal processing unit 33
Is connected to the two line units 34. That is, the line measuring device accommodates 64 line units 34. Here, the line control CPU 31 corresponds to the firmware CPU 2,
The RAM 32 corresponds to the own memory 7.

Specifically, the line controller 30 will be described with reference to FIG.
The procedure for starting the program will be described. (A) The man-machine I / F control unit 10 prior to resetting the line control unit 3
The program of the line control unit 30 (address 0 to
100,000 address) is transferred. (B) After reset release of the line control unit 30, CS0 becomes active, and the reset vector at address 0 of the common memory jumps to the boot unit. (C) The CS1 base address is set to 400,000 and the area size is set to 1 Mbyte. (D) The program is transferred from the address 0 of the common memory 6 to the own memory 7 (address 400,000) of the line control unit 30. (E) The own memory 7 has the same address as the common memory 6. (F) Change the base address of CS0 to 400,000.

By these processes, the own memory 7 of the line control unit 30 is changed from the 400,000 address to the 0 address after the program transfer, and the common memory 6 is changed to the 400,000 address. The area size and memory area start address are set by the CPU (for example, T
It is performed by controlling the memory address register of MP68301).

[0015]

As described above, since only one firmware program can be used, management becomes easy. Further, since it is not necessary to mount the boot ROM on each firmware CPU, the mounting space and cost can be reduced. In addition, because the program can be loaded with a simple boot device, the firmware memory can be
Moreover, the DRAM has a large capacity, and there is no need to back up the battery.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a multi-CPU using an embodiment of the present invention.

FIG. 2 is a diagram for explaining the operation of the multi-CPU showing one embodiment of the present invention.

FIG. 3 is a configuration diagram of a line measuring device using the present invention.

FIG. 4 is a diagram for explaining a procedure for starting a program of a line control unit of the line measuring device.

[Explanation of symbols]

1 ... Main CPU, 2 ... Firmware CPU, 6 ... Common memory, 7 ... Own memory, 8 ... Main memory, 10 ... Man-machine interface control unit, 20 ... Line management unit, 30 ... Line control unit, 31, Line control CPU , 32 ... Memory, 33
... signal processing unit, 34 ... line unit.

Claims (1)

[Claims] 1. A first step in which the main CPU 1 is in operation and the firmware CPU 2 is in a reset state when the apparatus power is turned on, and in this state, the main CPU 1 transfers the program of the firmware CPU 2 from the main memory 8 to the common memory 6. The second stage of expansion, the third stage after the second stage, in which the main CPU1 releases the reset of the firmware CPU2, and the firmware CPU2 makes the chip select CS0 active and the common memory 6 accessed when the reset is released. And a fourth step of starting the boot process, the firmware CPU2 sets the chip select of the own memory 7 to CS1, and copies all the contents of the common memory 6 to the own memory 7 in the firmware CPU2. After the copying is completed, the sixth step of setting the own memory 7 to the same address as the common memory 6 and the common memory 6 Stage 7 boot process farm CPU consisting of moving the address of Ppuserekuto CS0 to the area for which the own memory 7.