JPH09246981A - Digital modulation method and demodulation method and digital modulation circuit and demodulation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the system of m-n modulation so as not to largely change a DC level in m-n modulated and further NRZI modulated recording signals. SOLUTION: Input data are stored for one block in a FIFO memory 2. For respective input (m)-bit data, by processings in a CDS computing element 10 - a shift register 15, etc., DSV in the final bit of respective modulation block data after m-n modulation and NRZI modulation corresponding to the table numbers of 0-23 is computed for the respective table numbers. Then, by the processings in a DSC calculation device 16a and a |DSV| comparator 17a, etc., the m-n modulatron system for minimizing the absolute value of the DSV is specified and the number data are sent to a modulation system number generator 6 and an RLL modulator 3. The RLL modulator 3 m-n modulates the data of the FIFO memory 2 by the specified m-n modulation system. A switch 9 multiplexes synchronizing signals, the number of the m-n modulation system and the output of the RLL modulator 3 and sends them to an NRZI modulator 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention modulates an m-bit digital signal into an n-bit bit string to generate an NRZI signal.
(Non Return to Zero Inversion) Digital modulation method and circuit for modulation, and NR for n-bit modulation data
The present invention relates to a digital demodulation method and circuit for ZI demodulation to demodulate an original m-bit digital signal.

[0002]

2. Description of the Related Art As a method of storing and reproducing binary data at a high density on a recording medium, there is a method of RLL modulation and NRZI modulation. In this method, the number of 0s existing between 1 and 1 is limited to d or more and k or less, the signal of bit 1 is inverted, and 0 is not inverted. In this system, the following conditions are required.

(1) Large detection window width (Tw) A value proportional to m / n. This value is the time that can be used for detecting the reproduction bit, and shows the permissible capacity for the phase fluctuation of the reproduction pulse due to the waveform interference or noise accompanying the higher density. Therefore, the larger Tw is, the better. (2) The minimum polarity reversal interval (Tmin) is large. Tmin is obtained by the product of "d + 1" and Tw. When this value becomes small, the waveform interference between the reproduction pulses becomes large and the detection error at the time of demodulation increases. Therefore, the larger Tmin is, the better.

(3) The maximum polarity reversal interval (Tmax) is small Tmax is obtained by the product of "k + 1" and Tw. In order for the bit clock to follow the jitter of the reproduction signal, the polarity must be frequently inverted. Therefore, Tma
x should be small. (4) The constraint length Lc is small The length of the data before and after the reference when demodulating the modulated data is called the constraint length. The larger this value, the larger the error propagation and the more complicated the circuit. Therefore, the smaller Lc is, the better.

(5) Low amount of low frequency components As a measure for evaluating the amount of low frequency components, DSV (Digital Sum)
Variation) is used. This value is obtained by allocating "+1" to bit 1 of the recording signal and "-1" to bit 0 and calculating the sum from the beginning of the signal to a certain point. When recording / reproducing a signal on / from a recording medium, a direct current component and a low frequency component are cut off. That is, when the total sum has a large value of + or −, the recording signal waveform has a DC component in its frequency spectrum, but normally the recording signal or the reproduction signal is transmitted through the AC coupling element. Therefore, when the recording signal waveform has a DC component as described above, the recording signal waveform is distorted during transmission, which is not preferable. Moreover, even if the same waveform as the original recording signal waveform is reproduced at the time of reproduction, the DC component lost by the AC coupling element cannot be reproduced. For this reason, it is desirable that the recording signal waveform does not include a DC component.

As a method focusing on the above conditions (1) to (4), for example, Japanese Patent Publication No. 5-34747 discloses (d, k; m, n) = (2, 7; i). , 2i) R
LL code (i is a natural number) and JP-A-52-128024.
(D, k; m, n) = (1,7;
2i, 3i) There is an RLL code. Further, as a modulation method that also pays attention to the condition (5), there is an EFM modulation method disclosed in Japanese Patent Publication No. 1-27510. In this modulation method, 8-bit input data is “d = 2” “k = 10”
Is modulated into a 14-bit channel code subject to the constraint of “d = 2” and “k = 1” at the boundary value of each code.
Three bits are added to satisfy the constraint of "0" and to bring the DSV close to 0. Therefore, this modulation code corresponds to a (2,10; 8,17) RLL code.

[0007] Another method is Japanese Patent Publication No. 4-77991.
As shown in No. 6, there is a method of performing modulation from 8 bits to 14 bits so that the run length of bit 0 satisfies the constraint even at the boundary part of the modulation code. "CDS (Cord word
The 14-bit conversion code "Digital Sum) = 0" corresponds to the 8-bit input code in a one-to-one correspondence. Also, "CDS
The modulation code of "= 0" has a different CDS code,
In addition, one set of modulation codes having different CDS absolute values corresponds to the input code. As a result, the modulation code is selected so that the DSV approaches 0, and the low frequency component is suppressed. This modulation code is (1,7; 8,14) RL
It corresponds to the L code.

Further, in Japanese Unexamined Patent Publication No. 6-311042, in the (d, k; m, n) RLL code, modulation from m bits to "nd" bits is performed, and DSV is close to 0, Moreover, d bits are added so as to satisfy the constraint of (d, k). However, | CDS | (absolute value of CDS)
When is relatively small, the variation of DSV is small, so the modulation code from m bits to "nd" bits is in a one-to-one correspondence. It corresponds to the input code. As a code satisfying this modulation rule, (2,9; 8,17) RLL
Codes and (1,7; 8,13) RLL codes are listed.

[0009]

In any of the methods considering the above condition (5), the purpose is to bring the DSV close to 0. Therefore, additional bits are prepared and a plurality of modulation tables are prepared. Is used. Therefore, there is a problem that the restriction on the number of 0s between 1 and 1 must be relaxed and the number of bits after modulation must be increased.

Therefore, as compared with Japanese Patent Publication No. 5-34747 and Japanese Patent Laid-Open No. 52-128024, the detection window width Tw becomes smaller and the minimum polarity reversal interval Tmin.
Is small, and the maximum number k of 0s between 1 and 1 is large. In consideration of the above-mentioned conventional problems, the present invention is disclosed in Japanese Patent Publication No. 5-34.
While maintaining the parameters d, k, m, and n possessed by Japanese Patent Laid-Open No. 747 and Japanese Patent Laid-Open No. 52-128024, D
An object of the present invention is to provide a modulation method and a circuit that bring SV close to 0, and a demodulation method and a circuit.

[0011]

SUMMARY OF THE INVENTION The present invention is a digital modulation method for modulating m bits of input digital data into n bits of modulation data as a modulation unit, and a block of input digital data of a predetermined number of modulation units is provided. Each of the DC components of each modulation block data when modulated into a plurality of types of modulation data is detected, and the modulation block data having a small absolute value of the DC component is selected based on the detection result. The digital modulation method is characterized in that output data is generated by adding selective identification information. However, n> m, and the same applies hereinafter.

The present invention is a digital modulation method in which each m-bit of input digital data is m-n modulated into n-bit modulated data using each m-bit as a unit of code modulation. The DC components of the respective modulated block data obtained by m-n modulating a block of digital data composed of modulation units by a plurality of m-n modulation methods are compared with each other, and the absolute value of the DC component is An m-n modulation method corresponding to small modulation block data is selected, a block of the digital data is m-n modulated using the selected m-n modulation method to generate modulation block data, and the selected m is selected. -N is a digital modulation method in which modulation scheme number information indicating a modulation scheme is added to the modulation block data and output.

According to the present invention, a predetermined number of units of modulation block data having n bits as a demodulation unit and type identification information indicating the modulation system are input, and the modulation block data is demodulated according to the type identification information. The digital demodulation method is characterized in that

The present invention is a digital demodulation method in which each n bit of input digital data is used as a unit for code demodulation, and each n bit is demodulated into m-bit demodulated data by mn demodulation data. For each block data, an nm demodulation method corresponding to the modulation method number information indicating the modulation method of the block data, which is added to each block data as an nm demodulation method of block data configured in demodulation units, is used. , And block-modulates the corresponding block data by nm by using the selected nm demodulation method.
This is a digital demodulation method.

According to the present invention, in a digital modulation circuit for modulating m bits of input digital data as modulation units into n bits of modulation data, the input digital data is modulated to provide modulation type identification information and a type corresponding to the information. Modulation means for selecting and outputting specific output data from a plurality of types of output data, and a DC level for detecting the DC level of each type of the modulation data for each data of a predetermined modulation unit number. Detection means, and modulation control means for outputting output data including modulation data of a type having a small DC component based on the detection result by the DC level detection means from the modulation means for each data of the predetermined modulation unit number. These are digital modulation circuits that are arranged respectively.

According to the present invention, a predetermined number of codes are coded in a digital modulation circuit for m-n modulating each m-bit into n-bit modulated data with each m-bit of input digital data as a unit of code modulation. An arithmetic means for obtaining a DC component of each modulated block data obtained by m-n modulating a block of digital data composed of a unit of modulation by a plurality of m-n modulation systems, and an absolute value of each DC component. Comparing means for comparing the magnitudes of the values with each other; selecting means for selecting the mn modulation method corresponding to the modulation block data having a small absolute value of the direct current component based on the comparison result by the comparing means; and the selecting means. Selected by m-
Modulation means for m-n modulating the block of digital data using an n modulation method to generate modulation block data, and modulation method number information indicating the m-n modulation method selected by the selecting means. And a multiplex circuit added to the digital modulation circuit.

According to the present invention, a detecting means for detecting the type identification information from input data consisting of modulated data and type identification information of the modulated data, and demodulated data by demodulating the modulated data selected from a plurality of types of modulated data. And a demodulation control means for controlling the selection operation of the demodulation means based on the type identification information detected by the detection means.

According to the present invention, a predetermined number of codes are coded in a digital demodulation circuit that performs n-m demodulation of each n-bit into m-bit demodulated data using each n-bit of input digital data as a unit of code demodulation. Detection means for detecting the modulation scheme number information indicating the modulation scheme of the block data added to each block data as an nm demodulation scheme of block data composed of demodulation units, and detected by the detection means. N corresponding to the modulation method number information
-D demodulation means for selecting the -m demodulation method for each block data, and demodulation means for demodulating the corresponding block data by nm demodulation using the nm demodulation method selected by the selection means. Circuit.

According to the present invention, each m bit of input digital data is used as a unit of code modulation, and each m bit is m-n modulated into n-bit (n> m) modulated data (d, k; (m, n) In a digital modulation method for obtaining an RLL code, a block of digital data composed of a predetermined number of code modulation units is mn modulated by a plurality of mn modulation systems. A plurality of types of modulation block data are provided one-to-one with the plurality of types of m-n modulation schemes.
In the case where the modulation scheme number data obtained by one or more types so as to satisfy the d constraint from each of the modulation scheme number information corresponding to
The direct current components of the respective combined data are compared with each other, the mn modulation method corresponding to the combined data in which the absolute value of the direct current component is small is selected, and the digital data of the digital data is selected using the selected mn modulation method. This is a digital modulation method in which a block is m-n modulated to generate modulation block data, and the modulation scheme number data corresponding to the generated modulation block data is combined with the modulation block data and output.

According to the present invention, each m bit of input digital data is used as a unit of code modulation, and each m bit is m-n modulated into n bits (n> m) of modulated data (d, k; (m, n) In a digital modulation circuit for obtaining an RLL code, a block of digital data composed of a predetermined number of code modulation units is m-n modulated by a plurality of m-n modulation systems. A plurality of types of modulation block data are provided one-to-one with the plurality of types of mn modulation schemes
In the case where the modulation scheme number data obtained by one or more types so as to satisfy the d constraint from each of the modulation scheme number information corresponding to
Calculation means for respectively obtaining the DC component of each combined data, comparison means for mutually comparing the magnitudes of the absolute values of the respective DC components, and coupling for which the absolute value of the DC component is small based on the comparison result by the comparison means Selecting means for selecting an m-n modulation method corresponding to data; and modulating means for m-n modulating a block of digital data using the m-n modulation method selected by the selecting means to generate modulated block data. And a multiplexing circuit for adding the modulation method number data included in the combined data selected by the selecting means to the modulation block data.

The present invention is also directed to a method for selecting a modulation method that minimizes the absolute value of the cumulative value of the DC component at the final bit of the modulated data in any one or more of the above configurations. Circuit, method or circuit to select the modulation method that minimizes the absolute value of the maximum amplitude value of the DC component in the data after modulation,
A circuit or method for calculating the DC component based on the data stored in the ROM, and the modulation data based on the calculation of the DC component are N
A method or circuit that is RZI modulated data.

Further, the present invention is a method or circuit in which a plurality of modulation method number data can exist for one modulation method number information. In that case, the DC component of the combined data is reduced. A method and a circuit for selecting the mn modulation method.

Further, according to the present invention, each m bit of input digital data is used as a unit of code modulation, and each m bit is m-n modulated into n bits (n> m) of modulated data (d, k; m, n) In a digital modulation method for obtaining an RLL code, a block of digital data constituted by a predetermined number of code modulation units is mn modulated by a plurality of mn modulation systems. The direct current components of the obtained modulation block data are compared with each other, the mn modulation method corresponding to the modulation block data having a small absolute value of the direct current component is selected, and the mn modulation method is used to select the mn modulation method. A modulation method number corresponding to the selected mn modulation method from the modulation method number data group in which each block of digital data is mn-modulated to generate modulation block data and each data satisfies the d constraint. Selects and reads over data is read modulation scheme number data and the selected digital modulation method for outputting in addition to the modulated block data.

The modulation method number data group in which each data item satisfies the d constraint is generated so that the number data group number exceeding the total number of the mn modulation methods satisfies the d constraint, and an error is generated based on this. A correction code group is generated, and d is selected from the combination of the error correction code group and the number data group.
The digital modulation method is configured by extracting the same number of combinations satisfying the constraints as the total number of the mn modulation methods.

According to the present invention, each m bit of the input digital data is used as a unit of code modulation, and each m bit is m-n modulated into n bits (where n> m) of modulated data (d). , K; m, n) In a digital modulation circuit for obtaining an RLL code, a block of digital data composed of a predetermined number of code modulation units is used as a plurality of types of mn
Arithmetic means for obtaining the DC component of each modulated block data obtained by mn modulation by the modulation method, and comparison means for comparing the absolute values of the DC components with each other.
Based on the comparison result by the comparison means, mn corresponding to the modulation block data in which the absolute value of the DC component is small.
Selection means for selecting a modulation method, modulation means for mn-modulating the block of digital data using the mn modulation method selected by the selection means to generate modulation block data, and each data is d-constrained. Number generating means for selecting and reading the modulation method number data corresponding to the mn modulation method selected by the selecting means from the modulation method number data group satisfying the above, and the modulation method number data read by the number generating means. A digital modulation circuit having a multiplexing circuit added to the modulation block data.

Further, the number generating means generates a number data group of a number exceeding the total number of the m-n modulation schemes so as to satisfy the d constraint, and based on this, generates an error correction code group, and the number is generated. And a modulation method number data group table configured by extracting the same number of combinations satisfying the d constraint from the combination of the error correction code groups to the data groups as the total number of the mn modulation methods. It is a digital modulation circuit.

Further, according to the present invention, each m of digital data inputted by the mn modulation method in which an arbitrary n-bit (where n> m) arrangement is converted into an arbitrary m-bit arrangement in a one-to-one correspondence is converted. In a digital modulation method in which m bits are used as code modulation units, and m bits are each mn modulated into n bits of modulation data, at least one m
To describe an input block composed of a predetermined number of code modulation units using a plurality of types of m-bit description methods in which arbitrary information and arbitrary m-bit arrays are associated with each other so that the bit arrays are different. The input block data is converted into m-m, number data indicating the description system of the block is added to each block after the m-m conversion to form a number-added block, and each number-added block is calculated. An error correction code is added to each number addition block to form an error correction code addition block, and the DC components of each modulation block data obtained by m-n modulating each error correction code addition block are compared with each other. Then, the m-bit description method corresponding to the modulation block data in which the absolute value of the DC component is small is selected, and based on the selected m-bit description method, The error correction code addition block m-n
It is a digital modulation method of modulating and generating modulated block data.

Further, according to the present invention, each m of the input digital data is converted by an m-n modulation system in which an arbitrary n-bit (where n> m) arrangement is converted into an arbitrary m-bit arrangement in a one-to-one correspondence. In a digital modulation method in which m bits are code-modulated units and m bits are each m-n modulated into n bits of modulation data, at least one piece of the same information has different m bit arrays corresponding to different information. Any m
In order to describe an input block composed of a predetermined number of code modulation units by using a plurality of types of m-bit description methods that are associated with bit arrays, a bit string of the input block data is stored in the plurality of types. A plurality of types of block data are generated by converting into a bit string according to the m-bit description system, and number data indicating the description system of the block is added to each block data after the description system conversion to form a numbered block. Then, the error correction code calculated for each of the number-added blocks is added to each of the number-added blocks to form an error-correction code-added block, and each of the error-correction code-added blocks is m-n modulated. Before comparing the DC components of each modulation block data with each other and corresponding to the modulation block data in which the absolute value of the DC component is small Select m bits description method, the said error correction code addition block based on the selected m-bit description method m-n modulation to produce a modulated block data, a digital modulation method.

Further, it is a digital modulation method in which the above selection is performed based on specifying the modulation block data having the minimum absolute value of the cumulative value of the DC component at the final bit of the modulation block data. Further, it is a digital modulation method, wherein the selection is performed based on specifying the modulation block data having the smallest absolute value of the maximum amplitude of the modulation block data.

Further, according to the present invention, each m of digital data inputted by the mn modulation system for converting an arbitrary n-bit (where n> m) arrangement into an arbitrary m-bit arrangement in a one-to-one correspondence is converted. In a digital modulation circuit that performs m-n modulation of m bits into n bits of modulation data using bits as a code modulation unit, m for at least one same information
To describe an input block composed of a predetermined number of code modulation units using a plurality of types of m-bit description methods in which arbitrary information and arbitrary m-bit arrays are associated with each other so that the bit arrays are different. A data conversion circuit for converting input block data into m-m, a multiplex circuit for adding number data indicating a description method of the block to each block converted by the data conversion circuit to form a numbered block, and An error correction coding circuit that forms an error correction code added block by calculating and adding an error correction code to each number added block, and each obtained by m-n modulating each error correction code added block. Calculating means for respectively obtaining the DC component of the modulation block data, comparing means for mutually comparing the magnitudes of the absolute values of the DC components, and the comparing means. The selecting means for selecting the m-bit description method corresponding to the modulation block data in which the absolute value of the DC component is small based on the comparison result by the stage, and the error correction code addition block based on the selected m-bit description method are m -N modulation to generate modulated block data, and a digital modulation circuit.

Further, according to the present invention, each m of the input digital data is converted by the mn modulation method in which an arbitrary n-bit (where n> m) arrangement is converted into an arbitrary m-bit arrangement in a one-to-one correspondence. In a digital modulation circuit that m-n-modulates each m-bit into n-bit modulated data with m-bit as a code modulation unit, at least one piece of the same information has a different m-bit array, and any information Any m
In order to describe an input block composed of a predetermined number of code modulation units by using a plurality of types of m-bit description methods that are associated with bit arrays, a bit string of the input block data is stored in the plurality of types. A data conversion circuit that converts a bit string according to the m-bit description system to generate a plurality of types of block data, and number data indicating the description system of the block is added to each block data converted by the data conversion circuit. Multiplexing circuit as number addition block, error correction coding circuit each forming error correction code addition block by calculating and adding error correction code for each number addition block, and each error correction code addition block Calculating means for respectively obtaining the DC component of each modulation block data obtained by m-n modulating Comparing means for comparing the magnitude of minute magnitude to each other, based on the comparison result by the comparison means,
Selection means for selecting the m-bit description method corresponding to the modulation block data in which the absolute value of the DC component is small, and modulation block for performing mn modulation on the error correction code addition block based on the selected m-bit description method. A digital modulation circuit having: a modulation unit that generates data.

Further, the selecting means is a digital modulation circuit for selecting the mn modulation method corresponding to the modulation block data in which the absolute value of the cumulative value of the DC component at the final bit of the modulation block data is the minimum. . The selecting means is a digital modulation circuit that selects an mn modulation method corresponding to the modulation block data having the smallest absolute value of the maximum amplitude of the modulation block data.

Further, in the above configuration, further, there is provided a memory for storing each error correction code added block, and the modulation means corresponds to the m-bit description system selected from the memory by the selection means. It is a digital modulation circuit that reads out an error correction code added block and performs m-n modulation.

Further, in the above structure, further, a memory for storing the input block data, and an m-m conversion using the m-bit description method selected by the selecting means by reading the input block data from the memory. Second
And a second multiplexing circuit for adding number data indicating the description method selected by the selecting means to the block converted by the second data conversion circuit,
And a second error correction coding circuit for calculating and adding an error correction code to the block to which the number data has been added by the second multiplexing circuit and outputting the error correction code to the modulation means.

Further, according to the present invention, each n-bit of the input digital data is used as a code demodulation unit, and m-bit (where n> m) demodulation data is n-m demodulated to obtain a predetermined number of code demodulation units. The corresponding demodulation block data is sequentially generated, the demodulation block data is error-corrected using the error correction code added to the sequentially-generated demodulation block data, and the demodulation block data of the demodulation block data is corrected from the error-corrected demodulation block data. The number data indicating the description method is detected, and the demodulation block data is converted into another block data having a different m-bit array for at least one piece of the same information by using the m-m inverse conversion method specified by the number data. This is a digital demodulation method of performing m inverse conversion.

Further, according to the present invention, each n-bit of the input digital data is code-demodulated as a code-demodulation unit, and n-m demodulated into m-bit (where n> m) demodulation data, and a predetermined number of code-demodulation units. Sequentially generate demodulation block data corresponding to, the error correction code is added to the sequentially generated demodulation block data, the demodulation block data is error-corrected, and the demodulation block data after the error correction It is a digital demodulation method of detecting number data indicating a data description system and converting the demodulation block data into block data of a bit string according to the description system specified by the number data.

Further, according to the present invention, each n-bit of the input digital data is used as a code demodulation unit, and m-bit (where n> m) demodulation data is n-m demodulated to obtain a predetermined number of code demodulation units. A demodulation circuit that sequentially generates corresponding demodulation block data, an error correction circuit that error-corrects the demodulation block data by using an error correction code added to the demodulation block data that is sequentially generated by the demodulation circuit, and an error correction At least 1 of the demodulation block data is detected using a detection circuit for detecting number data indicating the description system of the demodulation block data from the subsequent demodulation block data and an MM inverse conversion system specified by the number data.
And a reverse conversion circuit for performing a reverse conversion of m-m into another block data having different m-bit arrays for the same information.

Further, according to the present invention, each n-bit of the input digital data is code-demodulated as a code demodulation unit, and n-m demodulated into m-bit (where n> m) demodulated data, and a predetermined number of code-demodulation units. A demodulation circuit that sequentially generates demodulation block data corresponding to the above, an error correction circuit that error-corrects the demodulation block data by using an error correction code added to the demodulation block data sequentially generated by the demodulation circuit, and an error. A detection circuit that detects number data indicating the description system of the demodulation block data from the corrected demodulation block data, and a description that converts the demodulation block data into block string data of a bit string according to the description system specified by the number data. A system conversion circuit, and a digital demodulation circuit.

[0039]

BEST MODE FOR CARRYING OUT THE INVENTION

1. DSV of information word First, an information word (original data to be recorded / reproduced; “information word” for distinguishing from modulation method number which is ancillary data
In the case of NR-modulating the above) and NRZI modulating this, an example of minimizing the absolute value of DSV will be described.

1-1. Principle of Modulation (FIG. 4) First, the principle of modulation of the present invention will be described with reference to FIG. In the present invention, m bits of input data are used as a modulation unit, and each m bits is m-n modulated (code conversion) into n bits to obtain a (d, k; m, n) RLL code, and then this is converted. , NRZI modulation. A plurality of types of modulation methods are prepared as the mn modulation method, and among them, an mn modulation method that minimizes the DC component after mn modulation and NRZI modulation is selected for each block. , Mn modulation is performed on each block by the selected modulation scheme, and data for identifying the selected mn modulation scheme (modulation scheme number data) is added to the mn modulation data of the block,
The data after the identification data is added is NRZI-modulated and output.

In FIG. 4, the input data supplied to the input terminal 28 is input to the serial / parallel converter 29 and output as m-bit parallel data. The m-bit data is converted into n-bit modulation data by the m-n modulator 30. The m-n modulator 30 is composed of j kinds of m-n modulators 30a, 30b, ... Which have different modulation systems, and simultaneously generates j kinds of m-n modulated data.

The generated j kinds of mn modulated data are
It is supplied to the DSV calculator 31 and the memory 37. The DSV calculator 31 has j kinds of DSV calculators 31a, 31b, ... Inside, and each DSV calculator 31a, 31b ,.
The absolute value | DSV | of the DSV of each NRZI modulated data when the mn modulated data output from the -n modulators 30a, 30b, ... Is NRZI modulated is calculated. This calculation is performed for a block (a unit composed of a predetermined number of m bits, which is a modulation unit).

The minimum | DSV | selector 32 is a DSV calculator.
By comparing the data output from 31a, 31b, ..., the output that minimizes the absolute value | DSV | of DSV is specified, and the mn modulation method corresponding to this is selected. This selected m-
The n modulation method number information (corresponding to the type selection identification information in the claims) is supplied to the selector 33 and the modulation method number adder 36.

After the operation of the minimum | DSV | selector 32 is completed, the selector 33 sequentially inputs each m-n modulation output read from the memory 37 and corresponds to the number selected by the minimum | DSV | selector 32. Select only the output that you want to output. The mn modulated data output from the selector 33 is sent to the parallel / serial converter 34, converted into serial data, and then supplied to the modulation method number adder 36.

The modulation system number adder 36 has a minimum | DSV |
The number information of the modulation method selected by the selector 32 is multiplexed on the serial data, and the output is input to the NRZI modulator 38. The NRZI modulator 38 NRZI-modulates the input multiplexed data and outputs the NRZI-modulated data to the output terminal 35.

Thus, in the present invention, a plurality of m-
Among the n modulation methods, D after mn modulation and NRZI modulation
An mn modulation method that minimizes the absolute value of SV is selected for each block, the block is mn modulated by the selected mn modulation method, and the selected mn modulation method is selected. The identification data shown is multiplexed and this multiplexed data is NRZI modulated.

In the present invention, the memory 37 is omitted, and instead of the memory 37, the m-n modulator 30 is used again.
It may be configured to output n-modulated data. Also,
Instead of providing j kinds of mn modulators 30a, 30b ,,, by replacing the input bit string with j kinds of bit strings and inputting these into a single mn modulator, mn modulation is performed. , J types of modulation can be performed. Further, by using the CDS and the polarity information about the n-bit modulation code, it is possible to calculate the DSV without using the m-n modulator. Instead of providing j m-n modulators, j kinds of m-n modulations may be realized by driving a single m-n modulator at high speed.

1-2. First Embodiment (Modulator Embodiment: FIG. 1) In the first embodiment, DSV after mn modulation and NRZI modulation is performed.
The mn modulation method that minimizes the absolute value at the end of the block is selected from 24 kinds of mn modulation methods as the mn modulation method for the block. In addition, each m-bit information word of the block is converted into an n-bit code word (mn modulation) by the selected m-n modulation method. This m-n modulated data is NRZI modulated and output. One block is composed of a predetermined number of information words, and each information word is composed of m bits. For example, one block is composed of 800 bits of input data.

The input data input from the input terminal 1 is
First, it is stored in 1 block memory 2. This one block memory 2 is composed of a FIFO (First In First Out) memory, and its capacity corresponds to one block of information words (the number of bits of input data existing between synchronous data). Each m-bit information word stored in the 1-block memory 2 is read in the order of storage, and RLL is performed every m bits.
The modulator 3 performs m-n modulation to obtain a (d, k; m, n) code. The type of mn modulation used here is |
DSV | Specified by the comparator 17a. The m-n modulation data converted from the m-bit information word to the n-bit code word by the RLL modulator 3 is NRZ-modulated by the NRZI modulator 4 together with the synchronization signal and the number data indicating the m-n modulation method.
The data is I-modulated and output from the output terminal 5 as recording data on the recording medium.

In the first embodiment, the m-n modulation system used in the RLL modulator 3 has 24 types of m-n so that the absolute value at the block end of DSV after NRZI modulation is minimized. From the modulation methods, each block is selected by the following processing.

First, the input data input from the input terminal 1 is stored in the one block memory 2 as described above, and is also sent to the CDS calculator 10 composed of a ROM.
The table number data “0 to 23” is input to the CDS calculator 10 from the table number generator 11 for every m bits of input data. That is, 24 table number data are sequentially input corresponding to the input of m bits of input data.

The CDS calculator 10 outputs the polarity data designated by the table number data and the m-bit input data to the exclusive OR circuit 13 in the order of the table numbers. Also,
The CDS calculator 10 outputs the CDS data designated by the table number data and the m-bit input data to the calculator 12 in the order of the table numbers.

The polarity data means m bits of the input data by m-n modulation method of each table of "0-23".
In the case of n modulation and further NRZI modulation, the final bit is data indicating whether it is a high level "1" or a low level "0", and each m bit and each table number. And is stored in advance in the CDS calculator 10 in association with. However, input m-bit mn
If the beginning of the n bits after modulation is “1”, the NR
ZI modulated data starts with "1" and has m bits of input m bits.
If the beginning of n bits after n modulation is “0”, the N
The RZI modulated data shall start with "0".

The CDS data is m of the input data.
When the bits are mn modulated by the mn modulation method of each table of "0 to 23" and further NRZI modulated, it is data indicating a direct current component of each modulation data,
Corresponding to each m bit and each table number, the CDS is set in advance.
It is stored in the calculator 10. However, when the beginning of n bits after m-n modulation of the input m bits is "1", the NRZI modulated data starts with "1" and the input m
When the head of n bits after mn modulation of the bit is "0", the NRZI modulated data is assumed to start with "0".

The polarity data output from the CDS calculator 10 is exclusive ORed with the polarity data which was input immediately before and processed by the same table number in the exclusive OR circuit 13. The result is input to the 24-stage polarity shift register 14. The polarity data input immediately before and processed by the same table number is supplied to the exclusive OR circuit 13 from the output side of the 24-stage polarity shift register 14 as shown in the figure.

The CD output from the CDS calculator 10
The S data is added to or subtracted from the CDS data that was input immediately before and processed by the same table number by the arithmetic unit 12, and the result is input to the 24-stage intra-block DSV shift register 15. The CDS data that was input immediately before and processed with the same table number is
As shown in the figure, it is supplied from the output side of the 24-stage DSV shift register 15 in the block to the arithmetic unit 12.

The selection of the addition or subtraction in the arithmetic unit 12 is made according to the polarity data which is input immediately before and processed by the same table number. That is, when the immediately preceding polarity data is low level "0", there is no need to invert the sign, so addition is selected. Further, when the immediately preceding polarity data is at the high level "1", the sign needs to be inverted, so that the subtraction is selected. Whether or not the sign inversion is necessary is determined by the polarity data and the CDS as described above.
“If the beginning of n bits after m-n modulation of the input m bits is“ 1 ”, the NRZI modulated data starts with“ 1 ”, and the n-bit data after m-n modulation of the input m bits is When the head is “0”, the NRZI modulated data is “0”
It begins with "."

By the above-described processing, the 24-stage polarity shift register 14 performs m-n modulation on the latest input m bits by the method of each table number, and further, the modulated data obtained by NRZI modulation. The polarity of the last bit is stored in the order of table numbers. Similarly, within a 24-stage block D
The SV shift register 15 performs m-n modulation on the latest input m bits by the method of each table number, and further, NR
DS at the last bit of the modulated data obtained by ZI modulation
V is stored in the order of table numbers.

Therefore, when the processing for one block is completed, the 24-stage polarity shift register 14 performs mn modulation on the block by the method of each table number, and further,
The polarities of the final bits of the modulated block data obtained by NRZI modulation are stored in the order of table numbers.
Similarly, in the 24-stage intra-block DSV shift register 15, the DSV at the final bit of the modulated block data obtained by mn modulation of the block by the method of each table number and further NRZI modulation is They are stored in the order of table numbers. The polarity data and the DSV data are sent to the DSV calculator 16a in the order of table numbers when the processing for one block is completed. After that, the 24-stage polarity shift register 14 and the 24-stage in-block DSV shift register 15 are both reset, and the process for the next block is similarly performed.

The DSV calculator 16a sends m-values from the register 18a according to the method selected in the immediately preceding block.
DSV data at the final bit of the modulation block data that has been n-modulated and further NRZI-modulated is input. Also,
The DSV calculator 16a receives the polarity data of the final bit of the modulation block data, which is mn-modulated by the method selected in the immediately preceding block and further NRZI-modulated, from the register 18b. The polarity data and the DSV data are transferred from the registers 18a and 18b to the DSV when the processing for one block in the shift registers 14 and 15 is completed.
Each value is input to the calculator 16a, held in the register of the DSV calculator 16a until the processing relating to the block is completed, and used for the following calculation.

The DSV calculator 16a uses the last bit of the current block (the block currently being processed) input from the shift register 15 in the table number order to the DSV data of the last bit of the immediately preceding block input from the register 18a. DSV data is added or subtracted, and the result is
Table number order: | DSV | Comparator 17a and register
Output to the input side switch terminal of 18a. That is, the DS at the last bit of the current block obtained by considering the history
V data in the order of table numbers | DSV | Comparator 17a
And output to the input side switch terminal of the register 18a.

The addition or subtraction is selected by the DSV calculator 16a according to the polarity data of the last bit of the immediately preceding block input from the register 18b. That is,
When the polarity of the last bit of the immediately preceding block is low level “0”, addition is selected because it is not necessary to invert the sign. When the polarity of the last bit of the immediately preceding block is high level “1”, the sign needs to be inverted, and therefore subtraction is selected. Whether or not the sign inversion is necessary is basically determined by referring to the polarity data and the CDS as described above, in the case where “the beginning of n bits after m-n modulation of input m bits is“ 1 ””. , The NRZI modulated data starts with "1",
The beginning of n bits after m-n modulation of input m bits is "0"
In this case, the NRZI modulated data is defined as "beginning with 0".

The | DSV | comparator 17a is used for the DSV calculator 16
DSV data at the last bit of the current block sent from a in the order of table numbers (DS with history considered)
V data) is compared with the previously stored DSV data relating to the conventional table number, and the one having the smaller absolute value is stored as the DSV data. That is, the DSV data
Update with a smaller absolute value.

As a result of the above comparison, the | DSV | comparator 17a determines that the absolute value of the DSV data input from the DSV calculator 16a is greater than the absolute value of the DSV data relating to the previous table number stored previously. If it is smaller, switch each switch on the input side of the registers 18a and 18b to the DSV calculator.
Set on each output side of 16a. This allows register 18a
Stores the DSV data having a smaller absolute value than before, and the register 18b stores the polarity.

Therefore, when the processing of the current block is completed, the register 18a is subjected to mn modulation and NRZI modulation in such a manner that the absolute value of the DSV data at the last bit of the modulation block data is minimized. The DSV data is stored. Also register
In 18b, the polarity data of the last bit of the modulation block data in the above case is stored.

When the process for the final table number is completed, the | DSV | comparator 17a makes the absolute value of the DSV data at the final bit of the modulation block data m-minimized.
The table number data indicating the n modulation method is converted into the RLL modulator.
3 and modulation method number generator 6 are output. After that, | DS
The V | comparator 17a is reset and the processing for the next block is similarly performed.

The RLL modulator 3 reads the data in the 1-block memory 2 in the order of storage, performs m-n modulation on m bits, and converts it into a (d, k; m, n) code. The mn modulation method used at this time is a method specified by the table number data sent from the | DSV | comparator 17a as described above.

The modulation method number generator 6 generates n-bit number data corresponding to the table number data input from the | DSV | comparator 17a as described above. The sync signal generator 8 also generates an n-bit sync signal. These n-bit data are transferred to the RLL modulator 3 by the switch 9.
Of the NRZI modulator 4 and the NRZI modulator 4
I is modulated, but D of this NRZI modulated data
The number data and the synchronizing signal are selected so that the absolute value of SV becomes small.

1-3. Second Embodiment (Modulator Embodiment: FIG. 2) In the second embodiment, in the block of the absolute value of the DSV of the modulation block data which is mn modulated and further NRZI modulated. The mn modulation method that minimizes the maximum value is selected from 24 kinds of mn modulation methods as the mn modulation method of the block. In addition, according to the selected m-n modulation method, each m-bit information word of the block is converted into an n-bit code word (mn modulation) as in the first embodiment. n modulation data is NRZI
Modulated and output. The structure of one block is the same as that of the first embodiment. Hereinafter, in the second embodiment, the same components as those of the first embodiment will be designated by the same reference numerals in the drawings, and the description thereof will be simplified.

The input data input from the input terminal 1 is
First, it is stored in 1 block memory 2. The input data stored in the 1-block memory 2 is read out in the order of storage and is m-n modulated by the RLL modulator 3 by m bits to be a (d, k; m, n) code. The mn modulation scheme used here is specified by the | DSV | comparator 17b. From the m-bit information word to n in the RLL modulator 3
The mn modulated data converted into the bit codeword is NR
The data is NRZI-modulated by the ZI modulator 4 and is output from the output terminal 5 as recording data on the recording medium.

In the above, in the mn modulation method used in the RLL modulator 3, the maximum value of the absolute value of the DSV of the mn modulated and NRZI modulated modulation block data in the block is the maximum value. The smallest m-n modulation method is
Each block is selected from the 24 types of m-n modulation methods by the following processing.

First, the input data input from the input terminal 1 is the C data composed of the ROM as in the first embodiment.
It is also sent to the DS calculator 10. In this CDS calculator 10,
The table number data “0 to 23” is input from the table number generator 11 for every m bits of input data.

The CDS calculator 10 outputs the polarity data designated by the table number data and the m-bit input data to the exclusive OR circuit 13 in the order of the table numbers. Also,
The CDS calculator 10 outputs the CDS data designated by the table number data and the m-bit input data to the calculator 12 in the order of the table numbers. The polarity data and the CDS data have the same meaning as in the first embodiment.

The polarity data output from the CDS calculator 10 to the exclusive OR circuit 13 is 2 as in the first embodiment.
It is input to the four-stage polarity shift register 14. Also CD
The CDS data output from the S calculator 10 is added to or subtracted from the CDS data input immediately before and processed by the same table number by the calculator 12 as in the first embodiment, and the result is obtained. Is input to the 24-stage intra-block DSV shift register 15. The selection of addition or subtraction is performed in the same manner as in the first embodiment.

By the above-described processing, the 24-stage polarity shift register 14 performs m-n modulation on the latest input m bits by the method of each table number, and further the modulated data obtained by NRZI modulation. The polarity of the last bit is stored in the order of table numbers. Similarly, within a 24-stage block D
The SV shift register 15 performs m-n modulation on the latest input m bits by the method of each table number, and further, NR
DS at the last bit of the modulated data obtained by ZI modulation
V is stored in the order of table numbers.

In the second embodiment, the polarity data of the last bit of the latest m-bit input modulation data stored in the shift register 14 by the above-described calculation and the shift register
DSV data of the last bit of the modulation data of the latest m-bit input stored in 15 and DSV data from the respective output sides of the shift registers 14 and 15 are sequentially displayed in the order of table numbers.
It is output to the calculator 16b.

The DSV calculator 16b sends m-values from the register 18a according to the method selected in the immediately preceding block.
DSV data at the final bit of the modulation block data that has been n-modulated and further NRZI-modulated is input. Also,
To the DSV calculator 16b, the polarity data of the final bit of the modulation block data that has been mn modulated by the method selected in the immediately preceding block and further NRZI modulated is input from the register 18b. The polarity data and the DSV data are transferred from the registers 18a, 18b to D when the processing for the first m bits in the shift registers 14, 15 is completed.
It is input to the SV calculator 16b, held in the register of the DSV calculator 16b until the processing for the current block is completed, and used for the following calculation.

The DSV calculator 16b inputs the DSV data at the last bit of the immediately preceding block input from the register 18a, to the DSV data (each table) sequentially input from the shift register 15 for each m-bit process in the order of table numbers. Mn modulation by the number m-n modulation system, and further NRZ
DSV data at the final bit of each I-modulated n-bit modulation data) is added or subtracted, and the result is shown in the order of table numbers | DSV | comparator 17c and delay memory 21a.
Output to That is, the DSV data obtained in consideration of the history are output to the | DSV | comparator 17c and the delay memory 21a in the order of table numbers. Further, the polarity data of the final bit after the addition or subtraction is output to the delay memory 21b. The selection of addition or subtraction by the DSV calculator 16b is
It is selected according to the polarity of the last bit of the modulated block data which is mn modulated and NRZI modulated by the method selected in the immediately preceding block. That is, when the polarity of the last bit of the immediately preceding block is low level “0”,
Addition is selected because there is no need to invert the sign. On the contrary, when the polarity of the last bit of the immediately preceding block is the high level “1”, the sign needs to be inverted, and thus the subtraction is selected. The principle of the necessity of this sign inversion is
This is similar to each case described above.

The | DSV | comparator 17c is used for the DSV calculator 16
The DSV data (DSV data in which the history is taken into account) at the last bit of the modulation data obtained from the latest input m bits sent from b in the order of the table number is the same table number obtained from the immediately preceding input m bits. DSV data at the last bit of the modulation data (considering history, and
DSV data with the largest absolute value in the block), the one with the larger absolute value is the DS of the table number.
The V data is output to the maximum | DSV | shift register 20a of 24 stages. That is, D related to the table number
The SV data is updated with a large absolute value and output to the maximum | DSV | shift register 20a of 24 stages. In addition,
The DSV data of the final bit of the modulation data for the same table number obtained from the immediately preceding input m bits is
The maximum | DSV | shift register 20a of 24 stages supplies the | DSV | comparator 17c from the output side.

With the above processing, the maximum | DSV of 24 rounds
The shift register 20a stores the DSV data having the maximum absolute DSV value in the current block in the order of table numbers.

Therefore, when the processing for one block is completed, the maximum absolute value of DSV in the current block is stored in the maximum | DSV | shift register 20a of 24 stages in the order of table numbers. . Each DSV data (maximum value data) has a | DSV | comparator in the order of table numbers when the processing of the current block is completed.
Sent to 17b. Then, the maximum | DSV | shift register 20a of 24 stages is reset, and the processing for the next block is similarly performed.

| DSV | Comparator 17b has a maximum of 24 stages |
DSV | The DSV data of the current block sent from the shift register 20a in the order of the table numbers (the DSV data having the largest absolute value regarding the table number in the current block in consideration of the history) is previously stored. Compared with the DSV data relating to the conventional table number, the one having the smaller absolute value is stored as the DSV data. That is, the DSV data is updated with a small absolute value.

As a result of the above comparison, the | DSV | comparator 17b determines that the absolute value of the DSV data relating to the current table number input from the maximum | DSV | shift register 20a of 24 stages is previously stored. If it is smaller than the absolute value of the DSV data for the table number of, the switches on the input side of registers 18a and 18b are
Set on each output side of 21a, 21b. This allows the register
The DSV data at the final bit of the modulation block data relating to the current table number is stored in 18a, and its polarity is stored in the register 18b.

Therefore, when the processing of the current block in the | DSV | comparator 17b is completed, the register 18
a is the final value of the modulation block data in the case where mn modulation is performed by the mn modulation method in which the maximum absolute value of the DSV data in the modulation block is minimized, and further NRZI modulation is performed. DSV data in bits is stored. Further, in the register 18b, in the above case,
The polarity data of the last bit of the modulation block data is stored.

When the processing for the final table number is completed, the | DSV | comparator 17b outputs the table number data indicating the m-n modulation method that minimizes the maximum absolute value of the DSV data in the modulation block. , RLL modulator 3 and modulation method number generator 6 are output. After that, | DSV |
The comparator 17b is reset, and the process for the next block is similarly performed.

The RLL modulator 3 reads the data in the 1-block memory 2 in the order of storage, performs m-n modulation on every m bits, and converts it into a (d, k; m, n) code. The mn modulation method used at that time is a method specified by the table number data sent from the | DSV | comparator 17b as described above.

The modulation method number generator 6 generates n-bit number data corresponding to the table number data input from the | DSV | comparator 17b as described above. The sync signal generator 8 also generates an n-bit sync signal. These n-bit data are transferred to the RLL modulator 3 by the switch 9.
Of the NRZI modulator 4 and the NRZI modulator 4
I is modulated, but D of this NRZI modulated data
The number data and the synchronizing signal are selected so that the absolute value of SV becomes small.

1-4. Third Embodiment (Embodiment of Demodulator: FIG. 3) Modulated by the modulator of the first or second embodiment,
The information recorded on the optical disc is reproduced by a device including the demodulation circuit of FIG.

That is, in this circuit, the reproduced data input to the input terminal 40 is demodulated by the NRZI demodulator 41, and the demodulated output is input to the modulation method number detector 42. This modulation system number detector 42 detects the modulation system number following the synchronization signal,
The detection output is supplied to the RLL demodulator 44. The RLL demodulator 44 performs demodulation by the nm demodulation method corresponding to the detected modulation method number and supplies the demodulation output to the output terminal 45.

2. Modulation number Next, r-bit (r is preferably a small value) modulation number data is generated from the modulation number, and each m-bit of input data is mn-modulated (converted) into n-bit. An example of multiplexing the obtained m-n modulated data and minimizing the absolute value of the DSV when the multiplexed data is NRZI-modulated will be described in the case of "d = 2, r = 15". To do. Note that d is the (d, k; m, n) RLL code d. The r-bit modulation number data is composed of an information section and an inspection section, and this r-bit modulation number data is (d, k; m, n) R as a whole (information section + inspection section).
An example in which the d constraint of the LL code is satisfied is d = 2, r
The case of = 15 will be described. In other words, an example will be described in which d constraint is satisfied when d is relatively large and r is relatively small.

2-1. Principle of Modulation (FIG. 11) First, the principle of modulation of the present invention will be described with reference to FIG. The portion for converting each m bit of the input data into each n bit is the same as in FIG. The parts common to FIG. 4 are the input terminal 28,
Serial / parallel converter 29, mn modulator 30, DSV
An arithmetic unit 31, a minimum | DSV | selector 32, a memory 37, a selector 33, a parallel / serial converter 34, a modulation method number adder 36, an NRZI modulator 38, and an output terminal 35.

In FIG. 11, j numbers corresponding to j m-n modulation schemes are converted into bit data, and error correction codes are added to the respective bit data to obtain r bits. The added r-bit bit data satisfies the d constraint as a whole, and this is multiplexed by the modulation method number error correction code adder 39 as the modulation method number data.

The d constraint is (d, k; m, n) R.
This is a restriction on the LL code, and in the modulation data code-converted to n-bit data, at least "d""0" s must be present between each "1" and "1". .

For example, FIG. 6 shows 24 numbers "0 to 23" for a (1, k; m, n) RLL code, that is, a case of "d = 1". 24 called "0-23"
Since the number of individual pieces is less than 32, it can be originally represented by 5-bit data, but 7 bits are required to satisfy the constraint of “d = 1”. Therefore, 7 bits are allocated to the information part (number part of "0 to 23").

Each of the above 7-bit data is added to (a) of FIG.
By multiplying the generator polynomial G shown in (1) (the generator polynomial in the case of d = 1), a 4-bit error correction code is obtained. However, these 4-bit error correction codes may not be able to satisfy the constraint of “d = 1” as they are. That is, it may be continuous with "11". Therefore, by assigning a 4-bit error correction code to the odd bits of the 8-bit check unit and substituting "0" for the even bits, the error correction is made to comply with the constraint of "d = 1". The code is used as the code to generate the modulation system number data.

Furthermore, if the bits before and after the "0" assigned to the even-numbered bits of the inspection section are both "0", even if "1" is assigned instead of "0", "d = 1""
Can be satisfied. Such bits are indicated by "*" in FIG. In such a case, "0" or "1" is selected so that the DC component is minimized.

FIG. 8 shows 24 modulation scheme numbers "0 to 23", which satisfies the constraint of (2, k; m, n) RLL code, that is, the constraint of "d = 2", and the modulation. An example in which the bit number r of the scheme number data is reduced will be shown. In FIG. 8, r
= 15, a slightly larger number of 11 bits are allocated to the information part, and information words satisfying the constraint of "d = 2" are selected from them. Furthermore, a 4-bit check unit obtained by multiplying the generator polynomial of FIG. 9B is added to each of the above information words,
Twenty-four combinations (combination of 11 bits of information part and 4 bits of check part) satisfying the constraint of “d = 2” are extracted and adopted as the modulation method number data. By selecting in this way, it is possible to obtain modulation method number data that satisfies “d = 2” and has a small r.

In the present invention, the mn modulation data of the input data is multiplexed on the synchronization signal and the modulation method number data, and when these are NRZI-modulated, the DSV thereof is reduced so that the above-mentioned 2 One of the types of modulation method number data is selected. Further, in the present invention, (d, k;
(m, n) RLL code d is increased (d = 2) and the number r of bits is suppressed to be small, and modulation method number data is provided. In the following, an embodiment in which one of two types of modulation method number data is selected (an example in which “d = 1”) and a modulation method number data in “d = 2” are given according to a specific circuit. An example will be described.

2-2. Fourth Embodiment (Modulator Embodiment: FIG. 5) The fourth embodiment (FIG. 5) is substantially the same as the first embodiment (FIG. 1). Therefore, the description of the same parts as those in FIG. 1 is omitted.
The common part with FIG. 1 is input terminal 1 and 1 block memory.
2, RLL modulator 3, NRZI modulator 4, output terminal 5,
CDS calculator 10, table number generator 11, exclusive OR circuit 13, calculator 12, 24-stage polarity shift register 14, 2
4-stage DSV shift register 15, DSV calculator 16a, |
DSV | comparator 17a, register 18a, register 18b, modulation method number generator 6, and sync signal generator 8. The part not shown in FIG. 1 is a modulation system number error correction code generator 27. Also, the part that is slightly different from FIG. 1 is the switch 9
It is.

As described above, when the | DSV | comparator 17a completes the comparison process of the DSV data indicated by the final table number of the current block, the | DSV | comparator 17a determines the final bit of the modulation block data. DSV at
The table number data indicating the m-n modulation method that minimizes the absolute value of the data is output to the RLL modulator 3 and the modulation method number generator 6.

Correspondingly, the modulation system number generator 6
Generates 7-bit number data (FIG. 6; "d = 1") corresponding to the table number data. This 7
The bit number data is output to the terminal of the switch 9 and is also sent to the modulation method number error correction code generator 27.

The modulation method number error correction code generator 27 uses the 7-bit number data input from the modulation method number generator 6 to generate the generator polynomial G ((a) of FIG. 9) (in the case of "d = 1").
And the 4-bit data obtained by this is multiplied by "d
An 8-bit error correction code is generated by arranging four "0" s so as to satisfy the constraint "= 1".

When there are two types of error correction codes (see "*" in FIG. 6), the modulation method number error correction code generator 27 outputs m-n according to the selected method output from the RLL modulator 3. When the modulated data is multiplexed and NRZI-modulated, the error correction code having the smaller DSV is selected and output to the terminal of the switch 9.

The switch 9 generates a synchronizing signal generated by the synchronizing signal generator 8, 7-bit modulation method number data generated by the modulation method number generator 6, and a modulation method number error correction code generator 27. 8-bit error correction code,
Also, the m-n modulation data for one block output from the RLL modulation circuit 3 is multiplexed and output to the NRZI modulator 4. Thus, the multiplexed data is NRZI modulated.

Although the case of "d = 1" has been described above, in the case of "d = 2" (FIG. 8), since there is only one type of error correction code as described above, modulation is performed. The system number error correction code generator 27 outputs the error correction code to the terminal of the switch 9 without comparing the magnitude of the absolute value of DSV.

2-3. Fifth Embodiment (Modulator Embodiment: FIG. 7) The fifth embodiment (FIG. 7) is substantially the same as the second embodiment (FIG. 2). Therefore, the description of the same parts as those in FIG. 2 is omitted.
The common part with FIG. 2 is input terminal 1 and 1 block memory.
2, RLL modulator 3, NRZI modulator 4, output terminal 5,
CDS calculator 10, table number generator 11, exclusive OR circuit 13, calculator 12, 24-stage polarity shift register 14, 2
4-stage DSV shift register 15, | DSV | Comparator 17c
, A maximum of 24 stages | DSV | shift register 20a, register 18a, register 18b, | DSV | comparator 17b, delay memory 21a, delay memory 21b, modulation method number generator 6,
This is the synchronization signal generator 8. 2 are the modulation system number error correction code generator 27, | DSV | comparator 17d, 2
4-stage maximum | DSV | shift register 20b, | DSV |
A comparator 17e, a delay memory 21c, a delay memory 21d, and a selector 22. 2 are a DSV calculator 16c (DSV calculator 16b in FIG. 2) and a switch 9.

In the example of FIG. 2 described above, the DSV calculator 16b,
| DSV | Comparator 17c and 24 stages of maximum | DSV |
The shift register 20a calculates, for each m-n modulation data of the current m bits in the current block, DSV in consideration of the history after NRZI modulation for each table number, and these are calculated in the | DSV | comparator 17b in order. As a result of comparison, the m-n modulation method that minimizes the maximum absolute value of the DSV in the current block is selected.

In this example, this selection is made in two ways in consideration of the two types of history resulting from the two types of modulation method number data (see "*" in FIG. 6). That is, the modulation method number data is added at the beginning of the m-n modulation block data output from the RLL modulator 3 by the switch 9, but there are two kinds of modulation method number data as shown in FIG. In that case, the above-mentioned DSV differs depending on which modulation method number data is added, and as a result,
The m-n modulation method that minimizes the maximum absolute value of the DSV in the current block also differs.

Therefore, in this example, the DSV calculator of FIG.
A DSV calculator 16c is provided in place of 16b, and two systems are processed from this DSV calculator 16c.
| Comparing with the comparator 17e, considering the two types of histories resulting from the two types of modulation method number data, the maximum absolute value of the DSV in the current block is the minimum value mn
The DSV of the bit stream output from the NRZI modulator 4 is minimized by specifying the modulation method and also specifying one of the two kinds of modulation method number data.

Incidentally, in the above, the processing of the two systems is
The system of "| DSV | comparator 17c, maximum of 24 stages | DSV | shift register 20a, delay memory 21a, delay memory 21b" and "| DSV | comparator 17d, maximum of 24 stages | DS
V | Shift register 20b, delay memory 21c, delay memory
21d ”system. The selector 22 is switched depending on which system is being processed.

The processing results of both systems are "| DSV |
As a result of comparison by the comparator 17e, as described above, the m-n modulation method that minimizes the maximum absolute value of the DSV in the current block is specified, and the modulation method number data for realizing this is specified. After being specified, these are output to the modulation method number generator (modulation mode signal generator) 6 and the modulation method number error correction code generator 27, and are subjected to the above-described processing.

That is, the switch 9 is the synchronization signal generator 8
Signal generated from the modulation method number generator, 7-bit modulation method number data generated from the modulation method number generator 6, 8-bit error correction code generated from the modulation method number error correction code generator 27, and RLL modulation circuit. NRZI modulator that multiplexes one block of m-n modulation data output from
Output to 4. Thus, the multiplexed data is NRZI modulated.

In the above, the case of "d = 1" has been described, but in the case of "d = 2" (FIG. 8), since there is only one type of error correction code as described above, Of the two processings, one is unnecessary.

2-4. Sixth Embodiment (Embodiment of Demodulator: FIG. 1)
0) modulated by the modulator of the fourth or fifth embodiment described above,
The information recorded on the optical disc is reproduced by a device including the demodulation circuit of FIG.

Since the circuit of FIG. 10 is substantially the same as the circuit of FIG. 3 described above, the same elements as those of the circuit of FIG. 3 are designated by the same reference numerals and the description thereof will be omitted. The circuit of FIG. 10 is different from the circuit of FIG. 3 in that an error correction decoder 43 for modulation method number is provided.

The modulation system number error correction decoder 43 uses the parity check matrix H in the lower 8 bits of the modulation system number data.
By multiplying ((a) of FIG. 9) and comparing the result with the inspection unit (FIG. 6), the presence or absence of an error is inspected and the modulation scheme number data is specified. 9A and FIG. 6 show the case of “d = 1”, “d = 2”
In this case, (b) of FIG. 9 and FIG. 8 are used.

3. In the case where the modulation method number is included in the information word In the above-described first to sixth embodiments, the information word, that is, the original data to be recorded / reproduced is m-n modulated by the selected method and is selected. The data obtained by encoding the modulation method number indicating the m-n modulation method so as to satisfy the d constraint is added, but in place of this, the modulation method number is included in the information word for mn modulation. You can also Hereinafter, such a method will be described with reference to each of the seventh to ninth embodiments.

3-1. Data Format FIG. 12 shows the data format (upper row) in the above-mentioned first to sixth embodiments and the data format (lower row) in the following seventh to ninth embodiments.

As shown in the upper part of the drawing, in the first to sixth embodiments, the data of one block, which is the unit for selecting the mn modulation system, is the synchronization signal SYNC, and the modulation system indicating the mn modulation system of the block. Number part (modulation mode signal part in the figure),
And a data section having information of original recording / reproduction target. The error correction code is added to each of the modulation method number part and the data part as a "check part" and an "data error code".

On the other hand, in the seventh to ninth embodiments, as shown in the lower part of the figure, one block of data consists of the synchronization signal SYNC and the data part, and the data part is the original recording / reproducing target in the block. The number data indicating the description method of the information is included. Further, the error correction code is collectively calculated and added to the data group consisting of the number data indicating the description method and the information to be originally recorded / reproduced.

In the above description, the description method is a method of associating arbitrary information with an arbitrary m-bit array, and by making the m-bit array corresponding to at least one piece of the same information different between the description methods. , Multiple description methods are available. For example, with respect to the information "A", "0000" is assigned in the first description method, "1000" different from the first method is assigned in the second description method, and the second is used in the third description method. The same "1000" as in the above method is assigned. Further, to the information "B", "0001" is assigned in the first description method, "0001" is assigned in the second description method, which is the same as the first method, and the second description method is used in the second description method. "0010" different from the method is assigned. In this way, the m-bit array corresponding to at least one piece of the same information is assigned differently depending on the description method.

3-2. Seventh Embodiment (Modulator Embodiment: FIG. 1)
3) The input data is first converted into j types of data having different description methods. For example, using m bits, which is a unit of code modulation in mn modulation, as a unit of data conversion, j kinds of data converters 51a are used for j kinds of data having different description systems and the unit of code modulation is The data is converted into m-bit data (m-m conversion). The m-m conversion refers to data conversion of m-bit data of a certain description method into corresponding m-bit data of another description method. The j-type data converter 51a only needs to have a function of converting input data into j-type data having different description systems. For example, the conversion unit does not necessarily have to be m bits. That is, the converted data may be described using m bits as the unit of code modulation, as in the case before conversion.

The data of each description method for one block, which has been m-m converted, is then converted into the j-type data conversion number multiplexer 52a.
Thus, the data conversion number data indicating the description method of the block is multiplexed. Here, one block means a data amount composed of a certain predetermined number of m bits, and | DSV
| It becomes the unit of comparison.

A block (numbered block) of each description system in which number data indicating the description system is multiplexed is next subjected to operation of the error correction code of the numbered block by the j type error correction encoder 53a. It is added to form the error correction code addition block described in the claims. As described above, in this embodiment, since the error correction is performed on the entire data composed of the number data and the original information to be recorded / reproduced, the product code or the like can be applied and the error correction capability is enhanced. . Each data of the error correction code addition block of each description method is stored in the 1-block memory 54a and is input to the j type | DSV | calculator / comparator 55.

Next, the error correction code addition block of each description system is
DSV | are compared with each other and the error correction code added block having the smallest absolute value is selected. Here, the absolute value to be compared is, for example, the value in the final bit of the error correction code added block. Alternatively, the error correction code addition block in which the absolute value of the maximum amplitude in the error correction code addition block is the smallest may be selected. This point has been described in detail in the above-described first embodiment and the like, and thus the description thereof will be omitted. The configuration of the j type | DSV | arithmetic / comparator 55 has also been described in detail in the above-described first embodiment and the like, and thus the description thereof will be omitted.

When the error correction code addition block with the minimum | DSV | is selected, the information is sent to the selector 56, and the selector 56 causes the error correction code addition block with the minimum | DSV | to be the RLL modulator 57. Is input to. As a result, the RLL modulator 57 performs m-n modulation, and then the NRZI modulator 58 performs NRZI modulation. R
The configurations and functions of the LL modulator 57 and the NRZI modulator 58 have been described in detail in the above-described first embodiment and the like, and therefore the description thereof is omitted here.

3-3. Eighth Embodiment (Embodiment of modulator: FIG. 1)
4) The eighth embodiment is a circuit configured to reduce the number of block memories. That is, in the above-described seventh embodiment, since the error correction code added blocks of each description method are stored in the 1-block memory 54a, the block memory 54a as a whole needs a capacity of j blocks. . In view of this, in the eighth embodiment, the required capacity of the one block memory 54b is set to one block by storing the input data in the one block memory 54b. In the following description, the description of the same parts as those in the seventh embodiment will be simplified.

First, the j type data converter 51a, the j type data conversion number multiplexer 52a, and the j type error correction encoder 53a calculate error correction code added blocks based on each description method, and j type | DSV | operation
The comparator 55 compares them with each other to select the error correction code added block having the smallest | DSV |. The result of this selection is sent to the data converter 51b.

When the selection result is input, the data converter 51b reads the data read from the one-block memory 54b so that the data of the description system based on the error correction code addition block having the smallest | DSV | Is converted to m-m. Number data indicating the description system is multiplexed by the data conversion number multiplexer 52b on the m-m converted data, and an error correction code is calculated and added by the error correction encoder 53b. , RLL modulator 57 m-
The signal is n-modulated and further NRZI-modulated by the NRZI modulator 58 and output.

3-4. Ninth Embodiment (Embodiment of demodulator: FIG. 1)
5) FIG. 15 is a circuit for demodulating data configured as shown in the lower part of FIG. 12 by the modulator of FIG. 13 or 14.

The data input to this demodulator is first N
The RZI demodulator 61 performs NRZI demodulation, and then the RLL demodulator 62 performs nm demodulation. An error correction decoder 63 performs error correction on the nm demodulated data. Next, from the data after error correction, the data conversion number detector 64 detects the number data indicating the description method,
This number data is sent to the data inverse converter 65.

The data reverse converter 65 reverses the data input from the error correction decoder 63 by m-m based on the number data input from the data conversion number detector 64. As a result, the data is returned to the data of the original description method (data when input to the modulation circuit of FIG. 13 or 14).

[0133]

As described above, according to the present invention, since the mn modulation method is selected for each block of data, a modulated output with a small DC level fluctuation can be efficiently generated. Further, in the present invention, when the DC level is detected and stored at the final timing of the block,
The circuit can be simplified by using the DC level for evaluation. Further, in the present invention, when the DC level at each timing in the block is evaluated, the absolute value of the DC level can be minimized.

Further, in the present invention, when there are a plurality of modulation method number data of the modulation method number information indicating the selected modulation method, the DC component in the case where the modulation block data is combined with the data is evaluated. Then, the optimum recording signal can be obtained as a whole by selecting the m-n modulation method. Further, by selecting the modulation method number information as in the present invention, it is possible to obtain a modulated output with a small DC level fluctuation.

Further, in the present invention, | DSV | is reduced by selecting the m-m data conversion equivalent to the selection of the m-n modulation method for each data of one block for each data of one block. Therefore, a modulated output with a small DC level fluctuation can be efficiently achieved.

Further, according to the present invention, the demodulation can be performed only by detecting the modulation system for each block on the demodulation side and switching the demodulation system, and the demodulation can be performed by a simple circuit.

[Brief description of drawings]

FIG. 1 is a block diagram of a digital modulation circuit that is a first embodiment of the present invention.

FIG. 2 is a block diagram of a digital modulation circuit that is a second embodiment of the present invention.

FIG. 3 is a block diagram of a digital demodulation circuit that is a third embodiment of the present invention.

FIG. 4 is a block diagram showing a first modulation principle of the present invention.

FIG. 5 is a block diagram of a digital modulation circuit that is a fourth embodiment of the present invention.

FIG. 6 is a data configuration diagram showing a sequence of modulation scheme number data used in the fourth and fifth embodiments of the present invention for d = 1.

FIG. 7 is a block diagram of a digital modulation circuit that is a fifth embodiment of the present invention.

FIG. 8 is a data configuration diagram showing an arrangement of modulation scheme number data used in the fourth and fifth embodiments of the present invention for d = 2.

FIG. 9 shows a generator polynomial G of an error correction code and a parity check matrix H used in the fourth, fifth and sixth embodiments of the present invention.
(A) shows the case of d = 1, and (b) shows the case of d = 2.

FIG. 10 is a block diagram of a digital demodulation circuit that is a sixth embodiment of the present invention.

FIG. 11 is a block diagram showing a second modulation principle of the present invention.

FIG. 12 is an explanatory view showing a data format of the present invention, the upper part shows the data format in the first to sixth embodiments, and the lower part shows the data format in the seventh to ninth embodiments.

FIG. 13 is a block diagram of a digital modulation circuit that is a seventh embodiment of the present invention.

FIG. 14 is a block diagram of a digital modulation circuit that is an eighth embodiment of the present invention.

FIG. 15 is a block diagram of a digital demodulation circuit that is a ninth embodiment of the present invention.

Claims (54)

[Claims] 1. A digital modulation method for modulating n (where n> m) bits of input digital data as a modulation unit into n (where n> m) bits of modulation data, wherein a block of input digital data of a predetermined number of modulation units is Detecting the DC component of each modulation block data when modulated into a plurality of types of modulation data, respectively, based on the detection result, select the modulation block data with a small absolute value of the DC component, to the selected modulation block data A digital modulation method characterized in that output data is generated by adding type selection identification information. 2. A digital modulation method in which each m-bit of input digital data is used as a unit of code modulation and each m-bit is m-n modulated into n-bit (n> m) modulated data. Comparing the DC components of the respective modulated block data obtained by mn-modulating a block of digital data constituted by a predetermined number of code modulation units by a plurality of mn modulation schemes, An mn modulation method corresponding to the modulation block data having a small absolute value of the DC component is selected, and the block of the digital data is mn modulated using the selected mn modulation method to generate modulation block data. Then, the modulation method number information indicating the selected mn modulation method is added to the modulation block data and output. 3. The selection method according to claim 1, wherein the selection is based on specifying the modulation block data having the minimum absolute value of the cumulative value of the DC component at the final bit of the modulation block data. Digital modulation method. 4. The digital modulation method according to claim 1 or 2, wherein the selection is based on specifying a modulation block data having a minimum absolute value of the maximum amplitude of the modulation block data. 5. The digital modulation method according to claim 1, wherein the DC component is obtained by arithmetically processing the modulation block data, and the selection is performed by reading the modulation block data from a storage unit. 6. The DC component according to claim 1, wherein the DC component is obtained by calculation in a process of generating the modulation block data, and the modulation block data to which the type identification information is added is a modulation block based on the selection. A digital modulation method obtained by regenerating data. 7. The digital modulation method according to claim 2, wherein the DC component is obtained based on m-bit input data and data uniquely designated by an m-n modulation method. 8. The digital modulation method according to claim 1 or 2, wherein the modulation block data is NRZI modulation data obtained by further NRZI modulating the data after mn modulation. 9. A predetermined number of units of modulation block data having n bits as a demodulation unit and type identification information indicating the modulation method are input, and the modulation block data is demodulated according to the type identification information. A digital demodulation method characterized by the above. 10. A digital demodulation method in which each n-bit of input digital data is used as a unit of code demodulation and each n-bit is demodulated into m-bit (n> m) demodulated data by n-m demodulation. As an nm demodulation method for block data configured by a predetermined number of code demodulation units, nm demodulation corresponding to modulation method number information indicating the modulation method of the block data added to each block data. A digital demodulation method, in which a method is selected for each block data, and the corresponding block data is demodulated by nm by using the selected nm demodulation method. 11. A digital modulation circuit that modulates input digital data into m (where n> m) bits of modulation data using m bits as a modulation unit, and modulates the input digital data to obtain modulation type identification information. Modulating means for selecting and outputting specific output data from a plurality of types of output data consisting of modulation data of a type corresponding to the information, and a direct current of the modulation data of each type for each data of a predetermined modulation unit number. Based on the detection result by the direct current level detection means for detecting the level, respectively, the direct current level detection means, the output data including the modulation data of a small direct current component,
A digital modulation circuit comprising: a modulation control unit that outputs the data from the modulation unit for each of the predetermined number of modulation units. 12. The modulation device according to claim 11, wherein the modulation means selects and outputs the modulation data having the minimum absolute value of the cumulative value of the DC component in the final bit of the data for the predetermined modulation unit number. , Digital modulation circuit. 13. The digital modulation circuit according to claim 11, wherein the modulation means selects and outputs the modulation data having the minimum maximum absolute value of the DC component in the data for the predetermined modulation unit number. . 14. The DC level detecting means according to claim 11, wherein each type of modulation data stored in the storing means is arithmetically processed to obtain each DC level, and the modulating means selects the selected data. A digital modulation circuit for reading the type of modulation data to be included in output data from the storage means. 15. The DC level detection means according to claim 11, wherein each DC level is calculated in the process of generating each type of modulation data, and the modulation means outputs the selected output data. A digital modulation circuit that regenerates the kind of modulation data that should be included. 16. The digital modulation circuit according to claim 11, wherein the output data is NRZI modulation data. 17. A digital modulation circuit, wherein each m bit of input digital data is used as a unit of code modulation, and each m bit is m-n modulated into n bits (n> m) of modulation data. Arithmetic means for respectively obtaining a DC component of each modulated block data obtained by m-n modulating a block of digital data constituted by a predetermined number of units of code modulation by a plurality of m-n modulation systems; Comparing means for mutually comparing the magnitudes of the absolute values of the DC components, and m-n corresponding to the modulation block data having a small absolute value of the DC component based on the comparison result by the comparing means.
Selecting means for selecting a modulation method; modulating means for mn modulating the block of digital data to generate modulated block data using the mn modulation method selected by the selecting means; and selecting by the selecting means A digital modulation circuit comprising: a multiplexing circuit for adding modulation system number information indicating the m-n modulation system to the modulation block data. 18. The stored R of the original DC component data uniquely specified by the m-bit input data and the m-n modulation method according to claim 17.
A digital modulation circuit having an OM, wherein the calculating means obtains the DC component based on the original DC component data read from the ROM. 19. The selecting means according to claim 17, wherein the selecting means selects an m-n modulation method corresponding to the modulation block data having the minimum absolute value of the cumulative value of the DC component at the final bit of the modulation block data. A digital modulation circuit. 20. The digital modulation circuit according to claim 17, wherein the selection unit selects an m-n modulation method corresponding to modulation block data having a minimum absolute value of the maximum amplitude of the modulation block data. 21. The digital modulation circuit according to claim 17, wherein the modulation block data is NRZI modulation data obtained by further NRZI modulating the m-n-modulated data. 22. Detection means for detecting the type identification information from input data composed of modulated data and type identification information of the modulated data, and demodulated demodulated data by demodulating the modulated data selected from a plurality of types of modulated data. Based on the demodulation means to output, and the type identification information detected by the detection means,
A demodulation control means for controlling a selection operation of the demodulation means; 23. A digital demodulation circuit for performing n-m demodulation of each n-bit into m-bit (where n> m) demodulation data by using each n-bit of input digital data as a unit of code demodulation. As an nm demodulation method for block data configured by a predetermined number of code demodulation units, detection means for detecting modulation method number information indicating the modulation method of the block data added to each block data, The selecting means for selecting the nm demodulation method corresponding to the modulation method number information detected by the detecting means for each block data, and the mn demodulation method selected by the selecting means are used respectively. A digital demodulation circuit having demodulation means for demodulating block data by nm. 24. Each m bit of input digital data is used as a unit of code modulation, and each m bit is m-n modulated into n bits (where n> m) of modulated data (d, k; m). , N) In a digital modulation method for obtaining an RLL code, a block of digital data constituted by a predetermined number of units of code modulation is respectively converted into m blocks by a plurality of mn modulation systems.
A plurality of types of modulation block data obtained by the -n modulation is set so that the d constraint is satisfied from each of the modulation scheme number information corresponding to the plurality of types of mn modulation schemes in a one-to-one manner.
Modulation method number data obtained by more than one type are compared with each other when the modulation methods are associated with each other and the direct current components of the respective combined data are compared with each other, and the absolute value of the direct current component corresponds to the combined data having a small absolute value. A mn modulation method to be performed, mn modulation is performed on the block of the digital data using the selected mn modulation method to generate modulation block data, and modulation corresponding to the generated modulation block data is performed. A digital modulation method in which method number data is combined with the modulation block data and output. 25. The digital modulation method according to claim 24, wherein the selection is performed by identifying combined data having a minimum absolute value of a cumulative value of a DC component at a final bit of the combined data. 26. The digital modulation method according to claim 24, wherein the selection is performed by identifying a modulation block data having a minimum absolute value of the maximum amplitude of the modulation block data in the combined data. 27. The DC component of the combined data according to claim 24, based on data in which the DC component of the modulation block data is uniquely designated by m-bit input data and an mn modulation method. A digital modulation method that is obtained by obtaining. 28. The combined data according to claim 24, wherein the modulation method number data is added to data obtained by m-n modulating the block of digital data, and the data after the addition is further added. A digital modulation method, which is NRZI modulated data obtained by NRZI modulation. 29. The modulation scheme number data obtained from the modulation scheme number information corresponding to the m-n modulation scheme is present in two types for one m-n modulation scheme. Digital modulation method. 30. Each m bit of input digital data is used as a unit of code modulation, and each m bit is m-n modulated into n bits (n> m) of modulated data (d, k; m). , N) In a digital modulation circuit for obtaining an RLL code, a block of digital data composed of a predetermined number of code modulation units is respectively converted into m blocks by a plurality of mn modulation systems.
A plurality of types of modulation block data obtained by the -n modulation is set so that the d constraint is satisfied from each of the modulation scheme number information corresponding to the plurality of types of mn modulation schemes in a one-to-one manner.
When the modulation method number data obtained for each type or more is associated with each modulation method and combined, the calculation means for determining the DC component of each combined data and the absolute value of each DC component are mutually compared. Comparing means for comparing, selecting means for selecting an mn modulation method corresponding to combined data having a small absolute value of the direct current component based on a comparison result by the comparing means, and m-n selected by the selecting means Modulation means for m-n modulating the block of digital data using a modulation method to generate modulation block data, and modulation method number data included in the combined data selected by the selection means is added to the modulation block data. A digital modulation circuit having a multiplexing circuit. 31. The R for storing the original DC component data uniquely specified by the m-bit input data and the m-n modulation method according to claim 30.
OM, and the arithmetic means reads the data uniquely specified by the m-bit input data and the mn modulation method from the ROM to obtain the DC component of the modulation block data, thereby obtaining the combined data. Digital modulation circuit that calculates the DC component of. 32. The selection means according to claim 30, wherein the absolute value of the absolute value of the cumulative value of the DC component at the final bit of the combined data corresponds to the combined data.
A digital modulation circuit that selects the n modulation method. 33. The selecting means according to claim 30, wherein the selecting means selects an m-n modulation method corresponding to modulation block data having a minimum absolute value of the maximum amplitude of the modulation block data in the combined data. Digital modulation circuit. 34. The combined data according to claim 30, wherein data obtained from the modulation method number information is added to data obtained by m-n modulating the block of digital data, and the addition is performed. A digital modulation circuit which is NRZI modulated data obtained by further NRZI modulating the subsequent data. 35. The modulation scheme number data obtained from the modulation scheme number information corresponding to the m-n modulation scheme is present in two types for one m-n modulation scheme. Digital modulation circuit. 36. Using each m bit of input digital data as a unit of code modulation, each m bit is m-n modulated into n bit (n> m) modulated data (d, k; m). , N) In a digital modulation method for obtaining an RLL code, a block of digital data composed of a predetermined number of code modulation units is obtained by m-n modulating each of a plurality of types of m-n modulation methods. The direct current components of the respective modulation block data are compared with each other, the mn modulation method corresponding to the modulation block data in which the absolute value of the direct current component is small is selected, and the digital data is obtained using the selected mn modulation method. The block of is mn modulated to generate the modulation block data, and each data is from the modulation scheme number data group satisfying the d constraint,
A digital modulation method, wherein modulation scheme number data corresponding to the selected m-n modulation scheme is selected and read, and the modulation scheme number data selected and read is added to the modulation block data and output. 37. The modulation method number data group according to claim 36, wherein each data item satisfies the d constraint so as to generate a number data group whose number exceeds the total number of the mn modulation methods. Then, based on this, an error correction code group is generated, and from the combinations in which the error correction code group is combined with the number data group, the number of combinations satisfying the d constraint is the same as the total number of the mn modulation schemes. A digital modulation method that consists of extracting. 38. Each m bit of input digital data is used as a unit of code modulation, and each m bit is m-n modulated into n bits (n> m) of modulated data (d, k; m). , N) In a digital modulation circuit for obtaining an RLL code, a block of digital data composed of a predetermined number of code modulation units is mn-modulated by a plurality of types of mn modulation methods. The calculation means for obtaining the DC component of each modulation block data, the comparison means for mutually comparing the magnitude of the absolute value of each DC component, based on the comparison result by the comparison means, the absolute value of the DC component is small Mn corresponding to modulation block data
Selecting means for selecting a modulation method; modulating means for mn modulating the block of digital data to generate modulated block data using the mn modulation method selected by the selecting means; From the modulation method number data group that satisfies
Number generating means for selecting and reading the modulation method number data corresponding to the mn modulation method selected by the selecting means; and a multiplexing circuit for adding the modulation method number data read by the number generating means to the modulation block data. , A digital modulation circuit having. 39. The number generation means according to claim 38, wherein the number generation means generates a number data group whose number exceeds the total number of the mn modulation schemes so as to satisfy the d constraint, and based on this, an error correction code is generated. A modulation method number formed by generating a group and extracting the same number of combinations satisfying the d constraint from the combination of the error correction code group and the number data group as the total number of the mn modulation methods. A digital modulation circuit having a table of data groups. 40. An m-type that converts an arbitrary n-bit (where n> m) array into an arbitrary m-bit array in a one-to-one correspondence.
Depending on the n modulation method, each m of the input digital data
In a digital modulation method in which m bits are each m-n modulated into n bits of modulation data using bits as a code modulation unit, arbitrary information and arbitrary information such that at least one m-bit array corresponding to the same information is different The input block data is m-m converted to describe an input block composed of a predetermined number of code modulation units by using a plurality of types of m-bit description methods associated with the m-bit array of , Number data indicating the description system of the block is added to each block after the m-m conversion, and an error correction code calculated for each of the number added blocks is added to each numbered block. To form an error correction code added block, and each of the error correction code added blocks is m-n modulated to obtain modulated block data. Of the DC component of the DC component are compared with each other, the m-bit description method corresponding to the modulation block data in which the absolute value of the DC component is small is selected, and the error correction code addition block based on the selected m-bit description method is m- A digital modulation method in which n modulation is performed to generate modulation block data. 41. An m-type that converts an arbitrary n-bit (where n> m) array into an arbitrary m-bit array in a one-to-one correspondence.
Depending on the n modulation method, each m of the input digital data
In a digital modulation method in which m bits are each m-n modulated into n bits of modulation data using bits as a code modulation unit, arbitrary information and arbitrary information such that at least one m-bit array corresponding to the same information is different In order to describe an input block composed of a predetermined number of code modulation units by using a plurality of kinds of m-bit description methods associated with the m-bit array of A plurality of types of block data are generated by converting the bit string according to the m-bit description method of each type, and number data indicating the description method of the block is added to each block data after the description method conversion to add a numbered block. Error correction code calculated for each numbered block is added to each numbered block to correct the error. Comparing the DC components of the respective modulation block data obtained by mn-modulating each of the error correction code addition blocks to form a code addition block, and corresponding to the modulation block data having a small absolute value of the DC component. A digital modulation method, wherein the m-bit description method is selected, and the error correction code added block based on the selected m-bit description method is mn modulated to generate modulation block data. 42. The method according to claim 40 or 41, wherein the selection is based on specifying the modulation block data having the smallest absolute value of the cumulative value of the DC component at the final bit of the modulation block data. Digital modulation method. 43. The digital modulation method according to claim 40 or claim 41, wherein the selection is based on specifying a modulation block data having a minimum absolute value of the maximum amplitude of the modulation block data. 44. An m-type which converts an arbitrary n-bit (where n> m) array into an arbitrary m-bit array in a one-to-one correspondence.
Depending on the n modulation method, each m of the input digital data
In a digital modulation circuit that m-n modulates each m-bit into n-bit modulated data by using bits as a code modulation unit, arbitrary information and arbitrary information such that at least one m-bit array corresponding to the same information is different The input block data is m-m converted to describe an input block composed of a predetermined number of code modulation units by using a plurality of types of m-bit description methods associated with the m-bit array of A data conversion circuit, a multiplexing circuit that adds number data indicating the description method of the block to each block converted by the data conversion circuit to form a numbered block, and an error correction code for each numbered block. An error correction coding circuit that forms an error correction code addition block by calculating and adding the error correction code addition block; Of each of the modulated block data obtained by m-n modulating each of the clocks, a comparing means for mutually comparing the absolute values of the DC components, and a comparison result by the comparing means. Based on m, corresponding to the modulation block data in which the absolute value of the DC component is small,
A digital modulation circuit comprising: selection means for selecting a bit description method; and modulation means for mn modulating the error correction code addition block based on the selected m bit description method to generate modulation block data. 45. An m-type which converts an arbitrary n-bit (where n> m) array into an arbitrary m-bit array in a one-to-one correspondence.
Depending on the n modulation method, each m of the input digital data
In a digital modulation circuit that m-n modulates each m-bit into n-bit modulated data by using bits as a code modulation unit, arbitrary information and arbitrary information such that at least one m-bit array corresponding to the same information is different In order to describe an input block composed of a predetermined number of code modulation units by using a plurality of kinds of m-bit description methods associated with the m-bit array of Convert to a bit string according to the m-bit description method of the type,
A data conversion circuit that generates a plurality of types of block data; a multiplexing circuit that adds number data indicating the description method of the block to each block data converted by the data conversion circuit to form a numbered block; An error correction coding circuit that forms an error correction code addition block by calculating and adding an error correction code to each number addition block, and each obtained by m-n modulating each of the error correction code addition blocks. Calculation means for obtaining the DC component of each of the modulation block data, comparison means for mutually comparing the magnitude of the absolute value of each DC component, based on the comparison result by the comparison means, modulation with a small absolute value of the DC component The m corresponding to the block data
A digital modulation circuit comprising: selection means for selecting a bit description method; and modulation means for mn modulating the error correction code addition block based on the selected m bit description method to generate modulation block data. 46. The mute according to claim 44 or 45, wherein the selection means corresponds to the modulation block data having the minimum absolute value of the cumulative value of the DC component at the final bit of the modulation block data. Digital modulation circuit that selects n modulation method. 47. The method according to claim 44 or 45, wherein the selecting means selects an m-n modulation method corresponding to the modulation block data having the smallest absolute value of the maximum amplitude of the modulation block data. Digital modulation circuit. 48. The method according to claim 44 or 45, further comprising a memory that stores each of the error correction code added blocks, wherein the modulation means is selected from the memory by the selection means. A digital modulation circuit that reads an error correction code addition block corresponding to the m-bit description system and performs m-n modulation. 49. The memory according to claim 44, further comprising a memory that stores the input block data, and read the input block data from the memory, and use the m-bit description method selected by the selection means to perform m.
A second data converting circuit for performing m conversion, a second multiplexing circuit for adding number data indicating the description system selected by the selecting means to the block converted by the second data converting circuit, A second error correction coding circuit for calculating and adding an error correction code to the block to which the number data is added by the multiplex circuit of No. 2 and outputting the block to the modulation means. 50. The memory according to claim 45, further comprising: a memory that stores the input block data; and an input block data read from the memory, and a bit string of the input block data is selected by the selecting means. A second data conversion circuit for converting into a bit string according to the bit description system, and a second multiplexing circuit for adding number data indicating the description system selected by the selecting means to the block converted by the second data conversion circuit. And a second error correction coding circuit for calculating and adding an error correction code to the block to which the number data is added by the second multiplexing circuit and outputting the block to the modulation means. 51. Each n-bit of input digital data is m-bit as a code demodulation unit (provided that n> m).
Demodulation data is demodulated by n−m to sequentially generate demodulation block data corresponding to a predetermined number of code demodulation units, and the demodulation block is generated using the error correction code added to the sequentially generated demodulation block data. Data is error-corrected, number data indicating a description system of the demodulation block data is detected from the demodulation block data after the error correction, and the demodulation block is demodulated using the m-m inverse conversion system specified by the number data. A digital demodulation method in which data is m-m inversely converted into another block data having a different m-bit array corresponding to at least one piece of the same information. 52. Each n-bit of the input digital data is m-bit as a code demodulation unit (however, n> m).
Demodulation data is demodulated by n−m to sequentially generate demodulation block data corresponding to a predetermined number of code demodulation units, and the demodulation block is generated using the error correction code added to the sequentially generated demodulation block data. The data is error-corrected, the number data indicating the description system of the demodulation block data is detected from the demodulation block data after the error correction, and the demodulation block data is block data of the bit string according to the description system specified by the number data. Digital demodulation method to convert to. 53. Each n-bit of the input digital data is m-bit as a code demodulation unit (provided that n> m).
Demodulation data of n-m to sequentially generate demodulation block data corresponding to a predetermined number of code demodulation units, and an error correction added to the demodulation block data sequentially generated by the demodulation circuit. An error correction circuit that corrects the demodulation block data by using a code, a detection circuit that detects the number data indicating the description method of the demodulation block data from the demodulation block data after the error correction, and the detection circuit specified by the number data. And an inverse conversion circuit for inversely converting the demodulated block data into another block data having a different m-bit array corresponding to at least one piece of the same information by using the inverse m-m conversion method. circuit. 54. Each n-bit of the input digital data is m-bit as a code demodulation unit (where n> m)
Demodulation data of n-m to sequentially generate demodulation block data corresponding to a predetermined number of code demodulation units, and an error correction added to the demodulation block data sequentially generated by the demodulation circuit. An error correction circuit that error-corrects the demodulation block data by using a code, a detection circuit that detects number data indicating the description system of the demodulation block data from the error-corrected demodulation block data, and the demodulation block data. A description method conversion circuit for converting into block data of a bit string according to a description method specified by the number data, and a digital demodulation circuit.