JPH09219878A - Selective radio call receiver with message - Google Patents

Abstract

PURPOSE: To provide a selective radio call receiver capable of setting and reporting the alarm time to the respective plural receivers by providing a means for issuing an alarm for the clock of the receiver in response to the detection of the predetermined pattern of reception specifying signals. CONSTITUTION: When a desired frequency is received in the state (BS state) of intermittently applying an input signal voltage to a radio part 20 and a waveform shaping circuit 30 in a switching circuit 1 and efficiently utilizing power supply, prescribed reception signals are detected. As to the receiver for which the individual selective call number (ID) of the receiver is 'A1', when preamble signals (P) for BS cancellation are detected in a decoder 40, BS is cancelled and a voltage is continuously applied to the radio part. When frame synchronization signals are successively detected, the contents of a PROM 50 where the ID of the present receiver is written and the reception signals are compared and collated, and when matching is confirmed, message signals following ID signals are processed in a message data processing part 60.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a radio selective call receiver, and more particularly to a radio selective call receiver having a clock function.

[0002]

2. Description of the Related Art In recent years, the progress of device technology has been remarkable.
In the wireless selective call receiver as well, from the conventional call-only function to the one that can receive even a series of messages composed of numbers and letters, the reception function has been improved and the device has been downsized. Development is remarkable.

[0003]

Although a device having a clock function may be considered as a part of such an enhancement of the function ("Practical application No. 54-142160", a personal selective calling receiver with a display), an alarm time setting function. No device has been announced yet.

An object of the present invention is to wirelessly select a clock function (with a calendar function) for receiving time information (month / day information) sent regardless of an individual selection call number and sequentially calibrating an internal clock (internal calendar). It is to provide a call receiver.

Another object of the present invention is to provide a radio selective calling receiver having a clock function and capable of receiving a message, the radio selective calling receiver capable of arbitrarily setting an alarm time by the message signal. is there.

[0006]

A radio selective call receiver with a message according to the present invention is a radio call receiver which receives a call signal composed of a frame synchronization signal, a selective call signal, a designation signal and a message signal. Means is provided for issuing a warning in response to the detection of a predetermined pattern of the designated signal when the timepiece mounted on the receiver reaches the time given by the message signal.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings.

1 and 3 are block diagrams of a receiver used in the present invention. The outline of the operation of this receiver will be described with reference to FIGS. 1, 4 and 5.

FIG. 4 is a signal configuration diagram, in which [I] is a front signal pattern, (II) is a synchronization signal pattern, and [II].
I] is a configuration pattern of the address signal and the message signal, [IV] is a configuration pattern of the first control signal, [V]
Represents a configuration pattern of the second control signal, [VI] represents an end signal pattern, and FIGS. 5A (I) and A (II) together represent a time chart in normal operation. FIG. 5B shows It is a figure showing the time chart in the operation when the power is turned on after the preamble signal.

That is, the switching circuit 1 shown in FIG.
A state in which the voltage waveform shown in (j) of (I) is intermittently applied to the wireless unit 20 and the waveform shaping circuit 30 to achieve efficient operation of the power supply (this operation is generally referred to as battery saving. 5A (I) (a) in FIG. 5A (I) via the antenna 10, the radio unit 20, and the waveform shaping circuit 30 when a desired radio frequency arrives while a voltage is applied at (BS).
A received signal as shown in FIG. Here, the individual selective call number of the receiver (hereinafter referred to as "ID") "A1"
, The preamble signal for canceling the BS (hereinafter referred to as "P") is detected by the decoder 40 (D).
At T1), the BS is released and the voltage is continuously applied to the wireless section (j). In this way, the subsequent frame synchronization signal (hereinafter referred to as "SC") is detected (DT
2) and the programmable ID in which the ID of the own device is written
The contents of the read-only memory [P-ROM] 50 and the received signal are compared and collated to confirm the coincidence (DT3).
And message data (hereinafter referred to as “MD”) processing unit 6
At 0, the message signal following the ID signal is processed. Then, the signal (d) drives the transmission means (for example, an alarm horn) via the buffer 70, or the signal (c).
The contents of the message data received by the liquid crystal display device [L
CD] 90, or output to the terminal 5 as a signal (g). Here, since a central processing unit (CPU) that requires high-speed processing capability and a dynamic drive type LCD drive usually require a voltage of 2 V or higher, a booster circuit 7 that boosts the voltage of the battery 6 is used.

Now, details of the respective components P, SC, ID and MD of the above-mentioned received signal (a) are shown in FIG.

The preamble signal P is a repeating pattern of logic "1" and "0" as shown in FIG. 1I, and the frame synchronization signal SC is a specific pattern shown in FIG. Individually selected call number ID is shown in the figure [III]
The MSB (identification bit) is a BCH (31, 21) code having an inter-code distance 5 of logic "0" in the configuration pattern shown in FIG.
I], the MSB (identification bit)
Is given as a logic "1" and is divided into a first control signal "T", a second control signal "I" and an information message M as shown in FIGS. 5A (I) and A (II). There is. That is, the first control signal shown in (IV) of FIG.
(I) Code Z0 as message information indicated by "1" when there is a message addressed to the own device and "0" when there is no message
(Ii) Information designating the format of the subsequent message (for example, "001" if the message is numeric information composed of BCD code, "010" if the message is ASCII code compatible, and "10" if it is JIS code compatible.
0 ", or" 111 "for facsimile information), and (iii) the time from the first control signal to the next SC, T, or I, as shown in FIG. 5A (I). 31 bits as 1 for the specified duration information
BCD codes Z2 to represent the number of words when words are used
Z5.

The second control signal shown in FIG. 4 [V] is a signal "MCS" for designating the processing of the received message and a signal "TS" for indicating time or date information.
It consists of.

Here, the meaning of Table 1 which defines the message processing corresponding to the MCS pattern is as follows.

[0015]

[Table 1]

First, item 1 means that the received message is not processed. Items 2 and 3 indicate that the ID corresponding to the received message is set as the ID of the own device, or conversely, the ID registered in the own device is changed. Item 4 sets the built-in clock and sounds the ring alert at the time corresponding to the received message. Item 5 secures the message memory area according to the ID and byte information corresponding to the received message. Item 6 is that the receiver receives the time from BS start to SC detection as a message signal, and when the SC cannot be detected within the time, some means (for example, an alarm horn sounds with a sound different from the normal ringing sound). Sound) to warn. For items 7 and 9, the contents of the received message are arranged according to a predetermined format (see Tables 2 and 3) and output.

[0017]

[Table 2]

[0018]

[Table 3]

Item 8 processes the TS shown in FIG. 4 [V] as month / day information. Note that TS represents normal time information, and the code configuration in each case is shown in Table 4. Next, FIG.
The pattern I] corresponds to the signal E in the signal (a) of FIG. 5A (II) and is used as an end signal.

[0020]

[Table 4]

The decoder 40 shown in FIGS.
As the SC detection circuit, as shown in FIG. 6, a reception signal is fetched into the shift register 500 in series by a clock as shown in FIG. 6, and it is determined whether the read 31 bits have a predetermined desired pattern. That is, if it is a desired pattern, the AND gate 540 outputs a coincidence signal. Further, as shown in FIG. 7 as the ID detection circuit, the received signal (a) and the signal (e) from the P-ROM 50 in which the calling number of the own machine is written are EXNOR.
It is input to 610 and collated for each bit, and the coincidence output is input to the counter 600. As a result, the own device is called by the detection pulse output when the number of coincident inputs reaches a preset value.

Next, the buffer 70 is provided with a circuit configuration using transistors as shown in FIG. The message processing unit 60 in FIG. 2 is a 1-chip CPU (message decoder) 100, a random access memory [R
AM] 300 and an LCD driver 200, and the RAM 300 includes a diode 61 and a large-capacity capacitor 63. The backup circuit allows data protection even when the battery is replaced.

The configuration of the 1-chip CPU 100 in the message processing unit 60 shown in FIGS.
This is shown in FIGS. The decoder 8 in FIG. 3 is provided by the one-chip CPU shown in FIG. 10, and the function of each block is as follows. 102-106,119
121 to input ports, 101, 110 to 118, 12
2 is an output port, 107 is an interrupt port, 108 is a serial interface, 120 is a data bus, 130
Is a program counter indicating the contents of the address, 140 is a program memory that stores the sequence of instructions to be executed, and reads the contents of the address specified by the program counter 130, 160 decodes the information from the program memory 140, and sends it to each section. An instruction decoder for supplying a control signal corresponding to the instruction, 150 is an ALU (Ari) for performing various operations such as arithmetic operation and logical operation.
thmetric and Logic Unit), 1
Reference numeral 80 denotes a RAM used to store various data, a program count in a subroutine and an interrupt, a calculation result of the ALU 150 for saving a program status, an ACC (Accumulator) used for transmitting and receiving data between each port of the RAM 180, and 1
Reference numeral 90 is a system clock generation circuit that determines the execution instruction cycle time.

Next, the LCD driver 200 is given in the block configuration of FIG. 12, and 295 is the one-chip CPU 100.
A serial interface 270 for serially connecting the data between the input and output terminals, a command decoder 270 for fetching and decoding an instruction input via the serial interface 295, and controlling each unit according to the content of the instruction, 29
0 is a character generation circuit for generating a pattern of a 5 × 7 dot matrix corresponding to the input data,
280 is a data pointer for designating the writing of data from the serial interface 295 or the reading address of the data to the serial interface 295, 250 is a data memory for storing the output of the character generation circuit 290 or the display data from the serial interface 295, Reference numeral 220 is a row driver for controlling the row of the LCD, 210 is a column driver for controlling the column of the LCD,
Reference numeral 230 denotes an LCD voltage controller that controls the voltage to the LCD, and 240 denotes L that controls the drive timing of the LCD.
The CD timing controller, and 260 is the system clock controller.

Further, the RAM 300 is provided with the block configuration of FIG. 13, 310 is a serial interface for serially transferring data to and from the one-chip CPU 100, 320 is an address counter, and 330 is data of the address counter 320. Memory array 340
Is an XY decoder for designating the address of, and writing or reading data in the memory, 340 is a memory array, and 350 is a control circuit.

FIG. 14 shows a configuration example of the switching circuit 1. FIG. 15 shows the data structure of the output signal (g) to the external terminal 5, where each character has 11 bits. FIG. 16 shows a circuit example of the level shift 3. FIG. 17 shows an example of the key layout of the data input section.

The operation of the receiver in each case will be described below.

A) When the desired signal is received after the power is turned on
As shown in FIG. 5A (I), among the receivers in the BS state, the one corresponding to the ID of A1 is SC after the reception of P.
Is detected, the subsequent signal T1 is decoded. At this time,
Since the message data M1 follows, Z0 is a logical "1", and the period represented by the BCD code of Z2 to Z5 (at least until the next SC, usually A2 and T2)
The BS is released (OFF). Further, when "1000111" is received as the "MCS" pattern when decoding I1, the message data of M1 is decoded by the code corresponding to Z1 and stored in the RAM 300 and the LCD.
This is displayed on the LCD 90 via the driver 200, and the transmission means 80 is driven via the decoder 40 and the buffer 70 to notify the device holder of the calling. Also I
The built-in calendar is calibrated with the month / day information of the 1 “TS” pattern.

Then, the following SC, ID, T2 and I2 are detected and decoded. At this time, SC is detected, but since the ID signal is A2 and is not detected, the detection pulse DT3 is not output. Therefore, "MCS" of Z2 to Z5 of T2 and I2,
Looking at only the “TS” pattern, after detecting the signal of I2, Z2
While turning on the BS for the period indicated by Z5 (usually before the next SC), when "MCS" is other than 1000111, the built-in clock is calibrated at the time corresponding to the "TS" pattern, and the received and stored message is stored. The reception time is added to.

Thus, at the time of the next SC, B again
S is turned off. Since this period also has a different ID for A3 and the internal clock has already been calibrated, the period is up to T3. Thereafter, such an operation is repeated, and when the end signal E indicating the end of the data is detected, the normal BS operation is restored.

In the receiver whose ID corresponds to A3, P
SC is detected following the reception of T1, but since the IDs do not match at A1, Z2 to Z5 and I1 of T1 are detected.
See only the "TS" pattern of. And after turning on the period BS shown by Z2-Z5 after detecting the signal of I1,
Calibrate the built-in calendar on the month and day corresponding to the "TS" pattern. Then, at the time of the next SC, BS again
Is OFF until I2, SC is detected, but ID
Are not detected, so that Z2 to Z5 of T2 and "M
Only see the "CS" and "TS" patterns. Then, after detecting I2, turn on the BS for the period from Z2 to Z5, and
When S "is other than 1000111, the built-in clock is calibrated at the time corresponding to the" TS "pattern. Of course, when the" MCS "pattern is 1000111, the built-in calendar is calibrated with the month / day information corresponding to the" TS "pattern. Thus, at the next SC time, the BS turns off again,
This is the SC detection operation. When SC and ID are detected, the BS OFF state continues for the period of Z2 to Z5 at T3, and the "MCS" pattern is 1000011.
Then, the time corresponding to M3 decoded by the code corresponding to Z1 is stored. When the built-in clock reaches the predetermined time, the transmission means 8 is passed through the decoder 40 and the buffer 70.
While 0 is driven, the fact that it is a setting alarm is displayed on the LCD 90 (FIG. 18 is an example). Also, the built-in clock is calibrated again with the time information corresponding to "TS" of I3. After that, when there is no ID corresponding to A3 and the end signal E is received, the normal BS operation is restored.

By the way, in this embodiment, as long as the end signal E is not received, the signal T is checked regardless of whether the SC is received or not, and if this signal cannot be received correctly, a predetermined constant period ( In this embodiment, the BS is forcibly turned off, the operation shifts to the reception of the SC signal, and if it cannot be detected, the normal BS operation is resumed, and the SC continues 2 times.
If it is not detected more than once, it is determined that the electric field is defective and normal BS
By returning to operation, the battery is used effectively and the reliability of reception is improved.

B) When a desired signal arrives and power is turned on . In FIG. 5B, the receiver whose ID is AN is continuously turned on B for a predetermined period (about 1 minute in this embodiment) when the power is turned on.
S is turned off, and a desired SC signal is detected. When the SC signal is detected in this way, the ID is detected but not received. Therefore, after the I2 is detected, the built-in calendar or clock is calibrated with the "TS" information according to the "MCS" pattern, and the Z2 of the T2 is detected. The BS is turned on during the period from Z5 to Z5. Then, at the next SC, the operation of turning off BS again is repeated. Thus, when the ID corresponding to AN is received, the BS of the TN during the period from Z2 to Z5 is turned off,
If the "MCS" pattern of IN is 1000101, TN
The message data MN is decoded and stored by the code corresponding to Z1. As a result, if the SC is not detected by the time when the time corresponding to the received data is confirmed by the built-in clock after returning to the BS operation, a warning alarm is issued to notify that the service area is not in good condition. (When it is detected, the timer is stopped and restarted by returning to the BS.), And the BS is forcibly set to BSOFF for a predetermined fixed period (about 1 minute in this embodiment).
The C detection is performed, and the operation of returning to the BS operation is repeated if the SC is not detected in the certain period.

C) Registration / reading by manually inputting fixed form information
The operation will be described below with reference to Table 5 and FIG.

[0035]

[Table 5]

A desired key is selected from the mode SW of the data input section 2 (however, when the "CAL" or "TIME" key is selected, the LCD 90 operates in cooperation with the CPU as a computer function or a clock function). . Also here, "TE
When the "L" key is pressed, an interrupt is issued from the K terminal of the interrupt port 107 shown in FIG.
The pattern corresponding to the "EL" key is input. As a result, the CPU recognizes that the device has been set to the "TEL" mode, and thereafter, the data such as "DA" is input from the input port 103.
TA IN ”,“ AOKI ”,“ DATA IN ”,
“NEC”, “DATA IN”, “03-262-5”
174 "," DATA IN "," KUDO "," DA
"TA IN", "SONY", etc. are input. When the result of key input is confirmed, the data is read out according to a predetermined format (see Table 2), and first "DATA
Pressing the “OUT” key causes “AOKI” to be displayed on the LCD, and then pressing the “→” key causes “NEC” to be further changed to “→”.
If you press the key, press "03-262-5174", then press the "→" key, "KUDO", and then press the "↓" key, "E"
NDO ”,“ → ”key for“ KDD ”,“ ↑ ”key for“ S ”
You can check it like "ONY".

Similarly, when the "MEMO" key is pressed,
An interrupt is generated from the K terminal of the interrupt port 107, and the pattern “0010011” corresponding to the “MEMO” key is input from the input port 102. This result C
The PU determines that the device has been set to the "MEMO" mode, and thereafter inputs the following data ["DATA IN", "FEB.10.1984" input from the input port 103.
SCHEDULE ”,“ DATA IN ”,“ 9: 0 ”
0 ”,“ DATA IN ”,“ MEETING (NEW
PRODUCT) AT5-1 "," DATA I
N ”,“ 10:30 ”,.
When the "OUT" key is pressed, "FEB. 10.1984 SCHEDULE ”is displayed, and when the“ → ”key is pressed, the LCD display is“ 9:00 ”.
The display changes to "MEETIN" when the "→" key is pressed.
G (NEW PRODUCT) AT5-1 ", and then press the" ↓ "key," TEL (NTT MR KUD
O) ”and the necessary information can be checked at any time with a simple operation instead of a memo pad.

Further, since the present receiver has a built-in calendar and a built-in clock, at the time of "FEB.10""9:00","10:30", ... For example, an alarm or a horn) is driven to call attention and a display corresponding to the ringing time is displayed on the LCD 90. For example, at 18:00, "GIN
ZA (MORE) "will be displayed on the LCD.

D) Registration of fixed form information by radio The operation of the receiver will be described with reference to FIGS. 1, 9, 12, and 13.

When a preamble signal P is received while a voltage is applied to the radio section 20 and the waveform shaping circuit 30 of the receiver operating in the BS in the switching circuit 1, the following predetermined synchronization signal SC is detected. Only BS is turned off for a sufficient period of time. Then, when SC is detected during this time, the one-chip CPU 100 is activated by the detection pulse DT2 through the interrupt port 107, and the decoder 40 shifts to the ID detection operation. That is, the P number in which the own ID number is written starting from the detection of the SC
The data of the ROM 50 and the received data are compared and collated bit by bit (FIG. 7), and when the coincidence is confirmed, the detection pulse DT3 causes a 1-chip CPU via the input port 121.
The clock CL corresponding to the transmission speed is supplied from the input port 105 while being input to 100. At this time,
If DT3 is input after a predetermined period (time until DT3 is detected) from the interrupt activation by DT2, it is determined that the ID has been detected, and if not, it is determined that the ID does not match and the subsequent signal is detected. Prepare for reception. As a result, in the 1-chip CPU 100, the message signal D is read from the input port 106 at the clock CL, the contents of the predetermined program memory 140 are translated by the instruction decoder 160, and processed in accordance with each instruction. That is, the read signal is transmitted to the data bus 12.
0, written in the RAM 180 via the ACC 170.

Thus, every time 31 bits forming the BCH (31, 21) code are input, the ALU 150 performs an operation to decode the received signal.

The one-chip CPU 100 decodes 20 information bits of the first decoded BCH (31, 21) code in accordance with FIG. 4 (IV), and thereafter performs the BS operation of the receiver via the output port 112. Control.
At this time, if the 20 information bits have the following pattern, "110100000000000100000"
A "0" call is accompanied by a message, the message data has a 7-bit structure, and it is necessary to release the BS for at least 20 words (here, one word is 31 bits).

Then, the signal I is decoded after waiting for the input of the next 31 bits. Thus, the 20-bit information area is analyzed according to FIG. 4 [V], Table 1 and Table 4.
That is, if the information bit has the following pattern, "11
0001100101000100000 ”indicates that the subsequent message data is processed in the telephone directory mode and that the data transmission time is 10:20 AM.

The subsequent message is processed according to the control contents decoded in this way. Therefore, the information area (20-bit data) decoded every 31 bits is decoded in 7-bit units and sequentially stored in the external RAM 300. That is, by setting the chip select CS1 (negative logic) to the logic "0" level, the RAM 300 is set to the operation mode, and the address of the RAM 300 to be written is determined by the serial interface 108.
The corresponding address information is transferred via the signal line SO via. At this time, the 1-chip CPU 100 sends the system clock to the RAM 300 by SCK (negative logic) and at the same time, indicates that it is an address, and the signal line A / D (negative logic).
The signal line A / D (negative logic) is set to the logic "1" level to indicate that it is an address at the same time. And
At this time, in FIG. 13, the RAM 300 receives the input control signals (CS (negative logic), A / D (negative logic), R / W).
(Negative logic)), the signal input from the signal line SO is determined as an address signal, and the address counter 320, X
An address to be written in the memory array 340 is designated via the Y decoder 330.

Next, the 1-chip CPU 100 sends the message data to be written to the serial interface 10
No. 8 signal line SO and the signal line A / D (negative logic) is set to a logic “0” level to indicate that the send data is message data, and the signal line R / W (negative logic) is used to instruct writing. ) Is a logic "0" level.

As a result, in the RAM 300 of FIG. 13, the data input via the signal line SO is treated as message data corresponding to each input control signal via the XY decoder 330 and the memory array 340. Write in the address specified earlier.

When the message data is sequentially decoded in the above process, when the SC or the end code is detected in the BCH (31, 21) unit or the reception is impossible in two consecutive words, the 1-chip CPU 100 is used. Determines that the message data has ended, notifies the decoder 40 of the end of the message from the output port 110 via the signal line ME, and causes the sound generation circuit of the decoder 40 to operate with the signal line AC via the output port 111. To drive. The resulting signal (d), the alarm horn 8 via the buffer 70
0 sounds. Here, in the case of SC detection, one chip CP
U100 repeats the same operation as above, but when the end code is received or two consecutive words have not been received,
The operation returns to the S operation.

As described above, the code corresponding to the desired content is input to the receiver as a normal message.

Next, in order to read the data received and stored in this way, the one-chip CPU 100 supplies the first address information of the corresponding message data to the RAM 300 from the signal line SO by pressing the read switch S1. , The chip enable signal line CS1 (negative logic) to the logic "0" level, the chip select signal line CS2
(Negative logic) (this is a signal line for selecting the LCD driver 200) and the signal line A / D (negative logic) are set to the logic "1" level. Next, the signal line A / D (negative logic) is set to the logic "0" level, and the signal line R / W (negative logic) is set to the logic "1" level. As a result, the data corresponding to the above-mentioned first address is X.
The data is read from the memory array 340 via the Y decoder 330 and the data is read from the serial interface 3
It is supplied to the one-chip CPU 100 via the signal line SI via 10. In this way, when the data is read from the RAM 300 and supplied to the 1-chip CPU 100, the signal line CS1
(Negative logic) and the signal line C / D (negative logic) are set to the logic "1" level, and the chip select signal line CS2 (negative logic) is set to the logic "0" level to select the LCD driver 200. The character conversion instruction and the storage address information are supplied to the LCD driver 200 from the signal line SO. Subsequently, the 1-chip CPU 100 sets the data read from the RAM 300 to the signal line S by setting the signal line C / D (negative logic) to the logic “0” level.
O supplies it to the LCD driver 200.

As a result, the LCD driver 200 shown in FIG.
In the case of the information which is serial-parallel converted by the serial interface circuit 295, when the signal line C / D (negative logic) is at the logic "1" level, the command decoder 27
0, the command decoder 270 generates an internal control signal. Here, if the command is a write command or a character conversion command, the data pointer 280 is accessed to set the write address, and when the signal line C / D (negative logic) becomes the logic “0” level, the serial interface 295. The data input via the character generation circuit 290 is converted into a pattern of a 5 × 7 dot matrix by the character generation circuit 290 and written in the data memory 250, and is also controlled by the LCD timing controller 240 via the column driver 210 and the row driver 220. Signal C is displayed on the LCD 90.

E) Registration / Changing of Common ID The operation of the receiver will be described with reference to FIGS. 3, 10, and 11.

FIG. 3 is a diagram in which the configuration between the decoder 40 and the message processing unit 60 (the configuration example of the one-chip CPU 100 is FIG. 11) in FIG. 2 is partially changed. In particular, the decoder 8 serves as a RAM / decoder for the common ID. (In this example, a one-chip CPU is used, and its configuration is shown in FIG. 10).

Now, when the preamble signal P is received while the voltage is applied to the radio section 20 and the waveform shaping circuit 30 of the receiver operating in the BS in the switching circuit 1,
Subsequently, the BS operation is stopped for a sufficient period of time to detect the predetermined synchronization signal SC. When SC is detected during this time, the interrupt port 10 is detected by the detection pulse DT2.
The 1-chip CPU 100 and the decoder 8 are started via 7 and the decoder 40 is a P-ROM in which the individual selective call number of the own device is written starting from the detection of the SC.
The data of 50 and the received data are compared and collated bit by bit.

In this way, if the received data coincides with the individual call number of the own machine in the P-ROM 50, the detection signal DT3 is input from the input port 121 in FIG.
As a result, the CPU activated by the SC detection pulse DT2
At the time when D is to be detected, 1 instead of input port 119
It is judged that the input is from 21, and the detected ID is recognized as the individual selective call number, and the system prepares for reception of the message signal sent subsequently.

That is, in the 1-chip CPU 100, a signal following the ID is read from the input port 106 by the clock CL, the data bus 120, and the accumulator ACC1.
The data is written to the RAM 180 through the RAM 70. Thus BCH
Every time 31-bit data forming the (31, 21) code is input, the ALU 150 performs an operation to decode the received signal. Of the 31 bits thus decoded, 20 information bits are decoded according to FIG. 4 [IV], and thereafter the BS operation of the receiver is controlled via the output port 112. At this time, if the 20 information bits have the following pattern, "1101000000"
000000110010 ”indicates that the call has message information composed of a 7-bit unit code afterward, and indicates that the BS operation needs to be canceled for 32 words. That is, the one-chip CPU 100 has 32
Set and start the word timer.

Then, the signal I is decoded after waiting for the input of the next 31 bits. The 20-bit information area thus obtained is analyzed in accordance with FIG. 4 [V], Table 1 and Table 4. That is, if the information bit has the following pattern, "11000100011001000110110",
Some message data that follows is registered as a common ID, which means that the current time is PM 2:36 minutes.

Therefore, the built-in clock of the 1-chip CPU 100 is calibrated, and the following message data is 31
It is decoded bit by bit, and 20 bits in it are decoded in 7-bit units. Here, if the pattern of the 20-bit information area of the received message is as follows, Table 6 (I),
6 (II) (ISO 7-bit code correspondence table, ISO64
(Extracted from 6)

[0058]

[Table 6]

SONY brand, ID "01101 ... 01"
1011 ”is registered, but the one-chip CPU 100
A label of Sony is attached to an empty number of the common ID area of M300, and the corresponding number and ID pattern of the ID area are transferred to the decoder 8.

[0060]

[Table 7]

[0061]

[Table 8]

That is, the chip select CS4 (negative logic) is set to the logic "0" level and the system clock SCK is set.
(Negative logic) and the serial output SO from the common ID area number (for example, 0110 = 6) and the ID pattern “0110”.
1 ... 011011 "is output. At this time, the decoder 8
Since the chip enable CE (negative logic) becomes logic "0", it prepares for reception, and the data input together with the subsequent system clock is transferred from the serial input SI through the serial interface 108 and the data bus 120 to the R level.
The ID is registered as the sixth ID in the AM 180.

If the pattern of the information bits of the received signal I is as follows, "11000010"
010100010000 ", the following message data has a common ID to be changed, and the time at the time of transmission is AM
11:30. If the pattern of the 20-bit information area of the received message is as follows, the 1-chip CPU 100 of FIG.

[0064]

[Table 9]

The area corresponding to the TDK of the label of the common ID area of the RAM 300 is searched, the area is changed from TDK to NEC, the chip select CS4 (negative logic) is set to the logic "0" level, and serialized with the system clock SCK (negative logic). The output SO outputs the common ID area number and the ID pattern “011010 ... 0111”. As a result, the input data is written in the area corresponding to the ID number in the RAM of the decoder 8.

Thus, when the detection of SC is confirmed in the state where the common ID is registered in the decoder 8, the decoder 8 in FIG.
Is supplied from the input port 105, the data D following the SC is read from the input port 106, the contents of the predetermined program memory 140 are translated by the instruction decoder 160, and processed according to each instruction.

That is, the above-mentioned read data is compared and collated bit by bit with the common ID (a plurality if there are a plurality) registered in the RAM 180 in advance in the ACU 150 via the data bus 120.

If a match with the common ID is confirmed, the data detection information DI is transmitted from the output port 113 to the 1-chip CPU 100 (FIG. 11) in the message processing unit 60, and the detected ID is the common ID area. The information DE indicating the order of the number is output from the output port 114 to the one-chip CPU 100.

The one-chip CPU 100 recognizes that the common ID is received by the signal from the input port 119 during the fixed period required for ID detection from the interrupt activation by the detection pulse DT2 of the SC, and the subsequent common ID area information is input to the input port 120. Read from.

As a result, since the received message data is stored in the RAM 300, the chip select CSI
(Negative logic) is set to logic “0” level, and the address information corresponding to the data from the input port 120 is transferred from the signal line SO via the serial interface 108. At this time, the 1-chip CPU 100 sets the system clock to S
At the same time as sending by CK (negative logic), the signal line A / D (negative logic) is set to the logic "1" level to specify that it is an address.

When the address setting of the RAM 300 is completed in this way, the message data received with the A / D (negative logic) at the logic "0" level is transferred from the signal line SO to the RAM 3.
Write to the designated address area of 00.

When the received message data is output to the outside, the chip select CS3 (negative logic) is set to logic "0", and the structure of one character is output from the output port 122 to the level shift circuit 3 in the format shown in FIG. Output.

If a signal processing unit connectable to the external terminal 5 of the receiver is used, it is possible to add desired processing to the data received via radio.

Since the receiver has an individual selective call number as an ID and a common ID, it is conceivable that the message storage areas of the RAM 300 are individually provided.
Then, if it is desired to change the distribution of the area, it can be arbitrarily set by using the MCS pattern of the signal I and the message data.

[0075]

As described above, according to the present invention, at least a frame synchronization signal, a selective calling signal, a control signal and a message signal are arranged in this order, and a predetermined code of the control signal is used. Depending on the contents of the subsequent message signal, a wireless selection that can receive message information equipped with means for calibrating the built-in clock (built-in calendar) installed in the receiver and means for issuing an alarm at the time specified by the message signal A call receiver can be provided.

Further, since the alarm is generated at the time designated by the predetermined code of the control signal and the subsequent message signal, the alarm time can be set and notified to each of the plurality of receivers. Have.

[Brief description of drawings]

FIG. 1 is a block diagram of a wireless selective calling receiver with display.

FIG. 2 is a block diagram of a message data processing unit 60;

FIG. 3 is a second block configuration diagram of the radio selective call receiver with display.

FIG. 4 is a signal configuration diagram.

FIG. 5 is a time chart at the time of normal operation and when power is turned on after a preamble signal.

FIG. 6 is a block diagram showing a circuit for detecting a synchronization signal and an end signal.

FIG. 7 is a block diagram showing an address detection circuit.

FIG. 8 is a circuit configuration diagram of a buffer 70.

FIG. 9 is a block diagram of the one-chip CPU 100.

FIG. 10 is a block configuration diagram of a 1-chip CPU 8.

FIG. 11 shows one chip C in the message processing unit 60 of FIG.
FIG. 2 is a block diagram of a PU 100.

FIG. 12 is a block diagram of the LCD driver 200.

13 is a block diagram of an external RAM 300. FIG.

FIG. 14 is a block diagram of the switching circuit 1;

FIG. 15 is a diagram showing a format of output data from a data input unit 2.

16 is a configuration diagram of a level shift circuit 3. FIG.

FIG. 17 is a diagram showing a key arrangement of the data input unit 2.

FIG. 18 is a diagram showing an example of a display indicating that a setting alarm has been issued.

FIG. 19 is a diagram illustrating an example of battery saving in which a battery is turned on in a time slot (G7) of a group to which the own device belongs.

[Explanation of symbols]

1 switching circuit, 2 data input section, 3 level shift circuit, 6 battery, 7 booster circuit, 8 decoder,
10 antennas, 20 radio units, 30 waveform shaping circuits,
40 decoder, 50 P-ROM, 60 message data processing unit, 61 and 62 diode, 63 and 64 capacitor, 70 buffer, 80 alarm horn (transmission means), 90 LCD, 100 1-chip CPU (message decoder), 101/110 -11
8 output port, 102-106, 119 input port, 107 interrupt port, 108 serial interface, 120 data bus, 130 program counter, 140 program memory, 150 ALU, 1
60 instruction decoder, 170 ACC,
180 RAM, 190 system clock generation circuit,
200 LCD driver, 210 row driver, 2
20 row driver, 230 LCD voltage controller, 240 LCD timing controller, 250
Data memory, 260 system clock controller, 270 command decoder, 280 data pointer, 290 character generation circuit, 295 serial interface, 300 external RAM, 310 serial interface, 320 address counter, 33
0 XY decoder, 340 memory array, 350
Control circuit, 500 shift register, 510-530
Inverter, 540 AND gate, 600 counter,
610 EXNOR gate, 710/720 resistor, 73
0 NPN transistor, 740 PNP transistor, 800 alarm horn, 1a PNP transistor, 1b and 3c NPN transistor.

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] February 20, 1997

[Procedure amendment 4]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG. 7

FIG. 14

FIG.

[Fig. 2]

FIG. 4

FIG. 16

FIG.

[Figure 3]

FIG. 6

[Figure 8]

FIG. 13

FIG.

[Figure 5]

[Figure 9]

FIG. 10

FIG.

FIG. 11

FIG.

FIG.

Claims (2)

[Claims] 1. A radio paging receiver for receiving a paging signal composed of a frame synchronization signal, a selective paging signal, a designation signal and a message signal, in response to detection of a predetermined pattern of the designation signal, A radio selective call receiver with a message, comprising means for issuing a warning when a clock mounted on the receiver reaches a time given by the message signal. 2. The radio selective call receiver according to claim 1, further comprising means for adding and storing the time of a clock mounted on the receiver as the reception time when receiving and storing the message signal. A radio selective call receiver with a message characterized by the above.