JPH0367371B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Application Field] The present invention relates to a wireless selective calling receiver that can improve the reliability of paging service reception.
In particular, it relates to devices having a wireless selective calling function that allows message reception. [Prior art and its problems] With the development of integrated technology in recent years, radio selective calling receivers have changed from conventional ones that only functioned for calling to ones that can even receive a series of messages consisting of numbers, letters, signals, etc. The improvement in functionality is remarkable. By the way, in an asynchronous system, there is a prefix signal at the beginning of the transmitted signal to start up the receiver that is in an intermittent receiving state, but when the signal comes out from underground or inside a building, etc., or when the power is turned on, It is possible that the data after the signal continues for a while. In such a case, the receiver in the intermittent reception state cannot wake up until the prefix signal is present, so there is a drawback that it cannot receive the selective call signal of its own machine even if it exists in the data mentioned above. . This becomes a very serious problem when a long message signal continues in one prefix signal. This accelerates the above-mentioned drawbacks in message services in paging services in recent years. [Object of the Invention] An object of the present invention is to overcome the above-mentioned drawbacks, and to be able to inform the receiver owner whether the receiver is currently in a state where it can receive normally, and to determine if it is not in a state where it can receive normally. To provide a radio selective calling receiver with a message capable of quickly putting the receiver into a receivable state and providing a highly reliable paging service. [Configuration of the Invention] According to the present invention, when the power is turned on, power is continuously supplied for a predetermined first period that is longer than the BS off period in the BS stroke, and then normal battery saving (hereinafter abbreviated as BS) is performed. ) Wireless selective call reception with reduced unreceived rate is obtained. According to the invention, battery saving (BS)
In a wireless selective calling receiver having the above function,
Means for performing normal BS operation after continuously supplying power for a predetermined first period longer than a BS off period in BS operation; Achieving a reduction in the unreceived rate by displaying a warning when a predetermined first signal is not detected and continuously supplying power for a predetermined third period. A wireless selective calling receiver is obtained. Further, according to the present invention, in the above receiver,
Reducing the non-reception rate, characterized in that the second period can be set to a required period according to a predetermined second signal in order to adapt to the requirements of the applied system. A wireless selective calling receiver that realizes this can be obtained. The present invention will be explained in detail below using the figures. [Example] Figures 1 and 3 show the first and second embodiments of the present invention.
1A and 1B each show a block diagram of a wireless selective calling receiver according to an embodiment of the present invention. An overview of the operation of this receiver will be explained using FIGS. 1, 4, and 5. Note that FIG. 5 shows a composite of A() and A() arranged side by side. That is, in the switching circuit 1, FIG. 5A()
When the voltage waveform shown in (j) is intermittently applied to the wireless unit 20 and the waveform shaping circuit 30 to ensure efficient operation of the power supply, that is, when the voltage is applied while BS is being performed, When a desired radio frequency arrives, the antenna 10, the radio section 20, and the waveform shaping circuit 3
A received signal as shown in (a) of FIG. 5A() is detected through 0. Here, if the receiver's individual selective calling number (hereinafter abbreviated as ID) is "A1", a preamble signal (hereinafter abbreviated as P) for BS cancellation is detected by the decoder 40 (DT1). , BS is released and voltage is continuously applied to the endless part (j). When the subsequent frame synchronization signal (hereinafter abbreviated as SC) is detected (DT2), the programmable read-only memory (PROM) 5 in which the ID of the own machine is written
The contents of 0 and the received signal are compared and verified, and when a match is confirmed (DT3), the message data (hereinafter referred to as MD
The processing unit 60 processes the message signal that follows the ID signal. Then, the signal (d) is transmitted via the buffer 70 to the alarm horn 8 which is the transmission means.
0, display the contents of the message data received using the signal (c) on a liquid crystal display (LCD) 90, or output it to the terminal 5 using the signal (g). Here, central processing units (CPUs) and dynamic drive systems that require high-speed processing power are used.
Since driving the LCD normally requires a voltage of 2V or more, a booster circuit 7 is used to boost the voltage of the battery 6. Now, each component P, SC, of the above-mentioned received signal (a),
Details of ID and MD are shown in FIG. First, the preamble signal P is a repeating pattern of logic "1" and "0" as shown in the same figure, the frame synchronization signal SC is a specific pattern shown in the same figure, and the individual selective call signal ID is a pattern shown in the same figure. In the configuration pattern shown in the figure, the MSB (identification bit) is a BCH31, 21 code having a logic "0" and an inter-symbol distance of 5, and the message data MD has the configuration pattern shown in the same figure, and the MSB (identification bit)
is given as logic “1”, and A(), A() in Fig. 5
As shown in FIG.
control signal "" and information message M. That is, the first control signal shown in Fig. 4 is "1" when there is a message addressed to the own machine.
If there is no message, code Z0 as message information is indicated as "0", and information specifying the format of the following message (for example, "001" if the message is an upper number consisting of a BCD code, or "001" if the message is an ASCII code compatible message). code Z1 as "010" for JIS code, "100" for JIS code, "111" for facsimile information, etc.) and Figure 5A.
As shown in (), from the first control signal to the next
It consists of BCD codes Z2 to Z5 representing the number of words when 31 bits are one word, as duration information specifying the time up to SC, T, or I. The second control signal shown in FIG. 4 is composed of a signal "MCS" for specifying processing of the received message, and a signal "TS" representing time or date information. Here, the meaning of Table 1 which defines message processing corresponding to the MCS pattern is as follows.
First of all, item 1 means that no processing is performed on the received message, and items 2 and 3 mean that the ID corresponding to the received message is set as the ID of the own device, or conversely, the ID registered in the own device is set. Indicates that the change is to be made. Item 4 sets the built-in clock to the time corresponding to the received message and sounds a call alarm. Item 5 stores the area of the message memory area according to the ID and byte information corresponding to the received message.
Secure a memory area. Item 6 is that the receiver receives the time from the start of BS to SC detection as a message signal, and if the SC cannot be detected within that time, it uses some means (for example, sounds an alarm horn with a different sound than the normal ring tone). (make a sound) to warn you. Items 7 and 9 arrange and output the contents of the received message according to a predetermined format (see Tables 5 and 6). Item 8 is the fourth
Process the TS in the figure as month/day information. Note that TS usually represents time information, and the code structure in each case is shown in Table 2. Next, the pattern in Figure 4 is the signal (a) in Figure 5 A(2).
This corresponds to signal E in , and is used as an end signal. Now, the decoder 40 in FIGS. 1 and 3
As shown in FIG. 6, the SC detection circuit inputs the received signal into the shift register 500 in series using a clock, thereby determining whether or not the read 31 bits have a predetermined desired pattern. That is, if it is a desired putter, a match signal is output from the AND gate 540. Also ID
As shown in FIG. 7 as a detection circuit. The received signal (a) and the signal (e) from the PROM 50, in which the calling number of the own machine is written in advance, are input to the exclusive NOR (EXNOR) 610, where they are compared bit by bit, and the matching output is counter 600
is input. As a result, when the number of matching inputs reaches a preset value, the detection pulse outputted indicates that the own device has been called. Next, the buffer 70 is provided with a circuit configuration using transistors, for example, as shown in FIG. The message processing unit 60 in FIG. 2 includes a 1-chip CPU (message decoder) 100, a random access memory (RAM) 300, and
Consists of 200 LCD drivers, 30 RAM
0 can protect data even when the battery is replaced by a backup circuit composed of a diode 61 and a large capacity capacitor 63. And Figure 1,
The configuration of the one-chip CPU 100 in the message processing section 60 in FIG. 3 is shown in FIGS. 9 and 11, respectively. Also, the decoder 8 in FIG.
is given by the one-chip CPU shown in FIG. 10, and the functions of each block are as follows. 102-106, 119-121 are input ports, 101, 110-118, 122 are output ports, 107 is an interrupt port, 108 is a serial interface, 120 is a data bus, 130
is a program counter indicating the contents of the address, 140
160 is a program memory in which a sequence of instructions to be executed is stored and reads out the contents of the address specified by the program counter 130; 160 is a program memory that decodes information from the program memory 140 and supplies control signals corresponding to the instructions to each section; The instruction decoder 150 is an ALU (Arithmetic
and Logic Unit), 180 is RAM used for storing various data, saving program counts and program status in subroutines and interrupts, ACC (ACC) is used to store the calculation results of ALU 150, and is used for sending and receiving data between each port of RAM 180. Accumulator), and 190 is
This is a system clock generation circuit that determines the execution instruction cycle time. Next, the LCD driver 200 is given by the block configuration shown in FIG.
A serial interface 270 serially connects data to and from the serial interface 295, command data 290 interrupts and decodes instructions inputted through the serial interface 295, and controls each unit according to the contents of the instruction. 280 is a character generation circuit that generates a 5×7 dot matrix pattern in response to input data;
writes data from serial interface 295 or serial interface 2
95 is a data pointer that specifies the read address of data; 250 is a character generation circuit 29;
0 output or data memory 220 for storing display data from the serial interface 295;
210 is a row driver that performs LCD row control;
The column driver 230 performs column control of the LCD.
The LCD voltage controller 240 controls the voltage to the LCD, and 240 controls the LCD drive timing.
LCD timing controller, and 260 is a system clock controller. Furthermore, the RAM 300 has the block configuration shown in FIG.
0 specifies the address of the memory array 340 by analyzing the data of the address counter 320, and the
-Y decoder, 340 is a memory array, and 350 is a control circuit. FIG. 14 shows an example of the configuration of the switching circuit 1. FIG. 15 shows the data structure of the output signal (g) to the external terminal 5, with 11 bits per character. FIG. 16 is a circuit example of level shift 3. FIG. 17 is an example of the key arrangement of the data input section. The operation of the receiver in each case will be explained below. (a) When the desired signal is received after the power is turned on.As shown in Figure 5A (), among the receivers in the BS state, the one whose ID corresponds to A1 receives SC after receiving P. When detected, the subsequent signal
Decrypt T1. At this time, the message data
Since M1 follows, Z0 is logic “1”, and
BS is canceled (turned off) during the period indicated by the BCD code of Z2 to Z5 (at least until the next SC, usually further up to A2 and T2). Furthermore, when "1000111" is received as the "MCS" pattern when decoding I1, the message data of M1 is decoded with the code corresponding to Z1, stored in the RAM 300, and sent to the LCD 90 via the LCD driver 200.
and drives the transmission means 80 via the decoder 40 and buffer 70 to notify the owner of the device that the call has been made. Also “TS” of I1
Calibrate the built-in calendar with the month and day information of the pattern. Then, the next SC, ID, T2, and I2 are detected and decoded. At this time, the SC signal is detected, but the ID signal is not detected because it is A2, so the detection pulse
DT3 will not appear. Therefore, looking only at the Z2 to Z5 of T2 and the "MCS" and "TS" patterns of I2, after detecting the signal of I2, turn on BS for the period indicated by Z2 to Z5 (usually until before the next SC) and MCS”
When the value is other than 1000111, the built-in clock is calibrated to the time corresponding to the "TS" pattern, and the reception time is added to the received and stored message. In this way, the BS is turned off again at the time of the next SC. This period is the period up to T3 because the ID is different in A3 and the built-in clock has already been calibrated. Thereafter, such operations are repeated, and when the end signal E indicating the end of data is detected, the normal BS operation is resumed. In addition, the receiver whose ID corresponds to A3 detects SC after receiving P, but since the ID does not match at A1, Z2 to Z5 of T1 and I1
Look only at the “TS” pattern. After the signal I1 is detected, the BS is turned on for a period indicated by Z2 to Z5, and the built-in calendar is calibrated on the month and day that correspond to the "TS" pattern. Thus the next SC
At time , when BS is turned off again until I2, SC will be detected but ID will not be detected.
Look only at T2's Z2-Z5 and I2's "MCS" and "TS" putters. After I2 is detected, BS is turned on for a period of Z2 to Z5 and “MCS” becomes 1000111.
Calibrate the built-in clock at the time that corresponds to the “TS” pattern. Of course, when the "MCS" pattern is 1000111, the built-in calendar is calibrated using the month and day information corresponding to the "TS" pattern. In this way, when the next SC time comes, the BS is turned off again and the SC detection operation begins. Then, when SC and ID are detected, the BS remains off for the period Z2 to Z5 at T3, and the “MCS” pattern is
If it is 1000011, the time corresponding to M3 decoded by the code corresponding to Z1 is stored, and when the built-in clock reaches the predetermined time, it drives the transmission means (alarm horn) 80 via the decoder 40 and buffer 70, A message indicating that it is a set alarm is displayed on the LCD 90 (FIG. 18 is an example of this). Also, calibrate the built-in clock again using the time information corresponding to “TS” in I3. Thereafter, when there is no ID that corresponds to A3 and the end signal E is received, normal BS operation is resumed. By the way, in this embodiment, unless the end signal E is received, the signal T is not received regardless of whether the SC is received or not.
If this signal cannot be received correctly, the BS is forcibly turned on for a predetermined period of time (approximately 1 minute in this example) and shifts to SC signal reception. normal
Return to BS operation, and if SC is not detected two or more times in a row, it is determined that there is a field failure and normal BS is activated.
By returning the device to normal operation, the battery is used more effectively and the reliability of reception is improved. (b) When the power is turned on when the desired signal arrives In Figure 5B, the receiver with ID AN is turned on and the BS is turned off continuously for a predetermined period of time (approximately 1 minute in this example). , detect the desired SC signal. When the SC signal is detected in this way, the ID is detected, but it is not received, so after I2 is detected, the built-in calendar or clock is calibrated with the "TS" information according to the "MCS" pattern, and the T2's Z2~ Turn on BS during Z5. Then, at the next SC, the operation of turning off the BS again is repeated. In this way, the ID corresponding to AN
is received, the BS is turned off for the period Z2 to Z5 of TN, and the “MCS” pattern of IN becomes 1000101.
If so, the message data MN is decoded and stored using the code corresponding to Z1 of TN. As a result, if SC is not detected before returning to BS operation and checking the elapse of time corresponding to the received data on the built-in clock, a warning will be issued to notify you that you are not in a good service area. (When detected, the timer stops and restarts when returning to BS.), and forcibly turns off the BS for a predetermined period of time (approximately 1 minute in this example) and detects the SC. conduct,
If SC is not detected within the certain period of time, the operation of returning to BS operation will be repeated. (c) Registration/reading by manual input of fixed form information Select the desired key from the mode switch of the data input section 2 (However, if you select the "CAL" or "TIME" key, the LCD 90 will operate in conjunction with the CPU and function or clock function). If you press the “TEL” key here, the 9th
An interrupt is applied from the K terminal of interrupt port 107 in the figure, and “TEL” is sent from input port 102.
The pattern corresponding to the key is input. As a result, the CPU recognizes that the device is set to "TEL" mode, and from now on, data from the input port 103, for example "DATAIN", "AOKI"
“DATAIN”, “NEC”, “DATAIN”, “03−
262−5174” “DATAIN”, “KUDO”,
“DATAIN”, “SONY”, etc. are input.
When the result of key input is recognized in this way, it is read out according to the predetermined format (see Table 5), and when the “DATAOUT” key is pressed first, “AOKI” is displayed on the LCD, and then “→ ” key will display “NEC”, further pressing the “→” key will display “03-262-5174”, further pressing the “→” key will display “KUDO”, then pressing the “↓” key will display “ENDO” , "KDD" with the "→" key and "SONY" with the "↓" key. Similarly, when the "MEMO" key is pressed, an interrupt is generated from the K terminal of the interrupt port 107 in FIG. 9, and the pattern "0010011" corresponding to the "MEMO" key is input from the input port 102. As a result, the CPU determines that the device is set to “MEMO” mode, and from now on input port 103
The following data input from [“DATAIN”, “FEB.10.1984 SCHEDULE”,
“DATAIN”, “9:00” “DATAIN”,
“MEETING (NEW PRODUCT) AT5-1”,
When you press the “DATA OUT” key to read “DATAIN”, “10:30”, …], “FEB.10.1984” will be displayed on the LCD 90 as shown in Table 6.
"SCHEDULE" is displayed, press the "→" key, the LCD display changes to "9:00", and then press the "→" key.
When you press the key, the display will change to “MEETING (NEW)”.
PRODUCT) AT5-1", and then press the "↓" key to change to "TEL (NTT MR KUDO)", and you can check the necessary information at any time with a simple operation instead of a memo pad. Since the machine has a built-in calendar and a built-in clock, the receiver's transmission device (for example, alarm horn) is activated at the dates of "9:00", "10:30", etc. of "FEB.10" to alert you. At the same time, a display corresponding to the sounding time is displayed on the LCD 90. For example, 18:00
If so, "GINZA (MORE)" will be displayed on the LCD. (d) Registration of fixed form information by radio The operation of the receiver will be explained using FIGS. 1, 9, 12, and 3. When the switching circuit 1 receives the preamble signal P while the voltage is being applied to the radio unit 20 and waveform shaping circuit 30 of the receiver operating BS, the preamble signal SC
BS is turned off for a period long enough to detect. If SC is detected during this period, one chip is sent via the interrupt port 107 with the detection pulse DS2.
When the CPU 100 is activated, the decoder 40
moves to ID detection operation. That is, starting from the detection of the SC, the received data is compared bit by bit with the data in the PROM 50 in which the ID number of the own machine is written (Fig. 7), and when a match is confirmed, the 1 chip CPU100 via input port 121 with detection pulse DT3
A clock CL corresponding to the transmission speed is supplied from the input port 105. At this time, a predetermined period of time from the interrupt activation by DT2 (time until DT3 is detected)
If DT3 is input later, it is determined that the ID has been detected, and if not, it is determined that the ID does not match, and preparations are made to receive the subsequent signal. As a result, the 1-chip CPU 100 reads the message signal D from the input port 106 using the clock CL, and
The predetermined contents of the program memory 140 are translated by an instruction decoder 160 and processed in accordance with each instruction. That is, the read signal is transmitted to the data bus 120, ACC1
The data is written to RAM 180 via 70. In this way, each time the 31 bits forming the BCH31, 21 code are input, the ALU 150 performs an operation and decodes the received signal. 1 chip CPU 100 is the first decrypted
The 20 information bits of the BCH31 and BCH21 codes are decoded according to FIG. 4, and thereafter the BS operation of the receiver is controlled via the output port 112. At this time, if the 20-bit information bits have the following pattern, ``110100000000000100000'', the call is with a message, the message data is composed of 7 bits, and there are at least 20 words (here 1
(31 bits) indicates that BS must be cleared. Then, it waits for the next 31 bits to be input and codes the signal I. The 20-bit information area is thus analyzed according to Tables 1 and 2 in FIG. That is, if the information bit has the following pattern, "110001100101000100000", it indicates that the subsequent message data will be processed in the telephone directory mode, and the data transmission time is AM10:
Indicates 20 minutes. Subsequent messages are processed in accordance with the control contents decoded in this way. Therefore, the information area (20 bits of data) decoded in units of 31 bits is decoded in units of 7 bits and sequentially stored in the external RAM 300. In other words, chip select 1 is set to logic “0”
By setting the level, the RAM 300 is set to operation mode, and the address of the RAM 300 to be opened is determined via the serial interface 108.
The corresponding address information is transferred via the signal line SO.
At this time, the 1-chip CPU 100 sends the system clock to the RAM 300 and at the same time sets the signal line A/ to logic "1" level to indicate an address. And at this time the 13th
In the figure, the RAM 300 determines that the signal input from the signal line SO is an address signal according to each input control signal (, A/, R/), and sends the signal via the address counter 320 and the X/Y decoder 330. The address to write to in memory array 340 is specified. Next, in the 1-chip CPU 100, the message data to be written is sent to the serial interface 1.
08 signal line SO, signal line A/ is set to logic "0" level to indicate that the data to be sent is message data, and signal line R/ is set to logic "0" level to instruct writing. . As a result, RAM30 in Figure 13
0 writes the data input via the signal line SO as message data to the previously designated address of the memory array 340 via the XY decoder 330 in response to each input control signal. When message data is sequentially decoded in the above process, if SC or end code is detected in BCH31, BCH21 unit, or if two consecutive words cannot be received, 1 chip CPU1
00 determines that the message data has ended, and notifies the decoder 40 through the signal line ME from the output port 110 that the message has ended, and also generates a sound from the decoder 40 through the signal line AC through the output port 111. Drive the circuit. As a result, the alarm horn 80 sounds via the buffer 70 as a signal (d). Here, in the case of SC detection, the 1-chip CPU 100 repeats the same operation as described above, but when the end code is received or when two consecutive words are not received, the receiver returns to the BS operation. As described above, a code corresponding to the desired content is input to the receiver as a normal message. Next, to read the data received and stored in this way, by pressing the read switch S1, the 1-chip CPU 100 reads the first address information of the corresponding message data from the signal line SO.
At the same time, the chip enable signal line 1 is set to a logic "0" level, and the chip select signal line 1 (this is a signal line for selecting the LCD driver 200) and signal line A/ are set to a logic "1" level. ``Level. Next, the signal line A/ is set to the logic "0" level, and the signal line R/ is set to the logic "1" level. As a result, data corresponding to the above-mentioned first address is sent to the X/Y decoder 330 in 1-byte units.
The data is read out from the memory array 340 via the serial interface 310 and sent to the one-chip CPU 10 via the signal line SI.
0. When the data is read from the RAM 300 and supplied to the 1-chip CPU 100, the signal line 1 and the signal line C/ are set to logic "1" level, and the chip select signal line 2 is set to the logic "1" level to select the LCD driver 200. By setting the logic to the "0" level, character conversion instructions and storage address information are supplied to the LCD driver 200 from the signal line SO. Next, the 1-chip CPU 100 sets the signal line C/ to the logic "0" level.
Data read from RAM 300 is supplied to LCD driver 200 via signal line SO. As a result, in the LCD driver 200 shown in FIG.
When the signal line C/ is at the logic "1" level, the information serial-to-parallel converted is decoded by the command decoder 270, and the command data 270 generates an internal control signal. Here, if the command is a write command or a character conversion command, the data pointer 280 is accessed to set the write address,
When the signal line C/ reaches the logic “0” level,
The data input via the serial interface 295 is processed by the character generation circuit 290 by 5×
7 is converted into a dot matrix pattern and written to the data memory 250, and is also written to the column driver 210 and row driver 2 under the control of the LCD timing controller 240.
20 and is displayed on the LCD 90 as a signal C. (e) Registration/change of common ID The operation of the receiver will be explained using FIGS. 3, 10, and 11. FIG. 3 shows a partially modified configuration between the decoder 40 and the message processing unit 60 (the configuration example of the one-chip CPU 100 is shown in FIG. 11) in FIG. In this example, a one-chip CPU is used and its configuration is shown in FIG. Now, when voltage is applied to the radio section 20 and waveform shaping circuit 30 of the receiver that is in BS operation in the switching circuit 1, the preamble signal P
When receiving SC, the BS operation is stopped for a period sufficient to detect a subsequent predetermined synchronization signal SC. If an SC is detected during this period, the detection pulse DT2 activates the 1-chip CPU 100 and the decoder 8 via the interrupt port 107, and the decoder 40 starts writing the individual selective call number of its own machine using the detection of the SC as a starting point. The data in the P-ROM 50 and the received data are compared bit by bit. In this way, if the received data matches the individual calling number of the own device in the PROM 50, the detection signal DT3 is transmitted to the input port 121 in FIG.
Input from As a result, SC detection pulse DT2
The CPU that was activated in Prepare for reception. In other words, in the 1-chip CPU 100, the signal following the ID is sent to the input port 106 using the clock CL.
The data is read from the data bus 120 and written to the RAM 180 via the accumulator ACC 170. In this way, BCH31,21 codes are formed.
ALU15 every time 31 bits of data is input
Performs calculations with 0 and decodes the received signal.
Of the 31 decoded bits, 20 information bits are decoded according to FIG. 4, and thereafter the BS operation of the receiver is controlled via the output port 112. At this time, if the 20-bit information bits have a pattern such as "110100000 0000 0011 0010", it indicates that the call has message information consisting of a 7-bit code afterward, and also indicates that the 20-bit information bit has a pattern such as "110100000 0000 0011 0010". Indicates that BS operation needs to be canceled. That is, 1
The chip CPU 100 sets and starts a 32-word timer. Then, it waits for the next 31 bits to be input and outputs the signal I.
Performs decoding. The 20-bit information area thus obtained is analyzed according to FIG. 4 and Tables 1 and 2. In other words, if the information bit has a pattern like "11000 0011 0010 0011 0110", it will be common to the following message data.
It is registered as an ID, and the current time is
PM2: means 36 minutes. Therefore, the built-in clock of the 1-chip CPU 100 is calibrated, and the subsequent message data is
It is decoded every 31 bits, and 20 of them are decoded into 7-bit units. Here, if the pattern of the 20-bit information area of the received message is as follows, then according to Table 3,

【table】 〓

Claims (1)

[Scope of Claims] 1. In a radio selective calling receiver having a battery saving (BS) function, a predetermined first
Normal BS after continuous power supply for a period of
means for performing the operation, and displaying a warning when a predetermined first signal is not detected in a predetermined second period after the start of the BS operation, and continuously supplying power for a predetermined third period. 1. A radio selective calling receiver which achieves a reduction in the proportion of unreceived calls, characterized by comprising means for reducing the number of unreceived calls. 2. In the receiver according to item 2 above, the second period can be set to a required period according to a predetermined second signal in order to adapt to the requirements of the applied system. A wireless selective calling receiver that is characterized by a reduction in the rate of unreceived calls.