JPH09218846A - Bus converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the degradation of system performance by integrating data, converting the data into the data of a low speed bus, storing the data in an FIFO storage device, taking out the data in the order of a bus cycle and processing the data. SOLUTION: The data corresponding to the N bus cycle on a system bus is converted into the data corresponding to the one bus cycle of a low speed part 9 in a speed conversion part 5. The data is written as a signal group 14 in a reception FIFO 11 by a reception FIFO writing control part 10. A transaction processing part 12 controls the reading signal for the reception FIFO 11, takes out data in order from the reception FIFO 11 and processes the data. The data stored in a flip flop array 13 after the process is transmitted as a signal group 15 to a high-speed part 2 and is outputted to the system bus via a data bus part 7 and an I/O buffer 3. Since the data corresponding to the N bus cycle of a high-speed bus is transmitted collectively to the low-speed part, the system bus can efficiently be used.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to, in a data processing device, between a system bus connected to a processor operating at a high frequency and an input / output bus connected to a processor operating at a low frequency. Related to the transaction data transmission / reception method.

[0002]

2. Description of the Related Art FIG. 11 is a diagram showing a general configuration of a conventional system in which a central processing unit (hereinafter referred to as CPU) and a storage control unit (hereinafter referred to as memory controller) are connected to a system bus. Is. In the figure, 101 is a CPU, 102 is a memory controller, 103 is an input / output control device (hereinafter referred to as I / O controller), 104
Is a system bus, 105 is a storage device (hereinafter referred to as memory), 6 is a memory bus, and 7 is an input / output bus (hereinafter, I / O bus).
The I / O bus 107 is connected to an input / output device (hereinafter referred to as an I / O device).

In FIG. 12, the memory controller 102 or I / O controller 03 shown in FIG. 11 is used as the system bus 104 and the memory bus 106 or I / O bus 107.
FIG. 3 is a block diagram showing a configuration of a bus interface unit 108 that controls an interface with (hereinafter, the memory bus 106 or the I / O bus 107 is referred to as a downstream bus). In the figure, a bus interface unit 108 is an interface unit 108a that interfaces with the system bus 104, and a data bus and main unit 1 that transfers data between the buses and controls the entire bus interface unit 108.
08b, a downstream bus interface unit 108c, and a clock driver unit 108d that distributes a clock inside the bus interface unit 108.

The operation will be described below with reference to the drawings. When the CPU 101 accesses the memory 105 or the I / O device, the CPU 101 performs arbitration according to the protocol defined by the system bus 104 and issues a transaction to the system bus 4 when the bus usage right is acquired. The issued transaction is received by the memory controller 102 or the I / O controller 103 according to its type and address. Inside the controller that received the transaction (memory controller 102 or I /
In the O controller 103), this transaction is sent to the data bus and main unit 108b via the system bus interface unit 8a, and the processing content is analyzed.
If the transaction is a write system, the address and the subsequent data are sent to the downstream device via the downstream bus interface 108c together with the control signal. If the transaction is a read system, the address and control signal are similarly sent to the downstream device. The data returned from the I / O device passes through the inside of the controller in the opposite direction of the transaction and is transferred to the C bus via the system bus 104.
Reach PU 101.

[0005]

Since the conventional smeller is constructed as described above, the system does not operate properly unless the frequency of the system bus is equal to the operating frequency of the entire controller. However, in recent years, the operating frequency of the CPU has become extremely high, but in order to make a controller LSI that operates at the same frequency as that, full custom or a method close to it must be applied to the entire chip, The design period and development cost will be large. On the other hand, it is impossible to realize an LSI that operates at the same speed as a CPU by using a gate array method that has a short design period and is relatively low in cost. Therefore, in the latter case, the frequency of the system bus is set lower than the internal frequency of the CPU, and the system performance is
It does not bring out the full performance of. As described above, the conventional method has a problem that either the design period / cost or the system performance must be sacrificed.

In order to solve the above problems, the present invention aims at designing most of the controller LSIs by using a gate array technique and nevertheless minimizing the deterioration of system performance. There is.

[0007]

SUMMARY OF THE INVENTION A bus converter according to the present invention has an interface with a system bus operating at a high-speed frequency, and has an operating frequency of 1 /
And an interface with a low speed bus operating at N,
A speed conversion unit that collectively converts data for N bus cycles of the system bus into data of one bus cycle of the low speed bus, a FIFO storage device that stores the data converted by the speed conversion unit, and this FIFO storage And a processing unit for extracting and processing the data stored in the device in the order of the bus cycle output to the system bus.

Further, the FIFO storage device is provided with means for judging the validity of the bus data sent from the speed conversion section, and only the data of the valid bus cycle is stored.

Further, the processing unit is adapted to read data of a plurality of bus cycles from the FIFO storage device at the same time.

Further, the system bus is constructed by a bus having a common address line and data line, the processing section has a data analysis section, and based on an analysis result of the data analysis section, the FIFO storage device outputs the data. The number of bus cycles of data to be read is determined.

Further, the speed conversion section holds a (N-1) stage flip-flop which holds bus data for (N-1) bus cycles driven at a high frequency, an input data and the (N-1) stage flip-flop. 1) N flip-flops which are driven at a frequency of 1 / N of the high-speed frequency with each output of each flip-flop as an input.

Further, the speed conversion unit receives the counter which operates at a high frequency, the N flip-flops whose drive inputs are controlled by the output of the counter, and the outputs of the N flip-flops as inputs. It is configured by N flip-flops operating at a frequency of 1 / N of the high-speed frequency.

Further, a storage device for storing the data processed by the processing unit is provided, and the number of data that can be read at one time from this storage device is equal to the maximum number of bus cycles that can be sent to the system bus in one arbitration. In the above configuration, a data path unit is provided for taking out the read data one bus cycle at a time by the selector and continuously sending the read data to the system bus for a required number of cycles.

Further, the number of data that can be read from the storage device at one time is set to N bus cycle of the system bus.

Further, the data path unit is configured to send to the system bus data corresponding to the number of bus cycles sent in advance from the storage device.

Further, the storage device is constituted by a flip-flop array.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. 1 to 6 are views for explaining an embodiment of a bus conversion device according to the present invention. FIG. 1 is a diagram showing a configuration of a bus converter connected to a system bus in the system shown in FIG. 11, in which 1 is the entire bus converter and 2 is the same as the system bus inside the bus converter 1. High-speed unit operating at speed (clock frequency), 3 is an I / O buffer group connected to the system bus, 4 is a signal group for one cycle of the system bus (for example, n bits), and 5 is from the high-speed unit 2 to be described later. , A speed conversion unit that converts a frequency to a low speed unit and transfers a signal, 6 is a control unit that controls the entire high speed unit 2, 7 is a data path, 8 is a signal for one cycle output to the system bus, and 9 is a transaction A low speed part for actually performing the processing, 10 is a write control part for writing a signal of the system bus to the FIFO storage device, 11
Is a reception FIFO for storing system bus signals
An O storage device (hereinafter referred to as a reception FIFO), 12 is a transaction processing unit that interfaces with a downstream bus to perform transaction processing, and 13 is a flip-flop array for transferring the data generated by the transaction processing unit 12 to a high-speed unit. , 14 are signal groups (N * n bits) for N cycles of the system bus transferred from the speed conversion unit 5 to the low speed unit 9 in synchronization with the clock of the low speed unit, and 15 is a flip-flop array provided in the flip-flop array 13. Are all output signal groups of the group.

FIG. 2 is a diagram showing an example of a clock supplied to the bus conversion device 1, FIG. 3 is a diagram showing the structure of one bit (on the system bus) of the speed conversion unit 5, and FIG. 4 is this speed conversion. FIG. 5 is a timing chart showing the operation of the unit 5. FIG. 5 is a reception FIFO storing the data converted by the speed conversion unit 5.
FIG. 6 is a diagram showing the configuration of (First In First Out) 11, and FIG. 6 is a flip-flop array 1 of the low-speed section 9.
3 is a diagram showing a circuit for sending out the data held by 3 to the high speed unit 2. FIG.

The first embodiment will be described below with reference to the drawings.
Will be described. Two kinds of clocks as shown in FIG. 2 are supplied to the bus conversion device 1. That is, the high speed unit 2 has a clock (CK) having the same frequency as the system bus.
1) is supplied to the speed conversion unit 5 of the low speed unit 9 and the high speed unit 2 at a frequency of 1 / N (N = 2 in the example of FIG. 2) of the frequency of the clock of the system bus, and a clock with a uniform rising edge ( CK2) is supplied.

Next, the operation of the speed converter 5 will be described with reference to FIGS. 3 and 4. In the example shown in the figure, the frequency of the clock CK2 of the low speed section 9 is set to 1/4 of the frequency of the clock CK1 of the high speed section 2. In FIG. 3, 20 (20
(1) to 20 (3), 20 (11) to 20 (14)) are flip-flops, 21-27 are each flip-flops 2
0 output. Data on the system bus (DATA)
Is synchronized with the high-speed clock CK1 using the three-stage flip-flops 20 (1) to 20 (3), and the final-stage flip-flops 20 (11) to 20 (14) use data (DATA) on the system bus. ), The outputs (21 to 23) of the flip-flops 20 (1) to 20 (3) at the respective stages are synchronized with the low-speed clock CK2, and OUT1 (24) to OU are synchronized.
Obtain T4 (27). Thus, N on the system bus
(N = 4 in the example in the figure) A signal for a bus cycle (4 clocks) is taken out as a signal for one bus cycle in the low-speed section. FIG. 4 shows a timing chart of the operation of the speed conversion unit 5.

Data for N bus cycles (1 bus cycle: n bits) on the system bus is converted by the speed conversion unit 5 into data (N * n bits) for 1 bus cycle of the low speed unit 9, and a signal group is generated. Receive as 14 Receive F in FIFO 11
It is written under the control of the IFO write control unit 10.
Referring to FIG. 5, the data of the first bus cycle out of the data of N bus cycles on the system bus is in
The data of the second bus cycle is received in the receive FIFO 11 (1) as data1, and the receive FIFO is received as in data2.
Similarly, the data of the Nth bus cycle is transferred to the reception FIFO 11 (N) in O11 (2) as in dataN.
Written at the same time.

As described above, the transaction issued to the bus conversion device 1 on the system bus is taken into the bus conversion device 1 via the I / O buffer 3 of the high speed section 2. The fetched transaction is transferred to the low-speed section 9 as a signal group 14 in which the signals for N cycles including the cycle in which the transaction is issued are combined into a signal for one bus cycle of the low-speed section 9 by the speed conversion section 5. .

The signals for N cycles of the system bus transferred to the low-speed section 9 are received by the write control section 10 in accordance with instructions from the reception FIFO 11 (1) to the reception FIFO 11 shown in FIG.
11 (N) is written. In the case of this example, the write control unit 10 makes the write signal significant when empty entries remain in all the reception FIFOs 11 in FIG. As a matter of course, if there is no empty entry in at least one reception FIFO 11, the bus conversion device 1
The system is controlled so that issuance of transactions to is suppressed.

In the transaction processing unit 12, the reception F
The read signal to the IFO 11 is controlled to sequentially take out the data (transaction) from the reception FIFO 11 for processing. When one process is completed, the reception FIFO
One entry of O11 is read and a new process is started. The signals of the system bus held in the N sets of reception FIFOs 11 shown in FIG. 5 are in the order in which they appear on the system bus, that is, the reception FIFO 11 (1) and the reception FIFO 11
In the order of (2), read signals read1, read2,
..., readn is issued and the entries are read one by one.

The transaction processing unit 12 sequentially receives F
The data read from the IFO 11 is processed by the transaction processing unit 12 itself or passed to a device connected to a downstream bus, and the processing result processed by the device is passed to the transaction processing unit 12 again. , Are stored in the flip-flop array 13. The data stored in the flip-flop array 13 is passed to the high speed unit 2 as a signal group 15, and is output to the system bus via the data path unit 7 of the high speed unit 2 and the I / O buffer 3. FIG.
FIG. 3 is a diagram showing a configuration in which the output of the flip-flop array 13 is converted into a signal to the system bus in the data path unit 7. In the figure, 30 is the output of the flip-flop array 13, 31 is a selector provided in the high speed unit, Reference numeral 32 is a flip-flop that synchronizes the output of the selector 31 with the clock CK1 of the system bus, and 33 is a selection signal of the selector 31.

The data transfer from the low speed unit 9 to the high speed unit 2 will be described in more detail below. For example, when the transaction received from the system bus via the high speed unit 2 by the low speed unit 9 is a transaction for reading from the downstream bus, the transaction processing unit (downstream bus interface) 12 fetches necessary data from the downstream bus. All the data fetched from the downstream bus is stored in the flip-flop array 13 in the fetched order. Since the flip-flop array 13 is driven by the clock CK2 of the low speed unit 9, if one entry (data for one cycle to be sent to the bus) is taken out and transferred to the high speed unit 2, it will be sent to the system bus in consecutive cycles. Can not do it. Therefore, all the contents of the flip-flop array 13 are directly connected to the high speed section 2 as the signal group 15. In the selector 31 or the three-state buffer provided in the data path unit 7 of the high speed unit 2,
The necessary entry is switched for each clock CK1 of the high speed section 2 and taken out, and sent out to the system bus. That is, one F is included in the flip-flop array 13 of the low-speed section 9 and the section for reading the output of the flip-flop array 13 of the high-speed section 2.
It functions as an IFO storage device. The high-speed section 2 starts reading after the signal group 15 is sufficiently stable. The number of entries in the flip-flop array 13 is prepared for the maximum number of cycles that can be sent to the bus in one arbitration.

Flip-flop array 13 in high speed section 2
The data held by is read out as follows. When the transaction processing unit (downstream bus interface) 12 finishes storing data in all of the flip-flop arrays 13, the low speed unit 9 reports a signal indicating the end of storage to the high speed unit 2. In response to this, the control unit 6 of the high speed unit 2 performs arbitration for the system bus, and when the system bus is acquired, the contents of the flip-flop array 13 are sent to the system bus as described above. The data is sent in consecutive system bus cycles until there is no more data to send. Although not shown in the figure, the control unit 6 is provided with a means for detecting that the FIFO storage device formed across the low speed unit 9 and the high speed unit 2 is empty.

As described above, data can be transmitted to the system bus in consecutive cycles of the high-speed system bus clock without inserting an idle cycle.

In the first embodiment, the size of the flip-flop array 13 is set to be larger than N cycles of the system bus. However, the size of the flip-flop array 13 is N of the system bus.
The same effect can be obtained even if the number of cycles is suppressed.
The operation at this time is as follows. When a read access is started from the transaction processing unit (downstream bus interface) 12 to the downstream bus, an arbitration request signal is transmitted from the low speed unit 9 to the high speed unit 2. Of the data to be sent to the bus, a read start signal is reported from the low speed unit 9 to the high speed unit 2 so that the high speed unit 2 starts reading at the timing when N cycles worth of data is written in the flip-flop array 13. . It is assumed that the system bus has been acquired by this time after the arbitration request signal is issued. If the system bus is acquired earlier than this time, the high-speed section 2 issues an idle cycle to the system bus until the read start signal is received. The low speed section 9 writes the next N cycles of data to the flip-flop array 13 at the clock of the next low speed section 9. At this time, since the reading of the data for the previous N cycles has just ended, the high-speed unit 2 repeats reading the data for the first one cycle in sequence and sending the data to the system bus. This operation is repeated until the data for the last N cycles is reached. The last N cycles worth of data is notified by the control signal transmitted from the low speed part to the high speed part. If the number of cycles of valid data to be sent to the bus is not a multiple of N, the contents of the idle cycle are written in the remaining entries for the last N cycles of data.

As described above, according to the first embodiment, data for N bus cycles of the high-speed bus are collected,
Since the data is sent to the low speed part, the system bus can be used efficiently. Further, since the flip-flop array for holding the result processed by the low-speed part is provided and the data is sequentially transmitted at the frequency of the system bus, the efficiency of use of the system bus when transmitting the data to the system bus is not impaired. Can be

Embodiment 2 The second embodiment is a modification of the configuration of the reception FIFO 11 in the first embodiment. FIG. 7 is a diagram showing the configuration of the reception FIFO in the second embodiment. As is clear from comparison with FIG. 5 described in the first embodiment, the write control signal (write) of each reception FIFO is independent. It is characterized by this. That is, the data from the speed conversion unit 5 can be written or not written for each reception FIFO. That is, in the second embodiment, of the data on the system bus, only the data valid for the bus conversion device 1 is fetched into the reception FIFO 11.

The operation of the second embodiment will be described below. The operation is the same as that of the first embodiment until a transaction is issued on the system bus and data is transferred to the low speed section 9 of the bus conversion device 1.
The signals for N cycles of the system bus transferred to the low speed unit 9 are written in the reception FIFO 11 shown in FIG. 7 according to the instruction of the write control unit 10. However, the write control unit 10 receives the reception FIFO for each signal of N cycles based on the result of the valid bit of the signal of the system bus, the type of transaction, the address decoding and the like.
11 It is judged whether or not the data should be stored in the memory device, and as a result of the judgment, the write control signals (enableX: X = 1, 2, ...
n) is generated and transmitted to the reception FIFO 11. In addition,
Although not shown in the figure, if the number of empty entries in the reception FIFO 11 is less than N entries, the bus conversion device 1
The system is controlled so that issuance of transactions to is suppressed. Although a maximum of N sets of data can be simultaneously written to the reception FIFO 11, writing is performed such that the data that appears on the bus earlier is read first when reading. The transaction processing unit 12 receives the reception FIFO when one process is completed.
If valid data is reserved in O11 (that is, it is not empty), the next one entry is read and a new process is started. Subsequent operations are the same as those in the first embodiment.

As described above, according to the second embodiment, the data of the bus cycle unnecessary for the local system is received.
Since it is not taken into the IFO, extra processing is not performed in the low speed section, and the processing efficiency is improved.

Embodiment 3. In the second embodiment,
A write control signal to the reception FIFO 11 is provided for each of N sets of input signals of the system bus, that is, N cycle input signals, and only valid signals are received in the FIFO 1
Although the data is stored in 1, the data is sequentially read from the reception FIFO 11 one bus cycle at a time. However, in the third embodiment, the read from the reception FIFO 11 is read according to an instruction from the side (transaction processing unit 12). This is different from the second embodiment in that a maximum of M sets of data (where M is equal to or smaller than N) can be read at one time. That is, in the third embodiment, read1, read2, ..., Re shown in FIG.
A plurality of signals of adn are driven simultaneously.

The operation of the third embodiment will be described. The operation until a transaction is issued to the system bus and it is written in the reception FIFO 11 is the same as the operation in the second embodiment. The operation thereafter is variable depending on the configuration of the bus conversion device 1.
The reception FIFO 11 storage device shown in FIG.
Since a set of data can be written and a maximum of M sets of data can be read (this can be realized by a shift register capable of shifting any bit from 0 to M at a time), the transaction processing unit 12 It is possible to simultaneously process a plurality of entries without fixing the processing unit of (1) to a signal for one entry of the reception FIFO 11. For example, if two sets of read transaction processing circuits are prepared in the transaction processing unit 12, by connecting the first entry and the second entry of the reception FIFO 11 to the two processing circuits, the read transaction is applied to both entries. If is held, two entries can be processed at once. At this time, the data (or pointer) of the reception FIFO 11 advances by two entries at once, and the contents of the third entry appear in the first entry. Transaction processing unit 1
In 2, if valid data is held in the reception FIFO 11 (that is, if it is not empty) after one process is completed, the next entry is read and a new process is started. The subsequent processing is the same as the operation in the first embodiment.

As described above, according to the third embodiment, since the data in the reception FIFO can be read at once, the processing efficiency in the low speed section is improved.

Fourth Embodiment 8 and 9 are diagrams for explaining a fourth embodiment of the bus conversion device according to the present invention. The fourth embodiment shows a detailed embodiment of the transaction processing unit in the third embodiment. FIG. 8 is a diagram showing a configuration for extracting transaction data from the reception FIFO 11. In the figure, 11 is the reception FIFO described in the third embodiment, and in this example, N = 2 for simplification of description. Reference numerals 40 and 41 are output signals of the first two entries of the reception FIFO 11, 42 is a transaction analysis circuit for analyzing a transaction issued to the system bus, 43 and 44 are registers for holding the output signals 40 and 41, respectively. Is a status signal (control signal) output from the transaction analysis circuit 42, and 46 and 47 are control signals for notifying the reception FIFO 11 of the number of read entries. FIG. 9 shows how the data stored in the reception FIFO 11 is processed by the operation in the fourth embodiment.

The fourth embodiment is intended to efficiently process a transaction on a high-speed bus in which an address line and a data line are common by a low-speed section 9 with a relatively small-scale circuit. As a system bus transaction, read-only 1
It is assumed that the cycle / write system consists of an address of 1 cycle and data of 4 cycles following it. In order to process the transaction efficiently by the low-speed section 9, it is preferable to prepare a plurality of transaction analysis circuits 42, a plurality of processing sections, and the like, but if this is done, the circuit becomes complicated and large-scaled. Then, the transaction analysis circuit 42 is connected only to the output of the first entry of the reception FIFO 11.

The operation of the fourth embodiment will be described below with reference to the drawings. The transaction analysis circuit 42 changes the control signals 46 and 47 according to the analysis result to control whether the content of the reception FIFO 11 is advanced by one entry or two entries, or not advanced at all. 1 if the output signal 40 of the first entry is an address
The entry is advanced and the output of the register 43 is passed to the transaction processing unit 12 as an address. At this time, the transaction processing unit 12 ignores the contents of the register 44. If the output signal 40 of the first entry is the data part of the write-related transaction, the contents of the reception FIFO 11 storage device are advanced by two entries, and the outputs of the registers 43 and 44 are both used as write data for the transaction processing part 1.
Hand over to 2. If the transaction processing unit 12 is processing the previous transaction or the reception FIFO 11 storage device is empty, both the control signals 46 and 47 are made insignificant.
9A to 9D, when one read-type transaction and one write-type transaction are sequentially stored in the reception FIFO 11, the contents of the reception FIFO 11 are changed by the operation in the fourth embodiment. It shows how it goes.

As described above, according to the fourth embodiment, since the circuit for analyzing the transaction in which each head entry of the reception FIFO is stored is provided, the data can be efficiently extracted from the reception FIFO. Therefore, the processing efficiency of the low speed part can be improved.

Embodiment 5. FIG. 10 is a diagram showing another embodiment of the present invention, and is a diagram showing another configuration of the speed conversion unit 5 described in the first embodiment. The speed conversion unit in the fifth embodiment uses the system bus signal (DAT).
N flip-flops 20 having A) as a common input
(20 (1) to 20 (N)) and the output of these N flip-flops 20 as input, and the clock C of the low speed unit 9
N flip-flops 20 operating in synchronization with K2
(20 (11) to 20 (1N)) and the clock CK1 of the high-speed section 2 are input, and N-bit select signals (S ₁ , S
₂ , ..., S _N ) and a counter CNT48 that makes only one signal significant, and N-bit select signals (S ₁ , S ₂ ,
, S _N ) to select the output of the clock CK1 of the high-speed section 2 by N gates 50 (G ₁ , G ₂ , ..., G)
_N ).

The operation of the speed converter in the fifth embodiment will be described below with reference to the drawings. It is the same as in the first embodiment until a transaction is issued to the system bus and a signal reaches the speed conversion unit of the bus conversion device 1. In the speed conversion unit configured as shown in FIG. 10, the signal DATA of the system bus is input by N flip-flops 20 (1) to 20 (N). At this time, the clock CK1 of the high speed unit 2 is taken. Select signal (S ₁ , S ₂ , ...
.., S _N ) only one (eg, S ₁ ) becomes significant, and _{one of} the gates 50 (G ₁ , G ₂ , ..., _GN ) that outputs the logical product of each select signal and CK1 Only one (eg, G ₁ ) outputs the clock CK1 for the high speed section 2.
The flip-flop 20 in which the clock CK1 of the selected high-speed section 2 receives the system bus signal DATA
Only one of (1) to 20 (N) (for example, 20 (1)) is supplied to set the system bus signal DATA.

Further, in the counter CNT48, the select signal is changed from S ₁ → S ₂ → ... by the clock CK1 of the high speed section.
・ → S _x → S (x + 1) → ・ ・ ・ → S _N → S ₁ → S ₂・
.. are significant in this order, and the system bus signal DATA is sequentially set in the flip-flop 20. The output of the flip-flop 20 that sequentially takes in the signals of the system bus is set to the flip-flops 20 (11) to 20 (1N) that operate in synchronization with the clock CK2 of the low speed unit 9. The clock CK2 of the low speed part 9 and the clock CK1 of the high speed part 2 are as shown in FIG.
Since the rising edge is aligned with the clock CK2 of the low-speed section 9 once every N cycles of, the signal that sequentially takes in the signal DATA of the system bus synchronizes the signal DATA of the system bus for N cycles in synchronization with the clock CK2 of the low-speed section 9. Output all at once. The subsequent operation is similar to that of the first embodiment.

As described above, according to the fifth embodiment, since the counter is used in the speed converter and the clock signal of the flip-flop is gated by the output of this counter, the signal of the system bus is monitored. Since it is easy to gate the signal of the bus cycle which is not valid, it is possible to simplify the circuit scale rather than monitoring the validity of the bus data when storing it in the reception FIFO memory device. it can.

In the above embodiment, the flip-flop array is used as the data buffer for storing the result processed by the low speed part, but there is no problem even if it is replaced with another storage device having the same function. Absent.

It is also possible that the low-speed section notifies the high-speed section of the number of bus cycles to be sent to the system bus in advance, and the high-speed section can operate so as to send the number of cycles. By doing so, there is an advantage that the idle cycle inserted when the number of cycles of the transmission data is not a multiple of N becomes unnecessary.

[0047]

As described above, according to the present invention, the data for N bus cycles of the high-speed bus is collected and sent to the low-speed section, so that the system bus can be used efficiently.

Further, in the reception FIFO, only the data valid on the device itself out of the data on the system bus is stored, so that unnecessary data is not taken into the processing section, and the processing efficiency is improved. improves.

Further, since the data for N bus cycles on the system bus can be read at one time from the reception FIFO, the processing efficiency of the bus conversion device can be further improved.

Further, since the circuit for analyzing the transaction in which each head entry of the reception FIFO is stored is provided, the data can be efficiently extracted from the reception FIFO, so that the processing efficiency of the low speed part is improved. You can

Further, when the speed conversion unit is an N-1 stage flip-flop and the value of N is small, the circuit configuration can be simplified.

Further, since the counter is used in the speed conversion unit and the clock signal of the flip-flop is gated by the output of this counter, the system bus signal is monitored and the signal of the bus cycle which is not effective is gated. Since it can be easily applied, the circuit scale can be made simpler than monitoring the validity of the bus data when storing it in the reception FIFO storage device.

Further, a storage device for storing data to be processed on the low-speed bus side and sent to the system bus is provided, and data of the maximum number of bus cycles which can be sent to the system bus can be taken out from this storage device by one arbitration. With such a configuration, the high-speed clock is used to send data to the system bus for each bus cycle. Therefore, it is possible to prevent the use efficiency of the system bus when sending data to the system bus from being impaired.

Since the number of data that can be read at one time is set to N cycles of the system bus in the memory device configuration,
The number of signal lines can be reduced and the circuit configuration can be simplified.

Further, since the number of cycles to be sent to the system bus is set in advance and the data for the required number of cycles is taken out from the storage device, when the number of cycles to be sent to the system bus is not a multiple of N, the system The idle cycle inserted by the bus can be eliminated.

Further, since the memory device is constituted by the flip-flop array, it can be constituted by a simple circuit.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of a bus conversion device according to the present invention.

FIG. 2 is a diagram showing a relationship between clocks respectively supplied to a high speed part and a low speed part of the bus conversion device.

FIG. 3 is a diagram showing a configuration of a speed conversion unit.

FIG. 4 is a timing chart showing the operation of the speed conversion unit.

FIG. 5 is a diagram showing a configuration of a reception FIFO storage device. It is a figure showing the image of the receiving FIFO memory | storage device used by the 2nd invention of this invention.

FIG. 6 is a diagram showing a configuration in which a high-speed part extracts data from a flip-flop array stored in a low-speed part.

FIG. 7 is a diagram showing a configuration of a reception FIFO storage device according to a second embodiment and a third embodiment.

FIG. 8 is a diagram showing a configuration of a transaction data acquisition unit according to the fourth embodiment.

FIG. 9 is a diagram showing changes in the contents of a reception FIFO storage device according to the fourth embodiment.

FIG. 10 is a diagram showing a configuration of a speed conversion unit in the fifth embodiment. 1 is a schematic view of a system to which an LSI according to the present invention is applied.

FIG. 11 is a diagram showing a system configuration to which a bus conversion device according to the related art and the present invention is applied.

FIG. 12 is a diagram showing a configuration of a conventional bus conversion unit.

[Explanation of symbols]

1 bus converter, 2 high speed part, 3 I / O buffer,
4 system bus 1 cycle input signal group, 5 speed conversion section, 6 control section, 7 data path section, 8 system bus 1 cycle output signal group, 9 low speed section, 10
Receive FIFO write controller, 11 Receive FIFO, 1
2 reception FIFO write controller, 13 flip-flop array, 14 system bus N cycle signal group, 15 system bus output signal group, 20 flip-flop, 21, 22, 23 flip-flop output,
24, 25, 26, 27 speed converter output, 30 flip-flop array output, 31 selector, 32
Flip-flop, 33 selector control signal, 33 1 cycle output signal to system bus, 40 reception F
Output signal of top entry of IFO, 41 receive FIFO
Second entry output signal, 42 transaction analysis circuit, 43 register holding the output signal of the first entry of the receive FIFO, 44 register holding the output signal of the second entry of the receive FIFO, 45 state of the transaction analysis circuit Signal, 46 read control signal 1, 47 read control signal 2, 48 counter,
50 AND circuit.

Claims (10)

[Claims] 1. An interface with a system bus operating at a high-speed frequency and an interface with a low-speed bus operating at 1 / N of the operating frequency of the system bus are provided for N bus cycles of the system bus. A speed conversion unit that collectively converts data into data of one bus cycle of the low-speed bus, a FIFO storage device that stores the data converted by the speed conversion unit, and the data stored in the FIFO storage device to the system. A bus conversion device, comprising: a processing unit that extracts and processes the bus cycles output to the bus in order. 2. The FIFO memory device has means for judging the validity of the bus data sent from the speed conversion unit, and stores only the data of valid bus cycles. The bus conversion device described in 1. 3. The bus conversion device according to claim 2, wherein the processing unit simultaneously reads data of a plurality of bus cycles from the FIFO storage device. 4. The system bus is configured by a bus having a common address line and data line, the processing unit has a data analysis unit, and based on an analysis result of the data analysis unit, the FIFO storage device outputs the data from the FIFO storage device. The bus conversion device according to claim 4, wherein the number of bus cycles of data to be read is determined. 5. The speed converter includes a (N-1) stage flip-flop that holds bus data for (N-1) bus cycles driven at a high frequency, input data, and the (N-1) stage flip-flop. 1. A bus according to claim 1, characterized in that it comprises: 1) N flip-flops which are driven at a frequency of 1 / N of the high-speed frequency with each output of the flip-flops as inputs. Converter. 6. The speed conversion unit receives the counter that operates at a high frequency, N flip-flops whose drive inputs are controlled by the output of the counter, and outputs of the N flip-flops as inputs. Fast frequency 1
2. The bus conversion device according to claim 1, wherein the bus conversion device is configured by N flip-flops operating at a frequency of / N. 7. A storage device for storing the data processed by the processing unit is provided, and the number of data that can be read at one time from this storage device is equal to the maximum number of bus cycles that can be sent to the system bus in one arbitration. 3. The data path unit according to claim 1, further comprising a data path unit for taking out the read data one bus cycle at a time by the selector and continuously sending the read data to the system bus for a required number of cycles.
7. The bus conversion device according to claim 6. 8. The bus conversion device according to claim 7, wherein the number of data that can be read from the storage device at one time is set to N bus cycle of the system bus. 9. The data path unit according to claim 7, wherein the data path unit sends to the system bus data corresponding to the number of sent bus cycles which is notified in advance from the storage device. Bus conversion device. 10. The memory device according to claim 7, wherein the memory device comprises a flip-flop array.
Alternatively, the bus conversion device according to claim 9.