JPH09213662A - Method of splitting wafer and method of manufacturing semiconductor device - Google Patents
Method of splitting wafer and method of manufacturing semiconductor deviceInfo
- Publication number
- JPH09213662A JPH09213662A JP8016037A JP1603796A JPH09213662A JP H09213662 A JPH09213662 A JP H09213662A JP 8016037 A JP8016037 A JP 8016037A JP 1603796 A JP1603796 A JP 1603796A JP H09213662 A JPH09213662 A JP H09213662A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- chip
- semiconductor device
- envelope
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
- Dicing (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明はウェーハの分割方
法及び半導体装置の製造方法に関するもので、特に、ウ
ェーハ上に形成された半導体素子を個々のチップに切断
分離し、外囲器に封止する工程に係り、外囲器の小型薄
厚化やウェーハの大口径化時に好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for dividing a wafer and a method for manufacturing a semiconductor device, and in particular, a semiconductor element formed on a wafer is cut into individual chips and sealed in an envelope. It is suitable for reducing the size and thickness of the envelope and increasing the diameter of the wafer in the process.
【０００２】[0002]
【従来の技術】半導体装置の製造工程は、ウェーハ（半
導体基板）上に種々の半導体素子のパターンを形成する
工程と、ウェーハ上に形成された半導体素子を個々のチ
ップに切断分離し、外囲器に封止する工程とに大別でき
る。近年、製造コストの低減を図るためにウェーハの大
口径化が推進されるとともに、実装密度を高めるために
外囲器の小型薄厚化が望まれている。従来は、薄厚化し
た外囲器に封止するために、ウェーハを個々のチップに
切断分離するのに先立って、ウェーハのパターン形成面
（主表面）の反対側の面（ウェーハの裏面）を砥石によ
る研削及び遊離砥粒による研磨等により除去して薄く
し、その後ダイシングして切断分離している。研削時に
は、ウェーハのパターン形成面に粘着性のシートを貼り
付けたり、レジスト等を塗布することによって保護して
いる。この後、上記ウェーハの主表面に形成された切断
分離（ダイシング）ライン領域に溝を形成する。この溝
を形成する際には、ダイヤモンドスクライバー、ダイヤ
モンドブレード、あるいはレーザースクライバー等を用
いている。上記ダイシング工程には、ウェーハ単体でこ
のウェーハの厚さの１／２までダイシング、またはウェ
ーハが３０μｍ程度残る状態までダイシングを行うハー
フカット法、ウェーハの裏面に粘着性のシートを貼り付
けて同様にダイシングするハーフカット法、粘着性のシ
ートを２０〜３０μｍ程度まで切り込み、ウェーハ厚全
てを切断するフルカット法等が用いられる。上記ハーフ
カット法は、分割作業が必要とされ、ウェーハ単体の場
合にはウェーハを柔軟性のあるフィルム等に挟み、ロー
ラー等で外力を加えて分割する。シートに貼り付けた場
合には、テープ越しにローラーその他で外力を加え分割
する。分割されたチップは、ダイボンディング装置に設
けられているピックアップニードルによってシート裏面
を突き上げ、このシートを貫通してチップ裏面にニード
ル（針）を直接接触させ、更に持ち上げてチップをシー
トから引き離す。引き離されたチップは、コレットと呼
ばれるツールでチップ表面を吸着し、リードフレームの
アイランドにマウントした後、ワイヤボンディングを行
ってチップの各パッドとリードフレームのインナーリー
ド部とを電気的に接続し、外囲器に封止している。上記
チップのアイランドへのマウント方法としては、アイラ
ンドへ導電性ペーストを予め塗布しておく方法、金−シ
リコンの共晶を利用してマウントする方法、及びウェー
ハの裏面に金属の薄膜を蒸着し、半田を用いてマウント
する方法等がある。2. Description of the Related Art The manufacturing process of a semiconductor device includes the steps of forming various semiconductor element patterns on a wafer (semiconductor substrate) and cutting and separating the semiconductor elements formed on the wafer into individual chips. It can be roughly divided into a process of sealing in a container. In recent years, an increase in the diameter of wafers has been promoted in order to reduce the manufacturing cost, and it has been desired to reduce the size and thickness of the envelope in order to increase the packaging density. Conventionally, in order to seal the wafer in a thinned envelope, the surface opposite to the pattern formation surface (main surface) of the wafer (the back surface of the wafer) is cut before separating the wafer into individual chips. It is thinned by removing it by grinding with a grindstone, polishing with loose abrasive grains, and the like, and then cut and separated by dicing. During grinding, an adhesive sheet is attached to the pattern forming surface of the wafer, or a resist or the like is applied to protect the wafer. Thereafter, a groove is formed in the cutting and separating (dicing) line region formed on the main surface of the wafer. When forming this groove, a diamond scriber, a diamond blade, a laser scriber, or the like is used. In the dicing step, a single wafer is diced to a half of the thickness of the wafer, or a half-cut method of dicing until the wafer remains about 30 μm, and an adhesive sheet is attached to the back surface of the wafer in the same manner. A half-cut method of dicing, a full-cut method of cutting an adhesive sheet to about 20 to 30 μm, and cutting the entire wafer thickness are used. The half-cut method requires division work, and in the case of a single wafer, the wafer is sandwiched between flexible films or the like, and external force is applied by rollers or the like to divide the wafer. When it is attached to the sheet, it is divided by applying an external force through the tape with a roller or the like. The divided chips are pushed up on the back surface of the sheet by a pickup needle provided in the die bonding apparatus, penetrate the sheet to directly contact the needle (needle) with the back surface of the chip, and further lift the chip away from the sheet. The separated chip adsorbs the chip surface with a tool called a collet, mounts it on the island of the lead frame, and then performs wire bonding to electrically connect each pad of the chip and the inner lead part of the lead frame, It is sealed in an envelope. As a method of mounting the chip on the island, a method of applying a conductive paste to the island in advance, a method of mounting using a gold-silicon eutectic, and a metal thin film is vapor-deposited on the back surface of the wafer, There is a method of mounting using solder.
【０００３】図９ないし図１５はそれぞれ、上述したよ
うな従来のウェーハの分割方法及び半導体装置の製造方
法の詳細な例について説明するためのもので、図９はウ
ェーハの表面保護テープを貼り付ける工程、図１０はウ
ェーハの裏面の研削及び研磨工程、図１１は表面保護テ
ープを剥がす工程、図１２（ａ），（ｂ）はウェーハを
固定用シートに固着する工程、図１３はウェーハのダイ
シング工程、図１４は分離したチップをピックアップす
る工程、及び図１５はダイボンディング工程をそれぞれ
示している。9 to 15 are each for explaining a detailed example of the conventional method for dividing a wafer and the method for manufacturing a semiconductor device as described above. FIG. 9 shows a wafer surface protection tape attached. Step, FIG. 10 is a step of grinding and polishing the back surface of the wafer, FIG. 11 is a step of peeling the surface protection tape, FIGS. 12A and 12B are steps of fixing the wafer to a fixing sheet, and FIG. 13 is dicing of the wafer. 14 shows a step of picking up separated chips, and FIG. 15 shows a die bonding step.
【０００４】図９ないし図１５において、１は各種の半
導体素子が形成されたウェーハ、１´はパターン形成面
（ウェーハ１の主表面）、２はポーラスチャックテーブ
ル、３はパターン形成面の保護テープ、４は貼り付けロ
ーラー、５は裏面研削用のチャックテーブル、６は研削
用砥石、７は保護テープ３を剥がすためのテープ、８は
フラットリング、９はウェーハの固定用シート、１０は
ダイシング用チャックテーブル、１１はダイシング用ブ
レード、１２は切断分離後のチップ、１３はピックアッ
プニードル、１４はリードフレームのアイランド、１５
は導電性ペースト等のダイボンディング用接着剤であ
る。In FIGS. 9 to 15, 1 is a wafer on which various semiconductor elements are formed, 1'is a pattern forming surface (main surface of the wafer 1), 2 is a porous chuck table, 3 is a protective tape for the pattern forming surface. 4, a sticking roller, 5 a chuck table for backside grinding, 6 a grinding wheel, 7 a tape for peeling off the protective tape 3, 8 a flat ring, 9 a sheet for fixing a wafer, 10 dicing Chuck table, 11 dicing blade, 12 chip after cutting and separation, 13 pickup needle, 14 lead frame island, 15
Is a die bonding adhesive such as a conductive paste.
【０００５】まず、図９に示すように、ウェーハ１の裏
面をポーラスチャックテーブル２上に固定し、貼り付け
ローラー４を回転させながら図示矢印方向に移動させて
保護テープ３をウェーハ１のパターン形成面１´に貼り
付ける。次に、図１０に示すように、上記保護テープ３
を貼り付けたパターン形成面１´を下にしてチャックテ
ーブル５に固定し、ウェーハ１の裏面を研削用砥石６で
所定の厚さ（最終的なチップ厚）まで研削及び研磨す
る。その後、図１１に示すように、保護テープ３に保護
テープを剥がすためのテープ７を貼り付け、パターン形
成面１´から保護テープ３を剥離する。次に、図１２
（ａ）に示すようなフラットリング８をウェーハの固定
用シート９に固着してシート９の弛みや皺などの発生を
防止した状態で、図１２（ｂ）に示す如くフラットリン
グ８の開口内のシート９上にチップ１を固着する。そし
て、上記チップ１を固着したシート９とフラットリング
をダイシング用のチャックテーブル１０に固定し、ダイ
シング用ブレード１１でダイシング（フルカット）し、
個々のチップ１２に切断分離する（図１３参照）。次
に、図１４に示すようにシート９の下方からピックアッ
プニードル１３をシート９を貫通させてチップ１２の裏
面に当てて押圧することにより個々のチップ１２をシー
ト９から剥離し、図１５に示すようにリードフレームの
アイランド１４に導電性ペースト等のダイボンディング
用接着剤を用いてマウントする。その後、リードフレー
ムのインナーリード部とチップ１２の各パッドとをワイ
ヤボンディングし、樹脂製やセラミック製の外囲器に封
止して半導体装置を完成する。First, as shown in FIG. 9, the back surface of the wafer 1 is fixed on the porous chuck table 2, and the sticking roller 4 is rotated and moved in the direction of the arrow shown in FIG. Stick on surface 1 '. Next, as shown in FIG.
The pattern forming surface 1 ′ attached with is fixed to the chuck table 5, and the back surface of the wafer 1 is ground and polished by a grinding stone 6 to a predetermined thickness (final chip thickness). Thereafter, as shown in FIG. 11, a tape 7 for peeling off the protective tape is attached to the protective tape 3, and the protective tape 3 is peeled off from the pattern forming surface 1 '. Next, FIG.
In the opening of the flat ring 8 as shown in FIG. 12 (b), the flat ring 8 as shown in (a) is fixed to the wafer fixing sheet 9 to prevent the sheet 9 from being loosened or wrinkled. The chip 1 is fixed on the sheet 9. Then, the sheet 9 to which the chip 1 is fixed and the flat ring are fixed to the chuck table 10 for dicing, and dicing (full cut) is performed with the dicing blade 11.
The individual chips 12 are cut and separated (see FIG. 13). Next, as shown in FIG. 14, the individual pickup chips 12 are peeled from the sheet 9 by penetrating the sheet 9 from below the sheet 9 and abutting and pressing the pickup needle 13 against the back surface of the chip 12, as shown in FIG. In this manner, the island 14 of the lead frame is mounted using a die bonding adhesive such as a conductive paste. After that, the inner lead portion of the lead frame and each pad of the chip 12 are wire-bonded and sealed in a resin or ceramic envelope to complete the semiconductor device.
【０００６】しかしながら、上記のようなウェーハの分
割方法及び半導体装置の製造方法では、下記（ａ）〜
（ｃ）に示すような問題がある。 （ａ）薄厚研削時にウェーハが割れ易い。保護テープを
貼り付けて研削を行っても、研削時の歪みによりウェー
ハが反ってしまい、このために研削装置内での搬送時に
引っ掛かったりして破損する。また、ウェーハが薄くな
ったり大口径化されるに従いウェーハの強度が低下する
ため、現状のようにウェーハを薄くした後、ウェーハ単
体を搬送して種々の処理を施す方法では破損する確率が
高くなる。例えば、ウェーハが４００μｍの厚さでは
１．６Ｋｇｆ／ｍｍ2 程度まで耐えられるが、厚さが２
００μｍになると０．４Ｋｇｆ／ｍｍ2 と１／４にまで
低下する。However, in the wafer dividing method and the semiconductor device manufacturing method as described above, the following (a) to
There is a problem as shown in (c). (A) The wafer is easily broken during thin-thickness grinding. Even if the protective tape is attached and the wafer is ground, the wafer is warped due to the distortion during the grinding, which causes the wafer to be caught or damaged during the transportation in the grinding machine. In addition, since the strength of the wafer decreases as the wafer becomes thinner or the diameter increases, the method of carrying out various treatments by transporting the wafer alone after the wafer is thinned as in the current situation increases the probability of damage. . For example, a wafer with a thickness of 400 μm can withstand up to about 1.6 kgf / mm 2 , but a thickness of 2
When it becomes 00 μm, it decreases to 0.4 Kgf / mm 2 and 1/4.
【０００７】（ｂ）パターン形成面の保護とダイシング
時のウェーハ保持用として二枚のシートを使用するた
め、これらの貼り付け、剥離、貼り付けと工程がそれぞ
れ必要となり、材料費が高くなり製造工程も増加する。(B) Since two sheets are used to protect the pattern-formed surface and to hold the wafer during dicing, the steps of attaching, peeling, and attaching each of these are required, which increases the material cost and manufacture. The process also increases.
【０００８】（ｃ）ダイシングを行った場合、ウェーハ
の裏面側のチッピングが大きくなり、チップの抗折強度
の低下を招く。しかも、従来は種々の特性モニター用の
トランジスタ、抵抗、コンデンサー等（これらをＴＥ
Ｇ：Ｔｅｓｔ ＥｌｅｍｅｎｔＧｒｏｕｐと称する）を
チップ内に配置していたが、高集積化を図るためにダイ
シングライン上に配置されるようになった。周知の通
り、これらの素子は酸化膜、アルミニウム等で構成され
ており、ダイヤモンドブレードを用いてダイシングを行
う際に、砥石の目詰まりを起こし易く、切れ味を阻害す
る材料である。このため、ダイシングライン上にＴＥＧ
が配置されている場合には、ウェーハの裏面側のチッピ
ングが更に大きくなる。一般に半導体基板として使用さ
れている材料はシリコンやＧａＡｓ等脆性材であるため
に、クラック等が存在すると抗折強度の低下を招きやす
い。(C) When dicing is performed, chipping on the back surface side of the wafer becomes large, resulting in a decrease in chip bending strength. Moreover, conventionally, various characteristic monitoring transistors, resistors, capacitors, etc.
G: Test Element Group) was arranged in the chip, but it is now arranged on the dicing line in order to achieve high integration. As is well known, these elements are composed of an oxide film, aluminum, etc., and are materials that easily cause the grinding stone to be clogged when dicing using a diamond blade and impair the sharpness. Therefore, the TEG on the dicing line
Is arranged, the chipping on the back surface side of the wafer is further increased. In general, the material used as a semiconductor substrate is a brittle material such as silicon or GaAs, and therefore cracks or the like are likely to cause a decrease in bending strength.
【０００９】[0009]
【発明が解決しようとする課題】上記のように従来のウ
ェーハの分割方法及び半導体装置の製造方法は、薄厚研
削時や搬送時にウェーハが割れやすいという問題があっ
た。また、パターン形成面の保護とウェーハの保持のた
めに二枚のシートを必要とするため、材料費が高くなり
製造工程も増加するという問題があった。更に、ダイシ
ングを行った場合、ウェーハの裏面側のチッピングが大
きくなり、チップの抗折応力の低下を招くという問題が
あった。As described above, the conventional wafer dividing method and semiconductor device manufacturing method have a problem that the wafer is easily broken during thin-thickness grinding or during transportation. Further, since two sheets are required to protect the pattern formation surface and hold the wafer, there is a problem that the material cost is increased and the manufacturing process is increased. Furthermore, when dicing is performed, there is a problem that chipping on the back surface side of the wafer becomes large, resulting in a decrease in bending stress of the chip.
【００１０】この発明は上記のような事情に鑑みてなさ
れたもので、その目的とするところは、薄厚研削時や搬
送時のウェーハの割れを抑制できるウェーハの分割方法
及び半導体装置の製造方法を提供することにある。The present invention has been made in view of the above circumstances. An object of the present invention is to provide a wafer dividing method and a semiconductor device manufacturing method capable of suppressing the cracking of a wafer during thin-thickness grinding or during transportation. To provide.
【００１１】また、この発明の他の目的は、製造工程と
コストの削減が図れるウェーハの分割方法及び半導体装
置の製造方法を提供することにある。この発明の更に他
の目的は、ウェーハの裏面側のチッピングを小さくで
き、チップの抗折応力の低下を抑制できるウェーハの分
割方法及び半導体装置の製造方法を提供することにあ
る。Another object of the present invention is to provide a wafer dividing method and a semiconductor device manufacturing method capable of reducing the manufacturing process and cost. Still another object of the present invention is to provide a method for dividing a wafer and a method for manufacturing a semiconductor device, which can reduce chipping on the back surface side of the wafer and suppress a decrease in bending stress of a chip.
【００１２】[0012]
【課題を解決するための手段】この発明の請求項１に記
載したウェーハの分割方法は、半導体素子が形成された
ウェーハのダイシングラインに沿って上記半導体素子の
形成面側から所定の深さの溝を形成する工程と、上記ウ
ェーハにおける半導体素子の形成面上に保持用のシート
を貼り付ける工程と、上記ウェーハの裏面を上記溝に達
するまで研削及び研磨し、ウェーハを個々のチップに分
離する工程とを具備することを特徴としている。According to a first aspect of the present invention, there is provided a method of dividing a wafer, wherein a predetermined depth is provided from a semiconductor element formation surface side along a dicing line of a wafer on which a semiconductor element is formed. A step of forming a groove, a step of attaching a holding sheet on the formation surface of the semiconductor element in the wafer, and a back surface of the wafer is ground and polished until the groove is reached, and the wafer is separated into individual chips. And a process.
【００１３】また、この発明の請求項２に記載した半導
体装置の製造方法は、ウェーハの主表面に半導体素子を
形成する工程と、ダイシングラインに沿って上記ウェー
ハの主表面側から所定の深さの溝を形成する工程と、上
記ウェーハの主表面上に粘着性のシートを貼り付ける工
程と、上記ウェーハの裏面を上記溝に達するまで研削及
び研磨し、ウェーハを個々のチップに分離する工程と、
分離した各チップを上記粘着性のシートから剥離して外
囲器に封止する工程とを具備することを特徴としてい
る。According to a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming a semiconductor element on a main surface of a wafer and a predetermined depth from the main surface side of the wafer along a dicing line. A step of forming a groove, a step of sticking an adhesive sheet on the main surface of the wafer, a step of grinding and polishing the back surface of the wafer until the groove is reached, and a step of separating the wafer into individual chips; ,
And a step of peeling each separated chip from the adhesive sheet and sealing the chip in an envelope.
【００１４】請求項３に示すように、前記分離した各チ
ップを前記粘着性のシートから剥離して外囲器に封止す
る工程は、ピックアップニードルを前記粘着性のシート
を介して前記チップの主表面に当てて押圧することによ
り前記チップを粘着性のシートから剥離し、チップ毎に
外囲器に封止するものであることを特徴とする。According to a third aspect of the present invention, in the step of peeling each of the separated chips from the adhesive sheet and sealing the envelope in an envelope, a pickup needle of the chip is inserted through the adhesive sheet. It is characterized in that the chip is peeled from the adhesive sheet by being pressed against the main surface and sealed in an envelope for each chip.
【００１５】請求項４に示すように、前記分離した各チ
ップを前記粘着性のシートから剥離して外囲器に封止す
る工程は、前記粘着性のシートから剥離したチップをリ
ードフレームのアイランドにマウントし、上記リードフ
レームのインナーリード部と前記チップの各パッドとを
ワイヤボンディングした後、外囲器に封止するものであ
ることを特徴とする。According to a fourth aspect of the present invention, in the step of peeling each of the separated chips from the adhesive sheet and sealing in an envelope, the chips peeled from the adhesive sheet are used as islands of a lead frame. And wire-bonding the inner lead portion of the lead frame and each pad of the chip, and then sealing in an envelope.
【００１６】あるいは、請求項５に示すように、前記分
離した各チップを前記粘着性のシートから剥離して外囲
器に封止する工程は、前記粘着性のシートから剥離した
チップの主表面上にリードの一端を接着し、上記リード
と前記チップの各パッドとをワイヤボンディングした
後、外囲器に封止するものであることを特徴とする。Alternatively, as set forth in claim 5, the step of peeling each of the separated chips from the adhesive sheet and sealing in an envelope is performed by the main surface of the chip peeled from the adhesive sheet. One end of the lead is bonded to the upper part, the lead and each pad of the chip are wire-bonded, and then sealed in an envelope.
【００１７】請求項６に示すように、前記チップの主表
面とリードとの間に介在される接着テープを更に備え、
前記接着テープの厚さは、前記ウェーハの裏面の研削及
び研磨工程で発生するシリコン屑よりも厚いことを特徴
とする。As described in claim 6, further comprising an adhesive tape interposed between the main surface of the chip and the lead,
The thickness of the adhesive tape is thicker than silicon debris generated in the grinding and polishing process of the back surface of the wafer.
【００１８】請求項１のようなウェーハの分割方法によ
れば、ウェーハの素子形成面側から所定の深さの溝を形
成し、このウェーハの裏面を溝に達するまで研削及び研
磨することによってウェーハを個々のチップに分離する
ので、ダイシングの際のチッピングを抑制できる。According to the wafer dividing method of the first aspect, a wafer having a predetermined depth is formed from the element forming surface side of the wafer, and the back surface of the wafer is ground and polished until it reaches the groove. Since chips are separated into individual chips, chipping during dicing can be suppressed.
【００１９】請求項２のような半導体装置の製造方法に
よれば、ウェーハ上に形成された半導体素子を個々のチ
ップ毎に切断分離して外囲器に封止する工程を、ダイシ
ング（ハーフカット）、ウェーハの裏面研削及び研磨、
ダイボンディングの順にしたので、ウェーハを個々のチ
ップに分離するのは、研削及び研磨によって行う。よっ
て、ウェーハの裏面を研削及び研磨して薄厚化した状態
での搬送や処理工程がないので、ウェーハの破損を防止
できる。シートは一枚で済むので材料費の低減と製造工
程の削減が図れ、低コスト化できる。外力を加えてウェ
ーハを分割する必要がないのでチッピングを抑制でき
る。また、ウェーハの裏面側を、切削及び研磨によって
除去して個々のチップに分離するので、ウェーハの裏面
側に発生するチッピングを抑制でき、抗折応力の低下を
抑制できる。According to the method of manufacturing a semiconductor device as claimed in claim 2, the step of cutting and separating the semiconductor element formed on the wafer into individual chips and sealing them in the envelope is performed by dicing (half cut). ), Wafer backside grinding and polishing,
Since the order of die bonding is used, the wafer is separated into individual chips by grinding and polishing. Therefore, since there is no conveyance or treatment process in the state where the back surface of the wafer is ground and polished to be thinned, damage to the wafer can be prevented. Since only one sheet is required, the material cost and the manufacturing process can be reduced, and the cost can be reduced. Since it is not necessary to divide the wafer by applying an external force, chipping can be suppressed. Further, since the back surface side of the wafer is removed by cutting and polishing to be separated into individual chips, chipping that occurs on the back surface side of the wafer can be suppressed, and reduction in transverse stress can be suppressed.
【００２０】請求項３に記載したように、ピックアップ
ニードルを粘着性のシートを介してチップの主表面に当
てて押圧し、チップを粘着性のシートから剥離しても、
ピックアップニードルの先端部の太さを最適化すれば粘
着性のシートを破ることなくチップを剥離することがで
き、半導体素子への損傷を防止できる。As described in claim 3, even if the pickup needle is pressed against the main surface of the chip via the adhesive sheet and the chip is peeled from the adhesive sheet,
If the thickness of the tip of the pickup needle is optimized, the chip can be peeled off without breaking the adhesive sheet, and damage to the semiconductor element can be prevented.
【００２１】請求項４に記載したように通常の樹脂パッ
ケージやセラミックパッケージに封止しても良く、請求
項５に記載したようにＬＯＣ（Ｌｅａｄ Ｏｎ Ｃｈｉ
ｐ）パッケージに封止しても良い。As described in claim 4, it may be sealed in an ordinary resin package or ceramic package, and as described in claim 5, LOC (Lead On Chi).
p) The package may be sealed.
【００２２】請求項６に記載したように、チップの主表
面とリードとの間にウェーハの裏面の研削及び研磨工程
で発生するシリコン屑よりも厚い接着テープを介在させ
れば、シリコン屑による不良を防止できる。As described in claim 6, if an adhesive tape thicker than silicon chips generated in the grinding and polishing steps of the back surface of the wafer is interposed between the main surface of the chip and the leads, defects due to silicon chips are caused. Can be prevented.
【００２３】[0023]
【発明の実施の形態】以下、この発明の実施の形態につ
いて図面を参照して説明する。図１ないし図６はそれぞ
れ、この発明の第１の実施の形態に係るウェーハの分割
方法及び半導体装置の製造方法について説明するための
もので、図１はダイシングラインに沿ってウェーハに溝
を形成する工程、図２（ａ），（ｂ）はウェーハに表面
保護テープを貼り付ける工程、図３はウェーハ裏面の研
削及び研磨工程（分割工程）、図４は分離したチップを
ピックアップする工程、図５はダイボンディング工程及
び図６は外囲器に封止する工程をそれぞれ示している。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 are each for explaining a wafer dividing method and a semiconductor device manufacturing method according to a first embodiment of the present invention. FIG. 1 shows a groove formed in a wafer along a dicing line. 2A and 2B are steps of attaching a surface protection tape to the wafer, FIG. 3 is a step of grinding and polishing the back surface of the wafer (dividing step), and FIG. 4 is a step of picking up separated chips. 5 shows a die bonding step, and FIG. 6 shows a step of sealing in an envelope.
【００２４】図１ないし図６において、２１は各種の半
導体素子が形成されたウェーハ、２１´はパターン形成
面（ウェーハ２１の主表面）、２２はダイシングライン
に沿って形成された溝、２３はダイシング用チャックテ
ーブル、２４はダイシング用ブレード、２５はフラット
リング、２６はパターン形成面の表面保護テープ（粘着
性のシート）、２７は裏面研削用チャックテーブル、２
８は裏面研削用砥石、２９は切断分離後のチップ、３０
はピックアップニードル、３１はリードフレームのアイ
ランド（ベッド）、３２は導電性ペースト等のダイボン
ディング用接着剤、３３は樹脂パッケージまたはセラミ
ックパッケージ（外囲器）、３４はリードフレーム、及
び３５はボンディングワイヤである。1 to 6, 21 is a wafer on which various semiconductor elements are formed, 21 'is a pattern forming surface (main surface of the wafer 21), 22 is a groove formed along the dicing line, and 23 is Dicing chuck table, 24 dicing blade, 25 flat ring, 26 surface protection tape (adhesive sheet) for pattern forming surface, 27 back surface chuck table, 2
8 is a grindstone for backside grinding, 29 is a chip after cutting and separating, 30
Is a pickup needle, 31 is an island (bed) of a lead frame, 32 is an adhesive for die bonding such as conductive paste, 33 is a resin package or ceramic package (envelope), 34 is a lead frame, and 35 is a bonding wire. Is.
【００２５】先ず、図１に示す如く、各種の半導体素子
が形成されたウェーハ２１をパターン形成面側を上にし
て、ダイシング装置のチャックテーブル２３にバキュー
ムその他の方法で吸着して固定する。そして、ダイシン
グ用ブレード２４を任意の回転数で回転させ、切削水を
掛けながら所定の深さまで溝２２を切り込む。この溝２
２の深さは、最終的なチップの厚さと実質的に等しい
か、それより少し深くする。その後、ウェーハ２１の洗
浄と乾燥処理を行う。First, as shown in FIG. 1, the wafer 21 on which various semiconductor elements are formed is fixed to the chuck table 23 of the dicing device by vacuum suction or another method with the pattern forming surface side facing upward. Then, the dicing blade 24 is rotated at an arbitrary number of revolutions, and the groove 22 is cut to a predetermined depth while sprinkling cutting water. This groove 2
The depth of 2 should be substantially equal to or slightly deeper than the final chip thickness. Then, the wafer 21 is washed and dried.
【００２６】次に、図２（ａ）に示すようなフラットリ
ング２５を表面保護テープ２６に貼り付けてこのテープ
２６の弛みや皺を除去した状態で、図２（ｂ）に示すよ
うに前工程で溝２２を形成したウェーハ２１のパターン
形成面２１´をテープ２６の接着剤側に貼り付けて固定
する。Next, a flat ring 25 as shown in FIG. 2 (a) is attached to the surface protection tape 26, and the slack and wrinkles of the tape 26 are removed, as shown in FIG. 2 (b). The pattern forming surface 21 ′ of the wafer 21 having the groove 22 formed in the step is attached and fixed to the adhesive side of the tape 26.
【００２７】その後、図３に示すように、上記フラット
リング２５と表面保護テープ２６とで保持されたウェー
ハ２１を、研削装置のチャックテーブル２７にバキュー
ム等の方法で吸着固定する。そして、チャックテーブル
２７と研削用砥石２８を回転させ、砥石２８を降下させ
ながらウェーハ２１の裏面を削る。一般にこの研削方法
はインフィード研削と呼ばれるものであるが、別の方法
としてスルーフィード研削またはクリープフィード研削
と呼ばれ、ウェーハの側面と砥石２８を回転させながら
削る方法を用いても良い。After that, as shown in FIG. 3, the wafer 21 held by the flat ring 25 and the surface protection tape 26 is attracted and fixed to the chuck table 27 of the grinding machine by a method such as vacuum. Then, the chuck table 27 and the grinding stone 28 are rotated, and the back surface of the wafer 21 is ground while lowering the grinding stone 28. Generally, this grinding method is called in-feed grinding, but as another method, it is called through-feed grinding or creep-feed grinding, and a method of grinding while rotating the side surface of the wafer and the grindstone 28 may be used.
【００２８】次に、図４に示すように、ウェーハ２１の
切断分離を終えて分割された個々のチップ２９が接着固
定されているフラットリング２５をダイボンディング装
置に設置し、このダイボンディング装置のピックアップ
ニードル３０を用いて表面保護テープ２６越しにパター
ン形成面２２に圧力を加える。これによって、ピックア
ップニードル３０は、テープ２６を貫通することなくチ
ップ２９のパターン形成面を押圧し、チップ２９がテー
プ２６から剥離される。上記ピックアップニードル３０
は、先端曲率半径が０．３５ｍｍ以上であれば１８Ｎの
力が掛かっても（１５ｍｍ×１５ｍｍチップ）、チップ
２９中に形成されたアルミ配線等にダメージが発生しな
いことを本発明者等は実験により確認している。よっ
て、チップ２９の主表面側から表面保護テープ２６を介
してピックアップニードル３０（金属製のピン）で押し
剥がしても、先端曲率半径を最適化することによりピッ
クアップニードル３０がテープ２６を破ることはなく、
特に問題は発生しない。Next, as shown in FIG. 4, the flat ring 25 to which the individual chips 29 that have been cut and separated after the wafer 21 have been cut and bonded are fixedly attached to the die bonding apparatus. The pickup needle 30 is used to apply pressure to the pattern formation surface 22 through the surface protection tape 26. As a result, the pickup needle 30 presses the pattern forming surface of the chip 29 without penetrating the tape 26, and the chip 29 is separated from the tape 26. The pickup needle 30
The inventors of the present invention have conducted an experiment that if the radius of curvature of the tip is 0.35 mm or more, the aluminum wiring and the like formed in the chip 29 will not be damaged even if a force of 18 N is applied (15 mm × 15 mm chip). Have confirmed by. Therefore, even if the tip 29 is pushed off by the pickup needle 30 (metal pin) from the main surface side of the tip 29 via the surface protection tape 26, the pickup needle 30 does not break the tape 26 by optimizing the radius of curvature of the tip. Without
No particular problem occurs.
【００２９】なお、本実施の形態では、チップ２９をテ
ープ２６から剥離する際に、チップ２９が押し下げられ
る構成となっているが、押し上げて剥離するように構成
しても良く、一般的には後者の方法が多用されている。In this embodiment, when the chip 29 is peeled off from the tape 26, the chip 29 is pushed down, but it may be pushed up and peeled off. The latter method is often used.
【００３０】テープ２６から剥離されたチップ２９は、
ダイボンディング装置のコレットと呼ばれるツールで吸
着保持し、図５に示すようにリードフレームのアイラン
ド３１にマウントする。この際、リードフレームのアイ
ランド３１に予め接着固定用の導電性ペースト３２を塗
布しておき、その上にチップ２９をダイボンディングす
る。金−シリコンの共晶を利用してマウントしたり、ウ
ェーハの裏面に金属の薄膜を蒸着し、半田を用いてマウ
ントすることもできる。The chip 29 separated from the tape 26 is
It is adsorbed and held by a tool called a collet of a die bonding apparatus, and mounted on an island 31 of a lead frame as shown in FIG. At this time, the conductive paste 32 for adhesive fixing is applied to the island 31 of the lead frame in advance, and the chip 29 is die-bonded thereon. It is also possible to mount using a eutectic of gold-silicon, or to deposit using a solder by depositing a thin metal film on the back surface of the wafer.
【００３１】その後、ワイヤボンディングを行ってチッ
プ２９の各パッドとリードフレーム３４のインナーリー
ド部とをボンディングワイヤ３５で電気的に接続する。
そして、チップ２９、アイランド３１及びリードフレー
ム３４のインナーリード部を樹脂パッケージ３３、また
はセラミックパッケージに封止し、リードフォーミング
を行って図６に示すような半導体装置を完成する。Thereafter, wire bonding is performed to electrically connect each pad of the chip 29 and the inner lead portion of the lead frame 34 with the bonding wire 35.
Then, the chip 29, the island 31, and the inner lead portion of the lead frame 34 are sealed in a resin package 33 or a ceramic package, and lead forming is performed to complete a semiconductor device as shown in FIG.
【００３２】図７（ａ），（ｂ）はそれぞれ、ウェーハ
を個々のチップに分離した時の研削面の拡大図である。
（ａ）図は従来の分割方法及び製造方法を用いた場合を
示し、フルカットによってダイシングした時の研削面側
の拡大図である。図示する如く、ダイシング部に多数の
チッピングが発生している。（ｂ）図はこの発明の分割
方法及び製造方法を用いた場合を示すもので、（ａ）図
に比べてシャープな切断面であり、チッピングは大幅に
減少している。FIGS. 7A and 7B are enlarged views of the ground surface when the wafer is separated into individual chips.
FIG. 7A is a magnified view of the grinding surface side when the conventional dicing method and the manufacturing method are used and dicing is performed by full cutting. As shown in the figure, many chippings occur in the dicing portion. The figure (b) shows the case where the dividing method and the manufacturing method of the present invention are used, and the cutting surface is sharper than the figure (a), and the chipping is greatly reduced.
【００３３】図８は、この発明の第２の実施の形態に係
る半導体装置の製造方法について説明するためのもの
で、ＬＯＣ（Ｌｅａｄ Ｏｎ Ｃｈｉｐ）パッケージに
適用したものである。ＬＯＣパッケージの場合には、図
４に示したピックアップ工程の後、チップ２９上に接着
テープ３６を介在させてリード３７の一端を接着した
後、ワイヤボンディングを行ってチップ２９の各パッド
とリード３７とをボンディングワイヤ３５で接続し、樹
脂パッケージ３３またはセラミックパッケージに封止す
れば良い。FIG. 8 is for explaining a method of manufacturing a semiconductor device according to the second embodiment of the present invention, which is applied to a LOC (Lead On Chip) package. In the case of the LOC package, after the pick-up step shown in FIG. 4, one end of the lead 37 is bonded onto the chip 29 with the adhesive tape 36 interposed therebetween, and then wire bonding is performed to bond each pad of the chip 29 and the lead 37. Are connected to each other with a bonding wire 35 and sealed in a resin package 33 or a ceramic package.
【００３４】この際、チップ２９上にシリコン屑が存在
すると、リード３７の接着やワイヤボンディング時の荷
重により、シリコン屑がチップ２９表面の保護膜を破
り、アルミ配線の段線やショート等の不良を起こす危険
がある。そこで、上記接着テープ３６の厚さを上記シリ
コン屑よりも厚くすることにより、上述したような不良
の発生を抑制できる。At this time, if silicon debris is present on the chip 29, the silicon debris breaks the protective film on the surface of the chip 29 due to the load at the time of adhesion of the leads 37 and wire bonding, and a defect such as a step line or short circuit of the aluminum wiring. There is a risk of causing Therefore, by making the thickness of the adhesive tape 36 thicker than the silicon scrap, it is possible to suppress the occurrence of the above-mentioned defects.
【００３５】上記のようなウェーハの分割方法及び半導
体装置の製造方法によれば、下記（１）〜（５）に示す
ような効果が得られる。 （１）ウェーハの薄厚化時のウェーハ破損による不良率
の低減化が図れる。According to the wafer dividing method and the semiconductor device manufacturing method as described above, the following effects (1) to (5) can be obtained. (1) It is possible to reduce the defect rate due to wafer breakage when the wafer is thinned.
【００３６】下表１は、直径が６インチのウェーハを個
々のチップに分割した場合のチップ厚（溝の深さと実質
的に等しいか、あるいは少し深い）と破損率（ｐｐｍ：
ｐａｒｔｓ ｐａｒ ｍｉｌｌｉｏｎ）との関係を示し
ている。Table 1 below shows the chip thickness (substantially equal to or slightly deeper than the groove depth) and damage rate (ppm: when a wafer having a diameter of 6 inches is divided into individual chips).
The relationship with the "parts par million" is shown.
【００３７】[0037]
【表１】 表１に示す如く、従来はチップ厚が薄くなると破損率が
高くなったが、この発明では最終的なチップ厚が薄くな
るほど破損率が低くなる。これは、チップ厚を薄くする
場合には溝を浅くすることができるので、溝の下に残存
するウェーハ厚が厚くなることに依るものである。直径
が６インチのウェーハの場合には、ウェーハの厚さは通
常６００〜６５０μｍである。従来の分割方法及び製造
方法では、例えば１００μｍの厚さのチップを形成しよ
うとすると、ウェーハを予め１００μｍの厚さに研削及
び研磨し、図１１ないし図１３に示した処理を行う。こ
れに対し、この発明の方法では、１００μｍの溝を形成
した後（溝の下には５００〜５５０μｍのウェーハが残
存されている）、研削及び研磨して個々のチップに分割
するので破損率が低くなる。[Table 1] As shown in Table 1, the breakage rate becomes higher as the chip thickness becomes thinner in the past, but in the present invention, the breakage rate becomes lower as the final chip thickness becomes thinner. This is because the groove can be made shallower when the chip thickness is made thinner, so that the thickness of the wafer remaining under the groove becomes thicker. For a 6 inch diameter wafer, the thickness of the wafer is typically 600-650 μm. In the conventional dividing method and manufacturing method, for example, when a chip having a thickness of 100 μm is to be formed, the wafer is ground and polished in advance to a thickness of 100 μm, and the processing shown in FIGS. 11 to 13 is performed. On the other hand, in the method of the present invention, after forming a groove of 100 μm (a wafer of 500 to 550 μm remains under the groove), grinding and polishing are performed to divide into individual chips, so that the damage rate is Get lower.
【００３８】（２）搬送時のトラブルがウェーハの口径
に左右されない。フラットリングに粘着性のシートを貼
り付け、これを保持用とする方式のため、チップ厚が薄
くなっても、あるいは同じ口径でも切削歪みによるウェ
ーハの反りの影響を受けることなく装置内搬送が可能で
ある。また、チップ厚が薄くなると溝の下に残存される
ウェーハが厚くなるので、この点からも搬送時のウェー
ハ破損等を低減できる。これにより下表２のような効果
が得られる。但し、ウェーハの直径が８インチで、チッ
プの厚さを１００μｍに仕上げる場合のものである。(2) Trouble during transportation does not depend on the diameter of the wafer. Since an adhesive sheet is attached to the flat ring and used for holding, it can be transported inside the device without being affected by the warp of the wafer due to cutting strain even if the chip thickness becomes thin or the same diameter. Is. Further, as the chip thickness becomes thinner, the wafer left under the groove becomes thicker, and from this point as well, damage to the wafer during transportation can be reduced. As a result, the effects shown in Table 2 below are obtained. However, the diameter of the wafer is 8 inches, and the thickness of the chip is 100 μm.
【００３９】[0039]
【表２】 この表２のデータから明らかなように、この発明はウェ
ーハの大口径化に有効であり、今後展開されるウェーハ
の１２インチ化、または１６インチ化への対応が容易に
なる。[Table 2] As is clear from the data in Table 2, the present invention is effective for increasing the diameter of the wafer, and it is easy to cope with the 12-inch or 16-inch wafer that will be developed in the future.
【００４０】（３）表面保護テープを一枚しか使用しな
いため、従来の方法に比して材料費と加工費を６０％程
度削減でき、製造コストの低減が図れる。 （４）フルカット方式の場合、シートまで切り込むた
め、ブレードの切れ味の低下及びダイシング中のチップ
の飛散が生ずるため、一般的に８０〜１２０ｍｍ／ｓｅ
ｃであるが、この発明の方法では２００ｍｍ／ｓｅｃま
で可能である。これによって、ダイシングスピードの向
上が図れ、１０％程度の加工費の低減が図れる。(3) Since only one surface protection tape is used, the material cost and the processing cost can be reduced by about 60% as compared with the conventional method, and the manufacturing cost can be reduced. (4) In the case of the full-cut method, since the sheet is cut, the sharpness of the blade is deteriorated and the chips are scattered during dicing. Therefore, it is generally 80 to 120 mm / se.
c, but the method of the present invention is possible up to 200 mm / sec. As a result, the dicing speed can be improved and the processing cost can be reduced by about 10%.
【００４１】（５）ウェーハを分割するために、ダイシ
ングシートまで切り込む必要がなく、且つ裏面研削用の
砥石で研削して分割するため、裏面チッピングの大きさ
が従来の１５μｍ程度から４μｍ程度へと小さくなり、
抗折応力値も４５Ｋｇｆ／ｍｍ2 と向上する。(5) Since it is not necessary to cut into the dicing sheet to divide the wafer and the wafer is divided by grinding with a grindstone for backside grinding, the size of the backside chipping is changed from the conventional size of about 15 μm to about 4 μm. Getting smaller,
The bending stress value is also improved to 45 Kgf / mm 2 .
【００４２】なお、この発明は上述した第１，第２の実
施の形態に限定されるものではなく、要旨を逸脱しない
範囲で種々変形して実施可能である。例えば、溝の形成
時にウェーハ２１をダイシング用チャックテーブル２３
に固着したが、従来の方法と同様にフラットリングを粘
着性のシートに貼り付けた状態で、ウェーハをダイシン
グ用チャックテーブルに固定するようにしても良い。あ
るいは、平板にウェーハを固定したり、平板に粘着性の
シートを用いてウェーハを固着した状態で溝を形成して
も良い。The present invention is not limited to the above-described first and second embodiments, and various modifications can be made without departing from the scope of the invention. For example, when the groove is formed, the wafer 21 is chucked on the chuck table 23 for dicing.
However, as in the conventional method, the wafer may be fixed to the chuck table for dicing while the flat ring is attached to the adhesive sheet. Alternatively, the wafer may be fixed to the flat plate, or the groove may be formed while the wafer is fixed to the flat plate by using an adhesive sheet.
【００４３】また、ウェーハ２１のパターン形成面２１
´を粘着性のシート（表面保護テープ２６）に貼り付け
るようにしたが、ウェーハ２１のパターン形成面２１´
と粘着性のシートとの間に極薄のフィルムを介在させて
も良い。例えば、ウェーハのパターン形成面にシリテク
ト−IIと呼ばれる液体をスプレーで吹き付けて被膜を形
成した後、粘着性のシートを貼り付ける。あるいは、平
板上に両面あるいは片面の粘着テープを貼り付け、その
上にウェーハを固着するようにしても良い。The pattern forming surface 21 of the wafer 21
′ Was attached to an adhesive sheet (surface protection tape 26), the pattern forming surface 21 ′ of the wafer 21
An extremely thin film may be interposed between the adhesive sheet and the adhesive sheet. For example, a liquid called Ciritect-II is sprayed on the pattern formation surface of the wafer to form a film, and then an adhesive sheet is attached. Alternatively, a double-sided or single-sided adhesive tape may be attached on a flat plate, and the wafer may be fixed thereon.
【００４４】更に、チップを表面保護テープから剥離す
るためにピックアップニードルを用いたが、ピックアッ
プニードルの代わりにチップ裏面をバキュームで吸着
し、表面保護テープから剥離するようにしても良い。Further, although the pickup needle was used for peeling the chip from the surface protection tape, instead of the pickup needle, the back surface of the chip may be sucked by vacuum and peeled from the surface protection tape.
【００４５】[0045]
【発明の効果】以上説明したように、この発明によれ
ば、薄厚研削時や搬送時のウェーハの割れを抑制できる
ウェーハの分割方法及び半導体装置の製造方法が得られ
る。また、製造工程とコストの削減が図れるウェーハの
分割方法及び半導体装置の製造方法が得られる。更に、
ウェーハの裏面側のチッピングを小さくでき、チップの
抗折応力の低下を抑制できるウェーハの分割方法及び半
導体装置の製造方法が得られる。As described above, according to the present invention, there can be obtained a wafer dividing method and a semiconductor device manufacturing method capable of suppressing the cracking of the wafer during thin-thickness grinding or during transportation. Further, there can be obtained a wafer dividing method and a semiconductor device manufacturing method capable of reducing the manufacturing process and cost. Furthermore,
A method of dividing a wafer and a method of manufacturing a semiconductor device can be obtained which can reduce chipping on the back surface side of a wafer and can suppress a decrease in bending stress of a chip.
【図１】この発明の第１の実施の形態に係る半導体装置
の製造方法について説明するためのもので、ダイシング
ラインに沿ってウェーハに溝を形成する工程を示す図。FIG. 1 is a view for explaining a method of manufacturing a semiconductor device according to a first embodiment of the present invention, showing a step of forming a groove in a wafer along a dicing line.
【図２】この発明の第１の実施の形態に係る半導体装置
の製造方法について説明するためのもので、ウェーハに
表面保護テープを貼り付ける工程を示す図。FIG. 2 is a view for explaining the method of manufacturing the semiconductor device according to the first embodiment of the present invention, showing a step of attaching a surface protection tape to a wafer.
【図３】この発明の第１の実施の形態に係る半導体装置
の製造方法について説明するためのもので、ウェーハ裏
面の研削及び研磨工程（分割工程）を示す図。FIG. 3 is a view for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention, which shows a grinding and polishing step (dividing step) on the back surface of a wafer.
【図４】この発明の第１の実施の形態に係る半導体装置
の製造方法について説明するためのもので、分離したチ
ップをピックアップする工程を示す図。FIG. 4 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a step of picking up separated chips.
【図５】この発明の第１の実施の形態に係る半導体装置
の製造方法について説明するためのもので、ダイボンデ
ィング工程を示す図。FIG. 5 is a view for explaining the method of manufacturing the semiconductor device according to the first embodiment of the invention, showing a die bonding step.
【図６】この発明の第１の実施の形態に係る半導体装置
の製造方法について説明するためのもので、外囲器に封
止する工程を示す図。FIG. 6 is a view for explaining the method for manufacturing the semiconductor device according to the first embodiment of the present invention, showing a step of sealing in an envelope.
【図７】従来とこの発明の方法でウェーハを個々のチッ
プに分離した時の研削面の拡大図。FIG. 7 is an enlarged view of a ground surface when a wafer is separated into individual chips by the conventional method and the method of the present invention.
【図８】この発明の第２の実施の形態に係る半導体装置
の製造方法について説明するためのもので、この発明を
ＬＯＣパッケージに適用した時の半導体装置の断面図。FIG. 8 is a cross-sectional view of a semiconductor device when the present invention is applied to a LOC package, for explaining the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
【図９】従来の半導体装置の製造方法について説明する
ためのもので、ウェーハの表面保護テープを貼り付ける
工程を示す図。FIG. 9 is a view for explaining a conventional method for manufacturing a semiconductor device, showing a step of attaching a wafer surface protection tape.
【図１０】従来の半導体装置の製造方法について説明す
るためのもので、ウェーハの裏面の研削及び研磨工程を
示す図。FIG. 10 is a view for explaining a conventional method for manufacturing a semiconductor device, showing the steps of grinding and polishing the back surface of a wafer.
【図１１】従来の半導体装置の製造方法について説明す
るためのもので、表面保護テープを剥がす工程を示す
図。FIG. 11 is a view for explaining a conventional method for manufacturing a semiconductor device, showing a step of peeling a surface protection tape.
【図１２】従来の半導体装置の製造方法について説明す
るためのもので、ウェーハを固定用シートに固着する工
程を示す図。FIG. 12 is a view for explaining a conventional method for manufacturing a semiconductor device, showing a step of fixing a wafer to a fixing sheet.
【図１３】従来の半導体装置の製造方法について説明す
るためのもので、ウェーハのダイシング工程を示す図。FIG. 13 is a view for explaining a conventional method for manufacturing a semiconductor device, showing a wafer dicing process.
【図１４】従来の半導体装置の製造方法について説明す
るためのもので、分離したチップをピックアップする工
程を示す図。FIG. 14 is a view for explaining a conventional method for manufacturing a semiconductor device, showing a step of picking up separated chips.
【図１５】従来の半導体装置の製造方法について説明す
るためのもので、ダイボンディング工程を示す図。FIG. 15 is a view for explaining a conventional method for manufacturing a semiconductor device, showing a die bonding step.
２１…ウェーハ、２１´…パターン形成面、２２…溝、
２３…ダイシング用チャックテーブル、２４…ダイシン
グ用ブレード、２５…フラットリング、２６…表面保護
テープ（粘着性のシート）、２７…裏面研削用チャック
テーブル、２８…裏面研削用砥石、２９…チップ、３０
…ピックアップニードル、３１…アイランド、３２…ダ
イボンディング用接着剤、３３…樹脂パッケージまたは
セラミックパッケージ（外囲器）、３４…リードフレー
ム、３５…ボンディングワイヤ、３６…接着テープ、３
７…リード。21 ... Wafer, 21 '... Pattern forming surface, 22 ... Groove,
23 ... Dicing chuck table, 24 ... Dicing blade, 25 ... Flat ring, 26 ... Surface protective tape (adhesive sheet), 27 ... Back grinding chuck table, 28 ... Back grinding wheel, 29 ... Chip, 30
... Pickup needle, 31 ... Island, 32 ... Die bonding adhesive, 33 ... Resin package or ceramic package (enclosure), 34 ... Lead frame, 35 ... Bonding wire, 36 ... Adhesive tape, 3
7 ... Lead.
フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 ＦＩ 技術表示箇所 Ｈ０１Ｌ 21/78 Ａ (72)発明者 徳渕 圭介 神奈川県川崎市幸区小向東芝町１番地 株 式会社東芝多摩川工場内Continuation of the front page (51) Int.Cl. 6 Identification number Reference number within the agency FI Technical display location H01L 21/78 A (72) Inventor Keisuke Tokubuchi 1 Komukai Toshiba-cho, Kawasaki-shi, Kanagawa Prefecture Toshiba Corporation Inside the Tamagawa factory
Claims (6)
シングラインに沿って上記半導体素子の形成面側から所
定の深さの溝を形成する工程と、上記ウェーハにおける
半導体素子の形成面上に保持用のシートを貼り付ける工
程と、上記ウェーハの裏面を上記溝に達するまで研削及
び研磨し、ウェーハを個々のチップに分離する工程とを
具備することを特徴とするウェーハの分割方法。1. A step of forming a groove having a predetermined depth from a side of a surface on which the semiconductor element is formed along a dicing line of the wafer on which the semiconductor element is formed, and a step of holding the groove on the surface of the wafer on which the semiconductor element is formed. And a step of grinding the back surface of the wafer until it reaches the groove to separate the wafer into individual chips.
る工程と、ダイシングラインに沿って上記ウェーハの主
表面側から所定の深さの溝を形成する工程と、上記ウェ
ーハの主表面上に粘着性のシートを貼り付ける工程と、
上記ウェーハの裏面を上記溝に達するまで研削及び研磨
し、ウェーハを個々のチップに分離する工程と、分離し
た各チップを上記粘着性のシートから剥離して外囲器に
封止する工程とを具備することを特徴とする半導体装置
の製造方法。2. A step of forming a semiconductor element on the main surface of a wafer, a step of forming a groove having a predetermined depth from the main surface side of the wafer along a dicing line, and an adhesive on the main surface of the wafer. The process of pasting the sexuality sheet,
Grinding and polishing the back surface of the wafer until reaching the groove, separating the wafer into individual chips, and separating each separated chip from the adhesive sheet and sealing it in an envelope. A method for manufacturing a semiconductor device, comprising:
ートから剥離して外囲器に封止する工程は、ピックアッ
プニードルを前記粘着性のシートを介して前記チップの
主表面に当てて押圧することにより前記チップを粘着性
のシートから剥離し、チップ毎に外囲器に封止するもの
であることを特徴とする請求項２に記載の半導体装置の
製造方法。3. The step of peeling each of the separated chips from the adhesive sheet and sealing the envelope in an envelope is performed by pressing a pickup needle against the main surface of the chip via the adhesive sheet. The method of manufacturing a semiconductor device according to claim 2, wherein the chip is peeled from the adhesive sheet by the above, and each chip is sealed in an envelope.
ートから剥離して外囲器に封止する工程は、前記粘着性
のシートから剥離したチップをリードフレームのアイラ
ンドにマウントし、上記リードフレームのインナーリー
ド部と前記チップの各パッドとをワイヤボンディングし
た後、外囲器に封止するものであることを特徴とする請
求項２または３に記載の半導体装置の製造方法。4. The step of peeling each of the separated chips from the adhesive sheet and sealing in an envelope is performed by mounting the chips separated from the adhesive sheet on an island of a lead frame, 4. The method of manufacturing a semiconductor device according to claim 2, wherein the inner lead portion of the frame and each pad of the chip are wire-bonded and then sealed in an envelope.
ートから剥離して外囲器に封止する工程は、前記粘着性
のシートから剥離したチップの主表面上にリードの一端
を接着し、上記リードと前記チップの各パッドとをワイ
ヤボンディングした後、外囲器に封止するものであるこ
とを特徴とする請求項２または３に記載の半導体装置の
製造方法。5. The step of peeling each of the separated chips from the adhesive sheet and sealing in an envelope is performed by adhering one end of a lead on the main surface of the chip peeled from the adhesive sheet. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the lead and each pad of the chip are wire-bonded and then sealed in an envelope.
在される接着テープを更に備え、前記接着テープの厚さ
は、前記ウェーハの裏面の研削及び研磨工程で発生する
シリコン屑よりも厚いことを特徴とする請求項５に記載
の半導体装置の製造方法。6. The device further comprises an adhesive tape interposed between the main surface of the chip and the lead, and the thickness of the adhesive tape is thicker than silicon debris generated in the grinding and polishing process of the back surface of the wafer. The method for manufacturing a semiconductor device according to claim 5, wherein
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8016037A JPH09213662A (en) | 1996-01-31 | 1996-01-31 | Method of splitting wafer and method of manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8016037A JPH09213662A (en) | 1996-01-31 | 1996-01-31 | Method of splitting wafer and method of manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09213662A true JPH09213662A (en) | 1997-08-15 |
Family
ID=11905392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8016037A Pending JPH09213662A (en) | 1996-01-31 | 1996-01-31 | Method of splitting wafer and method of manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09213662A (en) |
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