JPH09198866A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent input/output terminals of a CPU and a semiconductor storage device from being short-circuited in a dummy read cycle immediately after a power supply is turned on and to prevent an overcurrent from being generated. SOLUTION: A write detection circuit 2 receives the inverse of a row address strobe(AS) signal, the inverse of a column address strobe(CAS) signal and the inverse of a write enable (WE) signal, it detects a write cycle, and it permits the input of a control signal to an output circuit 3 from an output control circuit 1 after the write cycle has been detected. Consequently, before a first write cycle is performed immediately after a power supply is turned on, i.e., in a dummy read cycle, the write cycle detection circuit 2 inhibits the control signal from being input to the output circuit 3 even when the control signal is output from the output control circuit 1. Consequently, in the dummy read cycle, it is possible to prevent a CPU and a semiconductor storage device from being short-circuited when the output circuit 3 activates so as to output indefinite data, and it is possible to prevent an overcurrent from being generated due to its output short circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a write cycle in which data can be written,
The present invention relates to improvement of a semiconductor memory device having a read cycle capable of reading data.

[0002]

2. Description of the Related Art FIG. 4 shows a conventional semiconductor memory device. In the figure, 1 is an output control circuit and 3 is an output circuit.

The output control circuit 1 is provided with a / RAS (Row Address Strobe) signal and / CAS (C
It is controlled by the optical address strobe) signal, the / WE (Write Enable) signal, and the / OE (Output Enable) signal, and the output control signal is input to the output circuit 3 through the node F.

As can be seen from the timing chart shown in FIG. 5, the semiconductor memory device configured as described above controls the output when both the / RAS signal and the / CAS signal become "L" level after the rise of the power supply Vcc. The circuit 1 outputs a control signal, the output circuit 3 is activated in response to this, and predetermined data is output.

[0005]

In a system equipped with a semiconductor memory device or CPU having the above-described structure, generally, a write cycle for writing desired data in the semiconductor memory device and a read cycle for reading data from the semiconductor memory device are performed. And the control signals (/ RAS signal, / CAS signal, / WE signal, and / OE signal) so that
A circuit (hereinafter referred to as a control IC) for supplying a signal) to the output control circuit 1 is provided. In the above system, the data input / output terminal of the semiconductor memory device is directly connected to the data input / output terminal of the CPU via the data line on the system.

In the system as described above, when the power of the system is turned on, the circuit components on the system including the semiconductor memory device are also turned on, and thereafter,
The system is initialized. At this time, a memory check is performed on the semiconductor memory device to confirm whether data writing and reading are normally performed. However, depending on the system, from the time the power is turned on to the time before the memory check is started. From the control IC in the period / RA
In some cases, the S, / CAS, and / WE signals are output to execute a dummy read cycle (a read cycle that is performed especially when not intended to read data).

However, in the conventional semiconductor memory device, the output control circuit 1 receives a control signal from the control IC in the dummy read cycle and operates in the same manner as in the normal read cycle, and as a result, the output circuit 3 When activated, it outputs undefined data (“H” or “L” level). At this time, the CPU also outputs indefinite data before initialization, and if this data is the inversion level of the indefinite data from the output circuit 3, the CPU and the semiconductor memory device are short-circuited, causing an output short circuit. Excessive current is generated,
As a result, there are drawbacks that power consumption may increase and latch-up may occur.

The present invention solves the above-mentioned conventional problems, and an object thereof is to inhibit data output in a dummy read cycle immediately after power-on in a semiconductor memory device.

[0009]

To achieve the above object, according to the present invention, until the first write cycle after the power is turned on, the output control circuit outputs the output circuit by detecting the first write cycle. The output of control signals to is prohibited.

That is, in the semiconductor memory device according to the first aspect, in the semiconductor memory device having a write cycle in which data can be written and a read cycle in which data can be read, data is read in a read cycle immediately after power-on. It is characterized in that an output prohibiting means for prohibiting output is provided.

According to another aspect of the semiconductor memory device of the present invention, an output control circuit for controlling the reading and writing of data by receiving the / RAS signal, the / CAS signal and the / WE signal, and the output control circuit. A semiconductor memory device provided with an output circuit activated upon receiving a control signal is characterized by comprising an output prohibiting means for prohibiting data output from the output circuit in a read cycle immediately after power-on.

Further, in the invention according to claim 3, in the semiconductor memory device according to claim 1 or 2, the output prohibiting means detects that at least one write cycle has been performed after power-on. And a write cycle detection circuit for

In addition, in the invention according to claim 4, in the semiconductor memory device according to claim 3, before the write cycle detection circuit detects that at least one write cycle has been performed after power-on. Is characterized in that the control signal of the output control circuit is prohibited from being input to the output circuit.

Further, in the invention described in claim 5, in the semiconductor memory device according to claim 3, the write cycle detection circuit detects that at least one write cycle has been performed after power-on. After that, the control signal of the output control circuit is allowed to be input to the output circuit, and arbitrary data output from the output circuit in the subsequent read cycle is allowed.

With the above configuration, in the inventions according to claims 1 to 5, even if a read cycle (dummy read cycle) is performed after the power is turned on and before one or more write cycles are detected, the output control circuit. Outputs a control signal, but the input of the control signal to the output circuit is prohibited, so that data is not output, thus preventing malfunction.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a semiconductor memory device according to an embodiment of the present invention. In the figure, 1 is an output control circuit,
Reference numeral 2 is a write cycle detection circuit (output prohibiting means), and 3 is an output circuit.

The output control circuit is 1, / RAS signal, /
It is controlled by the CAS signal, / WE signal and / OE signal. The write cycle detection circuit 2 uses the / RAS signal,
The / CAS signal and the / WE signal are input and connected to the output control circuit 1 through the node A. The write cycle detection circuit 2 is connected to the output circuit 3 through the node B. A pair of data lines D and / D are connected to the output circuit 3.

FIG. 2 shows the details of the write cycle detection circuit 2 and the output circuit 3. In the write cycle detection circuit 2 of the figure, the / RAS signal, the / CAS signal, and the inverted signal of the / WE signal are input to the NOR gate 11, and the NO
The inverted signal of the output of the R gate 11
It is input to one input terminal of the D gate 12. The AN
The output of the D gate 12 is input to one input terminal of the NAND gate 13 through the node E, the output of the NAND gate 13 is input to one input terminal of the NAND gate 14 through the node C, and The inverted signal of the output is input to the other input terminal of the AND gate 12. The node C has a capacity of 15
Through the ground. The output of the NAND gate 14 is input to the other input terminal of the NAND gate 13 and the output circuit 3 through the node B. The NAND gate 14
The output of the output control circuit 1 is input through the node A to the other input terminal.

The output circuit 3 of FIG. 2 includes a P-channel MOS transistor 20 arranged between the power supply and the output terminal 3a, and an N-channel MOS transistor 21 arranged between the output terminal 3a and the ground. , The P channel MO
First NAN connected to the gate of the S transistor 20
D circuit 22 and the N-channel MOS transistor 21
Of the second N connected to the gate of
AND circuit 24. The first NAND circuit 2
2 includes a node B of the write cycle detection circuit 2 and
The second data line D is connected to the second NAN.
The node B of the write cycle detection circuit 2 and the other data line / D are connected to the D circuit 24. An N-channel MOS transistor 25 is connected between the one data line D and the ground, and the other data line / D is connected to the gate thereof. Similarly, the other data line /
N-channel MOS transistor 26 is also connected between D and ground.
Are connected, and the one data line D is connected to the gate thereof.

Next, the operation of the semiconductor memory device configured as described above will be described below.

First, after the power is turned on, the node C has a capacity of 15
As a result, the rising edge is delayed and becomes "L" level. Therefore, the output node B of the NAND gate 14 becomes "H" level. The inverted signal of the node C, that is, the "H" level is input to the other input terminal of the AND gate 12. At this time, if there is no write cycle, NO
"H" level is input to the input terminal of the R gate 11,
The output node D becomes "L" level. AND gate 12
One of the input terminals has an inverted signal of the node D, that is, "
The "H" level is input, and the output node E of the AND gate 12 becomes the "H" level. Therefore, the NAND gate 1
The output of 3 becomes "L" level and is latched. Therefore, the output node A of the output control circuit 1 is "H" or "L".
The node B is latched at the "H" level regardless of the level.

After that, when there is one or more write cycles (/ RAS signal is at "L" level, / CAS signal is at "L" level, / WE signal is at "H" level), the output node D of the NOR gate 11 is It becomes "H" level and AND
The inverted signal of the node D is input to one input terminal of the gate 12, the output node E of the AND gate 12 becomes "L" level, and the output of the NAND gate 13 becomes "H" level. As a result, the "L" level is input to the other input terminal of the AND gate 12, the node E becomes "L" level, and the node C is latched at "H" level. Therefore, the output circuit 3 is controlled by the control signal from the output control circuit 1 after the detection of one or more of the write cycles.

As described above, in the present embodiment, the write cycle detection circuit 2 is provided to allow the data output from the output circuit 3 only after the write cycle is detected once or more after the power is turned on. Even if a dummy read cycle was previously performed, no data is output, so
It is possible to prevent an excessive current from being generated due to a short circuit between the input / output terminals of the CPU and the semiconductor memory device during the dummy read cycle.

[0025]

As described above, according to the semiconductor memory device of the first to fifth aspects of the present invention, the write cycle detection circuit is provided and the CPU and the semiconductor in the dummy read cycle immediately after power-on. It is possible to prevent a short circuit between both the input and output terminals of the storage device and prevent an increase in power consumption due to the short circuit current and a latch-up.

[Brief description of drawings]

FIG. 1 is a diagram showing a block configuration of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific example of a write cycle detection circuit of the present invention.

FIG. 3 is a timing chart showing the operation of the semiconductor memory device according to the embodiment of the present invention.

FIG. 4 is a diagram showing a block configuration of a conventional semiconductor memory device.

FIG. 5 is a timing chart showing the operation of the conventional semiconductor memory device.

[Explanation of symbols]

 1 Output Control Circuit 2 Write Cycle Detection Circuit 3 Output Circuit 11 NOR Gate 12 AND Gate 13 NAND Gate 14 NAND Gate 15 Capacitance

Claims (5)

[Claims] 1. A semiconductor memory device having a write cycle in which data can be written and a read cycle in which data can be read is provided with an output inhibiting means for inhibiting data output in a read cycle immediately after power-on. A semiconductor memory device characterized by the above. 2. / RAS signal, / CAS signal and / WE
In a semiconductor memory device including an output control circuit that receives a signal and controls reading and writing of data, and an output circuit that is activated by receiving a control signal from the output control circuit, in a read cycle immediately after power-on Is a semiconductor memory device comprising an output inhibiting means for inhibiting data output from the output circuit. 3. The semiconductor memory according to claim 1, wherein the output prohibiting means comprises a write cycle detecting circuit for detecting that at least one write cycle has been performed after the power is turned on. apparatus. 4. The write cycle detection circuit prohibits the control signal of the output control circuit from being input to the output circuit before detecting that at least one write cycle has been performed after the power is turned on. 4. The semiconductor memory device according to claim 3, wherein 5. The write cycle detection circuit allows the control signal of the output control circuit to be input to the output circuit after detecting that at least one write cycle has been performed after the power is turned on. 4. The semiconductor memory device according to claim 3, wherein any data output from the output circuit in the subsequent read cycle is permitted.