JP3530402B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having an electrically rewritable non-volatile semiconductor memory which needs to be supplied with a high voltage for writing from the outside in a write mode. is there. In addition,
In the present invention, the “semiconductor integrated circuit device having a built-in non-volatile memory” means “a non-volatile semiconductor memory device having only a memory function” and “a non-volatile memory is built in as a program memory or a data memory”. It is defined as including both "a semiconductor integrated circuit device such as a microcomputer".

[0002]

2. Description of the Related Art Non-volatile memories such as flash memories are characterized by electrically rewriting data and retaining data even when the power is turned off, and are currently used in various fields and applications. It is also used, for example, for storing a program of a microcomputer. Semiconductor integrated circuit devices with a built-in non-volatile memory are expected to expand in capacity and diversify, and the fields of application will further expand. In addition, in terms of mounting, from the viewpoints of package miniaturization and cost reduction, it is necessary to cope with the increase in the number of terminals due to the multi-functionalization, or to reduce the number of parts such as external external switches. .

In view of the above background, a test terminal for setting a test mode of a semiconductor integrated circuit device having a built-in non-volatile memory and a high voltage (Vpp) necessary for rewriting data in the non-volatile memory are applied. Consider a high voltage application terminal (Vpp terminal) for this purpose. The test terminal is for testing each functional block in the circuit, and is a terminal fixed to the ground level (GND level) in actual use. Further, the Vpp terminal is not used so much after the data is once written in the nonvolatile memory. Therefore, these terminals are
It is a terminal that is used very rarely, and from the above background,
Generally, one terminal is also used.

[0004]

By the way, when actually writing data to the non-volatile memory on the board, as shown in FIG. 3, it is fixed to GND in normal use.
It is necessary to disconnect the TEST / Vpp terminal (shared terminal) 3 of the semiconductor integrated circuit device 1 from GND once and then apply the write voltage Vpp to the terminal. Conventionally, as shown in FIG. Outside the device (LSI),
The switch 8 for switching between GND / Vpp switching or GND fixing is provided, which causes a problem that the number of parts increases and the mounting efficiency also deteriorates.

From the above, the present invention aims to eliminate the need for the above-mentioned changeover switch, and achieves the object by using the voltage detection circuit for detecting the voltage level input to the shared terminal. .

Here, a semiconductor memory device disclosed in Japanese Patent Laid-Open No. 8-87883 is reported as one using a voltage detection circuit. The configuration is shown in FIG. This is characterized by having a burn-in mode detection circuit 20 which detects that the burn-in mode has been entered by the value of the power supply voltage Vcc and outputs an output signal φBI to an internal circuit. That is, when the power supply voltage is at the Vcc level, the output signal φBI of the detection circuit 20 is at the low level, the burn-in mode is not entered, and φNORM is activated by the command decoder 10, and the switches 16 and 1 are activated.
7, the external address A0-10 and the bank address BA are transmitted to the internal circuit. In addition, in the figure, 12
Is an address buffer, and 13 is a bank address (BA) buffer.

On the other hand, when the power supply voltage is sufficiently higher than Vcc, the output signal φBI of burn-in mode detection circuit 20 becomes high level and acts on control signal buffer / command decoder 10 to cause row address strobe signal bar RAS. The output from the internal refresh address counter 14 is transmitted to the internal circuit via the switches 18 and 19 and enters the burn-in mode regardless of the level of the external input such as the column address strobe signal bar CAS. In the figure, 15 is a self-refresh timer. Also, 9
Is a clock (CLK) buffer, and 11 is a memory array control circuit.

FIG. 5 shows the above-mentioned Japanese Unexamined Patent Publication No. 8-87883.
2 is an embodiment of a voltage detection circuit (burn-in mode detection circuit) in the semiconductor memory device of FIG. That is, in FIG. 5, R2 is a high resistance having one end connected to the power supply potential Vcc and the other end connected to the node N4, and Q5 is an N channel M having its gate and drain connected to the node N4.
The OS transistor, Q6, is an N-channel M-channel whose gate and drain are connected to the source of the MOS transistor Q5.
It is an OS transistor. Similarly, a predetermined number (N
Individual) N-channel MOS transistors are connected in series,
The source of the final MOS transistor Qn is connected to the ground potential Vs.
connect to s. Further, 21 'has an input terminal as a node N4.
Is an inverter whose output is the signal φBI.

In this circuit configuration, an N channel MOS
If the threshold voltage of the transistor is Vth, the node N4
Voltage exceeds N times Vth, N-channel MOS
Since a current flows through the transistors Q5 to Qn, the voltage of the node N4 becomes low level and the inverter 21 '
The φBI signal, which is the output of, goes high.

However, the circuit described above has the power supply voltage Vc.
The purpose is to automatically operate the burn-in circuit and easily enter the burn-in mode by applying a voltage exceeding c. It is possible to increase the number of terminals by sharing the terminals in actual use and reduce the number of parts. We have not been able to deal with problems such as improved implementation efficiency.

[0011]

In order to solve the above-mentioned problems, a semiconductor integrated circuit device incorporating a nonvolatile memory according to the present invention has a test terminal having a fixed input of a ground voltage in a normal operation mode. , A semiconductor integrated circuit having a built-in electrically rewritable nonvolatile semiconductor memory, in which a write voltage input terminal to which a predetermined high voltage exceeding a power supply voltage is applied in a write operation mode is constituted by a single shared terminal The circuit device is provided with voltage detection means for detecting a high voltage input to the dual-purpose terminal and terminal state switching means for switching the state of the dual-purpose terminal in accordance with a signal output from the voltage detection means. It is characterized by that.

Further, in the semiconductor integrated circuit device having the above structure, as the terminal state switching means, a signal from the detecting means is input to its gate, its source is connected to the ground voltage, and its drain is further connected. Is provided with an N-channel MOS transistor connected to the dual-purpose terminal via a pull-down resistor.

According to the present invention having the above structure, the dual-purpose terminal (TEST / Vpp terminal) is automatically fixed to GND internally by the pull-down resistor in the normal mode, so that it is not necessary to fix it to GND externally. . As a result, it is not necessary to externally cut off the GND level in the write mode, and the write voltage Vpp is applied to the dual-purpose terminal.
Can be applied directly. That is, it is possible to reduce the number of external changeover switches described in the related art, reduce the number of components, and improve the mounting efficiency.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a circuit diagram according to an embodiment of the present invention. Further, FIG. 2 shows a specific configuration example of the Vpp detection circuit of FIG.

First, the Vpp detection circuit of FIG. 2 will be described. This circuit includes an N-channel MOS transistor Q
2, Q4, a P-channel MOS transistor Q3, and inverters 6 and 7.

When the TEST / Vpp terminal is at the ground potential GND, the N-channel MOS transistor Q2 and the P-channel MOS transistor Q3 do not have the driving ability, and the N-channel MOS transistor Q4 has the driving ability. It is a level. Therefore, the SAVPP signal which is the output signal of the inverter 7 becomes the GND level.

Further, when the write voltage Vpp is applied to the TEST / Vpp terminal, the N-channel MOS transistor Q2 and the P-channel MOS transistor Q3 have drive capability, and the potential of the node N3 is forced to be inverted. Since the channel MOS transistor Q4 is also in the conductive state, if the drive capability of the N-channel MOS transistor Q4 is made smaller than the drive capability of the N-channel MOS transistor Q2 and the P-channel MOS transistor Q3, it will become the N-channel MOS transistor Q2. The drive capability of the P-channel MOS transistor Q3 is
The potential of the node N3 is inverted by exceeding the drive capability of the N-channel MOS transistor Q4, and as a result, the output signal SAVPP of the inverter 7 becomes the Vcc level.

That is, this Vpp detection circuit is
The voltage input from the T / Vpp terminal is detected, and when the input voltage is the voltage Vpp exceeding the voltage Vcc, the output signal SA
VPP outputs a Vcc level, and when the input voltage is Vcc or less, the output signal SAVPP outputs a GND level.

Next, the circuit of one embodiment of the present invention shown in FIG. 1 will be described. This circuit is a Vpp detection circuit 2,
It is composed of an inverter 4, an input buffer 5, a resistor R1, and an N-channel MOS transistor Q1.

Further, the N-channel MOS transistor Q1
Has a source connected to the ground potential GND, and a drain connected to the node N2 from the TEST / Vpp terminal 3 via the resistor R1. Further, the gate is connected to the output node N1 of the inverter 4 which receives the output signal SAVPP of the Vpp detection circuit 2 as an input. Further, the output of the input buffer 5 having the node N2 as an input is TEST.
It is a signal.

In this circuit, in the write mode, the TEST / V of the semiconductor integrated circuit device (LSI) 1 is
When the write voltage Vpp is applied to the pp terminal 3, V
The pp detection circuit 2 detects this and outputs the output signal SAVPP.
To the output node N of the inverter 4
Since 1 becomes the GND level, the N-channel MOS transistor Q1 does not have drive capability. Therefore, the internal signal Vpp supplies the write voltage Vpp to the memory core, and the internal signal TE, which is the output of the input buffer 5, is supplied.
ST supplies a voltage Vcc level which is a test mode signal. Here, the reason why the pull-down resistor is cut off when the voltage Vpp is applied is to prevent the current from increasing as a disadvantage when the pull-down resistor is included.

As described above, when the voltage Vpp is applied, the voltage level Vcc is supplied to the internal signal TEST. In the write mode, the memory cell (not shown) performs the same operation as in the test mode such as verifying. Therefore, in addition to supplying the write voltage Vpp to the memory core, the voltage Vcc is also supplied to the internal signal TEST. Is.

On the other hand, in the normal mode, TEST / Vpp
Since the terminal 3 is fixed to the ground potential GND, the internal node N2 and the internal signal TEST are at the GND level. However, in this circuit, the same effect can be obtained even when nothing is input to the TEST / Vpp terminal 3. That is, at this time, since the output signal SAVPP of the Vpp detection circuit 2 becomes the GND level and the node N1 becomes the Vcc level, the N-channel MOS transistor Q1 has the drive capability and the internal node N2 is fixed at the GND level. .

A technical idea of the present invention is that a nonvolatile semiconductor memory having a signal input terminal (address signal input terminal, data signal input terminal, or control signal input terminal) and a dual-purpose terminal that is also used as a high-voltage input terminal. It can be effectively implemented even in a built-in semiconductor integrated circuit device.

FIG. 6 shows a circuit diagram in that case. This circuit includes a Vpp detection circuit 2, an inverter 4, and an input buffer with an enable terminal (row active input buffer) 2.
1, resistor R1, and N-channel MOS transistor Q1
Composed of.

Further, the N-channel MOS transistor Q1
Has a source connected to the ground potential GND, and a drain connected from the IN / Vpp terminal 22 to the node N2 via the resistor R1. Furthermore, the output node N1 of the inverter 4 which receives the SAVPP signal which is the output signal of the Vpp detection circuit 2 is connected to the gate. Also,
The node N2 is an input, and the output signal S of the Vpp detection circuit 2
The output of the input buffer 21 using AVPP as an enable signal is the internal input signal IN '. The Vpp detection circuit 2 has the configuration shown in FIG.

In this circuit, IN / Vpp of the semiconductor integrated circuit device (LSI) 1 in the write mode.
When the write voltage Vpp is applied to the terminal 22, Vp
The p detection circuit 2 detects this and outputs the output signal SAVPP.
To the output node N of the inverter 4
Since 1 becomes the GND level, the N-channel MOS transistor Q1 does not have drive capability. Further, at this time, the input buffer 2 which uses the SAVPP signal as an enable signal
1 is inactive (low active). Therefore, the internal signal Vpp is the write voltage Vp to the memory core.
The write voltage Vpp is not supplied to the internal input signal IN ′ which is the output of the input buffer 21. Here, the reason why the pull-down resistor is cut off when the voltage Vpp is applied is to prevent the current from increasing as a disadvantage when the pull-down resistor is included.

On the other hand, in the normal mode, since the IN / Vpp terminal 22 is used as a normal input terminal, the level between the ground potential GND and the power supply potential Vcc is input to the terminal. At this time, since the output signal SAVPP of the Vpp detection circuit 2 is at the GND level,
Node N1 attains the Vcc level, N-channel MOS transistor Q1 has a drive capability, and input buffer 21 is activated. Therefore, the terminal 22
When the GND level is input to the internal input signal IN '
Becomes the GND level, and when the Vcc level is input to the terminal 22, the N-channel MOS transistor Q1 is in the conductive state, so that although the Vcc level is slightly lowered, the value of the resistor R1 and the transistor Q1 are reduced.
By setting the ON resistance value of 1 to an appropriate value, there is no voltage drop at the input of the input buffer 21 up to the inversion level, so the internal input signal IN output via this input buffer 21 ', The Vcc level will be output. That is, in normal mode,
The IN / Vpp terminal 22 can be used as a normal input terminal.

[0030]

As described above in detail, according to the semiconductor integrated circuit device with a built-in non-volatile memory of the present invention, the shared terminal has the write voltage Vpp in the write mode.
In the normal mode, it is fixed to GND even if nothing is given in the normal mode, which is necessary in the prior art.
The number of external changeover switches on the board can be reduced, the number of parts can be reduced, and the mounting efficiency can be improved.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a Vpp detection circuit shown in FIG.

FIG. 3 is a configuration diagram showing a conventional technique.

FIG. 4 is a block diagram showing a configuration of a semiconductor memory device disclosed in Japanese Patent Laid-Open No. 8-87883.

5 is a circuit diagram showing a configuration of a burn-in mode detection circuit shown in FIG.

FIG. 6 is a circuit diagram showing a configuration of another embodiment of the present invention.

[Explanation of reference numerals] 1 semiconductor integrated circuit device with built-in nonvolatile memory 2 Vpp detection circuit 3 TEST / Vpp terminals 4, 6, 7 inverter 5 input buffer 21 input buffer with enable terminal 22 IN / Vpp terminals Q1, Q2, Q4 N channel MOS transistor Q3 P-channel MOS transistor R1 Resistance SAVPP Vpp output signal of detection circuit

Continuation of front page (51) Int.Cl. ⁷ Identification code FI H01L 27/04 H01L 27/10 434 27/10 481 29/78 371 27/115 29/788 29/792

Claims (5)

(57) [Claims] 1. A single shared terminal serving as a test terminal having a fixed input of a ground voltage in a normal operation mode and a write voltage input terminal to which a predetermined high voltage exceeding a power supply voltage is applied in a write operation mode. In a semiconductor integrated circuit device with a built-in electrically rewritable nonvolatile semiconductor memory, the voltage detection means for detecting a high voltage input to the dual-purpose terminal, and the output from the voltage detection means. And a terminal state switching means for switching the state of the dual-purpose terminal according to a signal to be transmitted. 2. The semiconductor integrated circuit device according to claim 1, wherein, as the terminal state switching means, a signal from the detecting means is input to its gate, and its source is connected to a ground voltage. A semiconductor integrated circuit device having an N-channel MOS transistor whose drain is connected to the dual-purpose terminal through a pull-down resistor. 3. A single combined use of an input terminal for inputting a predetermined input signal in the normal operation mode and a write voltage input terminal for applying a predetermined high voltage exceeding the power supply voltage in the write operation mode. In an electrically rewritable nonvolatile semiconductor memory built-in semiconductor integrated circuit device configured by terminals, voltage detection means for detecting a high voltage input to the dual-purpose terminal, and the voltage detection means A semiconductor integrated circuit device, comprising: terminal state switching means for switching the state of the dual-purpose terminal according to an output signal. 4. The semiconductor integrated circuit device according to claim 3, wherein, as the terminal state switching means, a signal from the detecting means is input to its gate and its source is connected to a ground voltage. A semiconductor integrated circuit device having an N-channel MOS transistor whose drain is connected to the dual-purpose terminal through a pull-down resistor. 5. The semiconductor integrated circuit device according to claim 4, further comprising means for switching activation / deactivation of an input buffer connected to said dual-purpose terminal in response to a signal from said voltage detection means. A semiconductor integrated circuit device characterized by the above.