JPH0916142A - Display device - Google Patents

Abstract

PURPOSE: To provide a multi-sync type device which copes with different resolutions irrespective of the number of physical pixels on a display panel. CONSTITUTION: The display device is provided with a display panel which has a specified number of display dots and displays the display signals for one inputted screen in synchronization with specified internal vertical synchronization signals, a signal generating means 2 which generates internal vertical synchroinlzation signals, a first to a third memories 3-5 which have the same number of memory capacities as the total number of dots of the display panel 1, a writing means 6 which writes display signals to one of the first to third memories 3-5, and changes the memory to which the signals are written to a free memory that is not used yet for both of reading and writing when the external vertical synchronization signal changes and a readout means 7 which selectively reads the display signals having been written into the first to third memories 3-5 to output to the display panel 1, and changes the memory from which signals have been read out to a free memory that is not used for both of reading and writing when the internal vertical synchronization signal changes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-sync compatible technique for a display device in which horizontal and vertical scanning frequencies are physically fixed. In general, the horizontal / vertical scanning frequency of a personal computer is divided into several types depending on the hardware specifications and OS. For example, the vertical scanning frequency of a certain type of personal computer is 56 Hz, while the vertical scanning frequency of a DOS / V personal computer, which is also known as a world standard, is 60 Hz. Also, if a certain type of OS is installed, it is possible to eliminate the model dependency and standardize to a predetermined frequency.
z, 60 Hz, 72 Hz ... As described above, since there are various kinds of horizontal / vertical scanning frequencies in one bit, it is not practical in terms of cost if a display device is prepared for each frequency, which is wasteful. .

[0002]

2. Description of the Related Art Therefore, a so-called "multi-sync" display, in which one display device can handle several kinds of horizontal and vertical scanning frequencies, is widely used. This type of display realizes multi-sync support by expanding the usable bandwidth of horizontal and vertical scanning frequencies.

[0003]

However, most of such conventional multi-sync displays are of CRT (Cathode Ray Tube) type and LC
It is difficult to realize such a display device as a D (liquid crystal display) or a PDP (plasma display panel). For example, in a multi-gradation PDP, gradation display is performed using a so-called “subframe method (detailed description will be given later)”. However, the horizontal / vertical scanning frequency inside this subframe method is the pixel of the panel. Since it is physically determined by the number and the method of frame division, only a single horizontal / vertical scanning frequency can be supported.

[0004]

It is therefore an object of the present invention to realize a multi-sync type display device capable of coping with different horizontal / vertical scanning frequencies regardless of the horizontal / vertical scanning frequencies inside the device.

[0005]

According to the first aspect of the present invention,
As shown in FIG. 1, the principle configuration thereof includes a display panel 1 having a predetermined number of display dots and displaying an input display signal for one screen in synchronization with a predetermined internal vertical synchronizing signal; A signal generating means 2 for generating a synchronization signal, first to third memories 3 to 5 having at least the same number of storage capacities as the total number of dots of the display panel 1, and display signals supplied from the outside to the first to third memories. 3 When writing to one of the memories 3 to 5 and the vertical synchronization signal (external vertical synchronization signal) given from the outside changes, the writing destination memory is changed to a free memory which is not used for both writing and reading. The writing means 6 to be changed and the display signals written in the first to third memories 3 to 5 are selectively read and output to the display panel 1, and the internal vertical synchronizing signal is changed. When the read source memory, the reading means 7 to change the writing and free memory not used by any of the read, characterized by comprising a.

The invention according to claim 2 has a principle configuration as shown in FIG. 2, which has a predetermined number of display dots and synchronizes the input display signal for one screen with a predetermined internal vertical synchronizing signal. A display panel 11 for displaying the same, a signal generating means 12 for generating the internal vertical synchronizing signal, and a first to first storage having a storage capacity at least equal to the total number of dots of the display panel 11.
The fourth memory 13 to 16 and a display signal given from the outside are written to one of the first to fourth memories 13 to 16 and, when the vertical synchronization signal (external vertical synchronization signal) given from the outside changes, write The writing means 17 for changing the previous memory into a free memory which is not used for any of writing and reading and a predetermined data conversion process, and a display signal written in the first to fourth memories 13 to 16 The display panel 11 is selectively read out.
And a read means 18 for changing the internal vertical synchronization signal to a free memory which is not used for any of writing and reading and predetermined signal processing when the internal vertical synchronizing signal changes. ~ Fourth
The display signals written in the memories 13 to 16 are selectively read out, subjected to predetermined signal processing and written back, and when the internal vertical synchronizing signal changes, the read-out source memory is subjected to writing and reading and predetermined signal processing. Signal processing means 19 for changing to a free memory which is not used for any of the above.

[0007]

In the invention according to claim 1, the first to third memories 3 are provided.
One of the 5 to 5 always remains as a free memory that is not used for “writing” and “reading”. Therefore, even when the periods of the internal and external vertical synchronizing signals are different, that is, even when the vertical scanning frequency given from the outside and the vertical scanning frequency of the display panel 1 are different, the same free memory is newly written to or newly read from. By making the original, it is possible to avoid the conflict between “writing” and “reading” to the same memory, and it is possible to display normally.

According to the second aspect of the invention, one of the first to fourth memories 13 to 16 is always left as a free memory that is not used for "writing", "reading" and "predetermined signal processing". . Therefore, even when the internal and external vertical scanning frequencies are different, the same free memory can be used as a new write destination, a new read source for display, or a new read source for "predetermined signal processing". , It is possible to display the normal display by absorbing the difference in frequency.

[0009]

Embodiments of the present invention will be described below with reference to the drawings. 3 to 7 are views showing an embodiment of the display device according to the invention described in claim 1. In FIG. 3, reference numeral 21 denotes a display panel. The display panel 21 has X display dots in the horizontal direction and Y display dots in the vertical direction (the total number is X × Y), and for each vertical scanning cycle of frequency f _v. Image data (display signal) having a gradation of p'bits per dot is displayed. Reference _numeral 22 is a sync signal generator as a signal generating means for generating an internal vertical sync signal of frequency f _v , and 23 is a first to third memory 23.
a storage unit including a to 23c, 24 is a data writing unit as a writing unit that writes image data given from the outside to the storage unit 23, and 25 is a reading unit that reads the image data from the storage unit 23 and outputs it to the display panel 21. Is a data read unit, and 26 is a control unit.

The storage unit 23 has at least Xm × Ym × p.
There are three memory planes each having a bit storage capacity, and each plane includes a first memory 23a and a second memory 23.
b and the third memory 23c. Here, the capacity (Xm × Ym × p) of each plane is set corresponding to the image data of the maximum resolution among the image data (display signals) given from the outside. Xm is the number of dots in the horizontal direction of the same data, Ym is the number of dots in the vertical direction of the same data, and p is the number of gradation bits per dot. The capacity (Xm × Ym × p) of each plane is the minimum capacity necessary for calculation and does not indicate the physical capacity of the memory element.
Further, p = p 'may be satisfied, or p ≠ p' may be satisfied.

The control unit 26 controls each unit of the display device on the basis of an internal vertical synchronizing signal that determines the vertical scanning period of the display panel 21, an external vertical synchronizing signal that determines the vertical scanning period of image data given from the outside, and the like. It generates and outputs various control signals necessary for operation. For example, a vertical scanning signal or the like synchronized with an internal vertical synchronization signal is output to the display panel 21, and a data read unit 25 is An image data read control signal or the like synchronized with the internal vertical sync signal is output, and a data write control signal or the like synchronized with the external vertical sync signal is output to the data write unit 24.
A memory allocation control signal synchronized with the internal vertical synchronization signal and the external vertical synchronization signal is output to the storage unit 23.

Here, the memory allocation control, which is the point of this embodiment, will be described with reference to FIG.
FIG. 4 is an example of a memory allocation control flow executed by the control unit 26. When this flow is executed, first, as the initial value, the first memory 23a is assigned to the data read unit 25, and the second memory 2 is assigned to the data write unit 26.
3b is allocated (steps 30 and 31). The initial value of allocation is an example, and the present invention is not limited to this. For example, the first memory 23a and the second memory 23b may be reversed, or the first memory 23a (or the second memory 23
The third memory 23c may be allocated instead of b).
Here, the description will proceed assuming that the above-mentioned initial values are assigned.

Next, wait for a change in the internal vertical sync signal or the external vertical sync signal (steps 32 and 33), and if a signal change is detected, the type of the signal (internal or external).
Subsequent processing is branched according to. That is, when the internal vertical synchronizing signal changes, the process branches to steps 34 to 38 to execute the "data read unit memory allocation process",
On the other hand, when the external vertical synchronizing signal has changed, the process branches to steps 39 to 43 to execute the "data write unit memory allocation process". <Data Read Unit Memory Allocation Processing> When the internal vertical synchronization signal changes, it is first checked whether or not the first memory 23a has been allocated (step 34), and if not already allocated (in other words, the first memory). If 23a is free, this first memory 23a is assigned to the data read section 25 (step 35). Alternatively, if the first memory 23a is already allocated, then the second memory 2
It is checked whether or not 3a has been allocated (step 3
6) If the second memory 23b is free, the second memory 23b is assigned to the data read unit 25 (step 37). Alternatively, if the second memory 23b is also allocated, it can be seen that the remaining third memory 23c is free.
5 (step 38). <Data Write Unit Memory Allocation Processing> When the external vertical synchronization signal changes, it is first checked whether or not the first memory 23a has been allocated (step 39), and if not already allocated (in other words, the first memory). If 23a is free, this first memory 23a is assigned to the data write unit 26 (step 40). Alternatively, if the first memory 23a is already allocated, then the second memory 2
It is checked whether or not 3a has been allocated (step 4
1) If the second memory 23b is free, the second memory 23b is assigned to the data write unit 26 (step 42). Alternatively, if the second memory 23b is also allocated, it can be seen that the remaining third memory 23c is free.
6 (step 43).

Therefore, according to this memory allocation control flow, when the external vertical synchronizing signal changes, a free memory which is not used for writing or reading is allocated to the data write unit 26, and the internal vertical synchronizing signal is also allocated. When the signal changes, a peculiar effect is obtained in which a free memory which is not used for writing or reading is allocated to the data read unit 25.

FIG. 5 shows an internal vertical synchronizing signal and an external vertical synchronizing signal.
It is a timing chart when the period of a signal is near. This
In the figure, timing T₁ (And T_Three ) Internal vertical sync
Signal changes, timing T_Two (And T_Four ) With external vertical
The sync signal is changing. T ₁ Previously initial allocation state
Then, in this initial allocation state, the data read section
25 has a first memory 25a (hereinafter referred to as “memory”)
The write unit 26 has the second memory 23b (hereinafter referred to as "there").
Allocated and allocated, free memory is the third memory 2
3c (or less).

At T ₁ , the allocated memory of the data read section 25 is changed from to, and becomes free. Next T
_{In 2} , the allocated memory of the data write unit 26 is changed from to, and becomes new free. At the next T ₃ ,
The allocated memory of the data read unit 25 is changed from to, and becomes new free. At the next T ₄ , the allocated memory of the data write unit 26 is changed from to, and becomes new free.

FIG. 6 is a timing chart when the cycle of the internal vertical synchronizing signal is shorter than the cycle of the external vertical synchronizing signal. In this figure, the internal vertical synchronizing signal changes at timing T ₁₂ (and T ₁₃ ), and timing T ₁₁ (and T ₁₄ ).
The external vertical sync signal is changing at. At T ₁₁ , the allocated memory of the data write unit 26 is changed from to,
Will be newly free. At the next T ₁₂ , the allocated memory of the data read unit 25 is changed from to, and becomes new free. At the next T ₁₃ , the allocated memory of the data read section 25 is changed from to, and becomes new free. At the next T ₁₄ , the allocated memory of the data write unit 26 is changed from to, and becomes new free.

FIG. 7 is a timing chart when the cycle of the internal vertical synchronizing signal is longer than the cycle of the external vertical synchronizing signal. In this figure, the internal vertical synchronizing signal changes at the timing T ₂₁ (and T ₂₄ ) and the timing T ₂₂ (and T ₂₃ ) changes.
The external vertical sync signal is changing at. At T ₂₁ , the allocated memory of the data read unit 25 is changed from to,
Will be newly free. At the next T ₂₂ , the allocated memory of the data write unit 26 is changed from to, and becomes new free. At the next T ₂₃ , the allocated memory of the data write unit 26 is changed from to, and becomes new free. At the next T ₂₄ , the allocated memory of the data read section 25 is changed from to, and becomes new free.

Therefore, at any timing, one memory is always free and the remaining two memories are allocated to the data read section 25 and the data write section 26, so that the cycle of the internal vertical synchronization signal and the external vertical synchronization signal is Regardless of the difference, the operation of fetching image data from the outside (writing operation to the memory by the data write unit 26)
And the operation of outputting image data to the display panel 21 (reading operation from the memory by the data reading unit 25) can be performed without any trouble, and a display device compatible with multi-sync can be obtained.

The above embodiment is an example of application to a display device of the type that directly displays image data from the outside. In this example, the number of memories is the same as the number of data write units 25 and data read units 26. 2 quotas and 1 free
Including at least three (first to third memory 2
3a to 23c), but when the invention is applied to a display device of a type in which required processing (signal processing) is performed on image data from the outside, four memories may be required.

FIGS. 8 to 11 are views showing an embodiment of the display device according to the invention as defined in claim 2, which is a display device of a type for subjecting image data from the outside to required processing (signal processing). It is an application example to. In FIG. 8, reference numeral 51 denotes a display panel. The display panel 51 has X display dots in the horizontal direction and Y display dots in the vertical direction (the total number is X × Y), and for each vertical scanning cycle of the frequency f _v. Image data (display signal) having a gradation of p'bits per dot is displayed. Reference numeral 52 is a sync signal generating section as a signal generating means for generating an internal vertical sync signal having a frequency f _v , and 53 is a first to fourth memory 53a.
Storage unit including -53d, 54 is a data writing unit as a writing unit that writes externally supplied image data to the storage unit 53, and 55 is a reading unit that reads out the image data from the storage unit 53 and outputs it to the display panel 51. A data read unit, 56 is an image data conversion unit as a signal processing unit for performing required signal processing on the image data written in the storage unit 53, and 57 is a control unit.

The storage unit 53 has four memory planes each having a storage capacity of Xm × Ym × p bits, and each of the planes has a first memory 53a, a second memory 53b, and a third memory 53b.
It is used as the memory 53c and the fourth memory 53d. Here, the capacity (Xm × Ym × p) of each plane is set corresponding to the image data of the maximum resolution among the image data (display signals) given from the outside. Xm is the number of dots in the horizontal direction of the same data, Ym is the number of dots in the vertical direction of the same data, and p is the number of gradation bits per dot. In addition,
Needless to say, the capacity of each plane (Xm × Ym ×
p) is the minimum capacity required for calculation, and does not indicate the physical capacity of the memory element.

The control unit 57 controls each unit of the display device on the basis of an internal vertical synchronizing signal which determines a vertical scanning period of the display panel 51, an external vertical synchronizing signal which determines a vertical scanning period of image data given from the outside, and the like. It generates and outputs various control signals necessary for operation. For example, a vertical scanning signal synchronized with an internal vertical synchronizing signal is output to the display panel 51, and a data reading unit 55 is output to the display panel 51. An image data read control signal or the like synchronized with the internal vertical sync signal is output, and a data write control signal or the like synchronized with the external vertical sync signal is output to the data write unit 54.
A memory allocation control signal or the like synchronized with the internal vertical synchronization signal and the external vertical synchronization signal is output to the storage unit 53, and a signal processing unit for signal processing synchronized with the internal vertical synchronization signal is output to the image data conversion unit 56. Outputs control signals, etc.

FIG. 9 shows an internal vertical synchronizing signal and an external vertical synchronizing signal.
It is a timing chart when the period of a signal is near. This
In the figure, timing T₃₁(And T₃₃) Internal vertical sync
Signal changes, timing T₃₂(And T₃₄) With external vertical
The sync signal is changing. T ₃₁Previously initial allocation state
Then, in this initial allocation state, the data read section
55 includes a first memory 53a (hereinafter referred to as "image data change").
The second memory 53b (hereinafter referred to as “the memory”) is also included in the conversion unit 56.
The data memory 54 has a third memory 53c (hereinafter referred to as "memory").
Each is allocated, free memory is the 4th memo
53d (below).

At T ₃₁ , the allocation memory of the data read unit 55 is changed from to, and the allocation memory of the image data conversion unit 56 is changed from to, so that is newly freed. At the next T ₃₂ , the data write unit 5
The allocated memory of 4 is changed from to, and is newly free. At the next T ₃₃ , the allocation memory of the data read unit 55 is changed from to, and the allocation memory of the image data conversion unit 56 is changed from to.
Will be newly free. At the next T ₃₄ , the allocated memory of the data write unit 54 is changed from to, and is newly freed.

FIG. 10 is a timing chart when the cycle of the internal vertical synchronizing signal is shorter than the cycle of the external vertical synchronizing signal. In this figure, the internal vertical synchronizing signal changes at timing T ₄₂ (and T ₄₃ ) and the external vertical synchronizing signal changes at timing T ₄₁ (and T ₄₄ ). At T ₄₁ ,
The allocated memory of the data write unit 54 is changed from to, and becomes new free. At the next T ₄₂ , the allocation memory of the data read unit 55 is changed from to, and the allocation memory of the image data conversion unit 56 is changed from to, so that is newly freed. At the next T ₄₃ , the allocation memory of the data read unit 55 is changed from to, and the allocation memory of the image data conversion unit 56 is changed from to, and is newly freed. At the next T ₄₄ , the allocated memory of the data write unit 54 is changed from to, and becomes new free.

FIG. 11 is a timing chart when the cycle of the internal vertical synchronizing signal is longer than the cycle of the external vertical synchronizing signal. In this figure, the internal vertical sync signal changes at timing T ₅₁ (and T ₅₄ ) and the external vertical sync signal changes at timing T ₅₂ (and T ₅₃ ). In T _51,
The allocation memory of the data read unit 55 is changed from to, and the allocation memory of the image data conversion unit 56 is changed from to, and is newly freed. At the next T ₅₂ , the allocated memory of the data write unit 54 is changed from to, and becomes new free. At the next T ₅₃ , the allocated memory of the data write unit 54 is changed from to, and becomes new free. At the next T ₅₄ , the allocation memory of the data read unit 55 is changed from to, and the allocation memory of the image data conversion unit 56 is changed from to, so that becomes new.

Therefore, at any timing, one memory is always free and the remaining three memories are allocated to the data read section 55, the data write section 54 and the image data conversion section 56, so that the internal vertical synchronizing signal and the external Regardless of the difference in the cycle of the vertical synchronizing signal, an operation of fetching image data from the outside (writing operation to the memory by the data write unit 54) and a required signal processing operation for the fetched image data (by the image data conversion unit 56) The signal processing operation) and the image data output operation to the display panel 51 (reading operation from the memory by the data reading unit 55) can be performed without any trouble, and a display device compatible with multi-sync can be obtained.

Here, an example of signal processing in the image data conversion unit 56 will be described. A subframe division method is known as one of the multi-gradation display technologies of a PDP having a memory function (see, for example, Japanese Patent Laid-Open No. 4-195188). In this method, one display frame is divided into eight subframes, and the ratio of the number of times of light emission in each subframe is, for example, 1: 2: 4: 8: 1.
It is set to 6: 32: 64: 128 and these subframes are used in combination according to the gradation of the image data. For example, if the gradation of image data is [1111
1111], select all subframes,
In this case, the maximum number of times of light emission (255 times or an integral multiple thereof) results in a gradation close to the white level. Or
When the gradation of the image data is [00000000], the subframe is not selected, and in this case, the number of times of light emission is the minimum (0 times), so that the gradation is close to the black level.

The maximum number of gray levels that can be displayed in such a system is from [00000000] to [1111111].
1], there are 256 gradations, and in order to express more gradations, for example, a method such as a dither method or an error diffusion method must be used together. In such a method, conversion of image data for each pixel is performed. Since the processing (signal processing) is required, if the image data conversion unit 56 of the above-described embodiment performs such a signal processing operation, the converted image data can be passed to the data read unit 55, and the multi-gradation PDP can be obtained. Can be applied to provide a preferable technique.

Table 1 below shows each of the memories (first to third memories 23a to 23a) in the above-described two embodiments, which are shown for reference.
c or capacity estimation of the first to fourth memories 53a to 53d). In each of the above embodiments, the example of application to the LCD or PDP is shown, but the present invention is not limited to this. In short, any display device can be used as long as it selectively displays pixels on the XY coordinates, and any display device can be used so that the horizontal and vertical scanning frequencies are physically determined.

[0032]

According to the invention described in claim 1, one of the first to third memories 3 to 5 can always be left as a free memory which is not used for "writing" and "reading". . Therefore, even if the periods of the internal and external vertical synchronization signals are different, by using the same free memory as a new writing destination or a new reading source, it is possible to absorb the difference in frequency and perform normal display.

According to the second aspect of the invention, the first to fourth aspects are provided.
One of the memories 13 to 16 can always be left as a free memory that is not used for “writing”, “reading”, and “predetermined signal processing”. Therefore, even when the internal and external vertical sync signal periods are different, the same free memory can be used as a new write destination, a new read source for display, or a new read source for predetermined signal processing. , It is possible to display the normal display by absorbing the difference in frequency.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of the invention according to claim 1;

FIG. 2 is a principle configuration diagram of the invention according to claim 2;

FIG. 3 is a main part configuration diagram of an embodiment of the invention described in claim 1;

FIG. 4 is a schematic flow of an embodiment of the invention described in claim 1.

FIG. 5 is a timing chart (No. 1) of the embodiment of the invention described in claim 1;

FIG. 6 is a timing chart (No. 2) of the embodiment of the invention described in claim 1;

FIG. 7 is a timing chart (No. 3) of the embodiment of the invention described in claim 1;

FIG. 8 is a main part configuration diagram of an embodiment of the invention as set forth in claim 2;

FIG. 9 is a timing chart (No. 1) of the embodiment of the invention described in claim 2;

FIG. 10 is a timing chart (No. 2) of the embodiment of the invention described in claim 2;

FIG. 11 is a timing chart (No. 3) of the embodiment of the invention described in claim 2;

[Explanation of symbols]

 1: Display panel 2: Signal generating means 3-5: First to third memory 6: Writing means 7: Reading means 11: Display panel 12: Signal generating means 13-16: First to fourth memory 17: Writing means 18: Read-out means 19: Signal processing means 21: Display panel 22: Synchronous signal generation section (signal generation means) 23a to 23c: First to third memories 24 :: Data write section (writing means) 25: Data read section ( Reading means) 51: Display panel 52: Synchronous signal generating circuit (signal generating means) 53a to 53d: First to fourth memories 54: Data writing section (writing means) 55: Data reading section (reading means) 56: Image data Converter (Signal processing means)

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 5/66 102 H04N 5/66 102Z

Claims (2)

[Claims] 1. An input 1 having a predetermined number of display dots.
A display panel for displaying display signals for the screen in synchronization with a predetermined internal vertical synchronizing signal; a signal generating means for generating the internal vertical synchronizing signal; and a storage capacity at least equal to the total number of dots of the display panel. The first to third memories and the display signal given from the outside are written in one of the first to third memories, and when the vertical synchronization signal (external vertical synchronization signal) given from the outside changes, the write destination memory Writing means for changing to a free memory that is not used for both writing and reading, and selectively reading the display signals written in the first to third memories and outputting them to the display panel, When the internal vertical sync signal changes, the read source memory is changed to a free memory that is not used for writing or reading. And a reading means for reading the display device. 2. An input 1 having a predetermined number of display dots.
A display panel for displaying display signals for the screen in synchronization with a predetermined internal vertical synchronizing signal; a signal generating means for generating the internal vertical synchronizing signal; and a storage capacity at least equal to the total number of dots of the display panel. The first to fourth memories and a display signal given from the outside are written in one of the first to fourth memories, and when the vertical synchronization signal (external vertical synchronization signal) given from the outside changes, the write destination memory Means for changing to a free memory which is not used for any of writing and reading and predetermined data conversion processing, and the display by selectively reading the display signals written in the first to fourth memories. When the internal vertical synchronizing signal is output while being output to the panel, the memory of the reading source is subjected to writing and reading and predetermined signal processing. Reading means for changing to a free memory which is not used for any of the above; and a display signal written in the first to fourth memories for selectively reading and performing predetermined signal processing and writing back, and the internal vertical A display device, comprising: a signal processing unit that changes a read source memory to a free memory that is not used for writing, reading, and predetermined signal processing when the synchronization signal changes.