JPH09244595A - Display control method, device therefor, and display system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display control technology by which a display speed can be held at 30 frames/sec or more. SOLUTION: Video information from video signal input devices 9, 10 and picture information from a central processing device are synthesized, and display is performed by a display device 20 having a storing characteristic of a display state based on this synthesized information (display data). A scanning region (partial rewriting line flag information) in which update is performed in the picture information is detected, a scanning region of video information and its size (video data region information) in the synthesized information is detected, information updated out of the video information and the picture information is preferentially outputted to the display device based on the detected each scanning region and size Then, the preferential output is realized by differentiating the number of interlaces among a scanning region updated in the video information, a scanning region updated in the picture information, and the other scanning region, further, the number of interlaces in its scanning region is decided in accordance with magnitude of a scanning region of the video information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control technique, and more specifically, to a display capable of maintaining a display state updated by applying an electric field or the like by using, for example, a ferroelectric liquid crystal as an operating medium for updating the display. The present invention relates to a control technology of a display device including an element.

[0002]

2. Description of the Related Art Generally, a display device is used in an information processing system or the like as an information display means for performing a visual expression function of information. As such a display device, a CR is used.
T display devices are widely known. However, since the CRT requires a certain length in the thickness direction of the display screen, the CRT has a large volume as a whole, and it is difficult to reduce the size of the entire display device. In addition, this allows such CR
The degree of freedom in using the information processing system using T as a display, that is, the degree of freedom in installation location, portability, etc., is impaired.

To compensate for this point, a liquid crystal display (hereinafter, LCD: Liquid Crystal Disp) is used.
lay) can be used. That is, LC
According to D, the entire display device can be downsized (particularly thin). In such LCD, the above-mentioned ferroelectric liquid crystal (hereinafter, referred to as FLC: Ferroelectric
Display using a liquid crystal cell of ic Liquid Crystal (hereinafter, FLCD: FLC Disp)
lay), and one of the characteristics is that the liquid crystal cell has a storage property of a display state with respect to application of an electric field. That is, in the FLCD, the liquid crystal cell is sufficiently thin, and the elongated FLC molecules therein are oriented in the first stable state or the second stable state depending on the direction of application of the electric field. Also maintain their respective alignment states. Due to the bistability of the FLC molecule, the FLCD
Has memory. Details of such FLC and FLCD are described in, for example, Japanese Patent Application No. 62-76357.

As a result, when driving the FLCD,
Unlike CRTs and other liquid crystal displays, there is a time margin in the cycle of continuous refresh drive of the display screen.
Apart from the continuous refresh driving, partial rewriting driving for updating the display state of only the portion corresponding to the change on the display screen becomes possible.

In the FLCD, in accordance with a display information output request signal output from the display device, a line address corresponding to the number of lines in the vertical direction of the display screen and pixel information of the lines are output to perform partial rewriting drive, The apparent display speed is improved.

In recent years, a central processing unit (hereinafter, referred to as host CPU: Central Processing Un
(It)) has dramatically increased the processing speed, and the number of applications that display moving images on personal computers has increased remarkably. As an example thereof, there is a video capture system that synthesizes a video signal from a video camera, a video disc player, or the like with image information of a personal computer and outputs it on a display device.

[0007]

The partial rewriting control means in the video capture system was previously filed by the present applicant as Japanese Patent Application No. 7-13784. By using the means proposed by this, it becomes possible to preferentially display the video information input from the video signal input device by the partial rewrite control, but in order to maintain a better display quality, It is necessary to keep the information display speed at 30 frames / second or more. However, the means to achieve this remain unsolved.

The present invention has been made based on the above-mentioned viewpoint, and it is an object of the present invention to provide a display control technique capable of maintaining the display speed at 30 frames / second or more.

[0009]

To achieve this object, in the present invention, the video information from the video signal input device and the image information from the central processing unit are combined, and the display state is based on this combined information. In a display control method and device for displaying by a display device having a memory property of, detecting a scanning region to be updated in the image information,
Detecting a scanning area of video information in the composite information,
The size of the scanning area is detected from the scanning area of the video information, and based on the detection result by the first to third detecting means, priority is given to the one of the video information and the image information whose display is updated. The output is intentionally output to the display device. In this priority output, the interlace number is made different between the scanning area updated by the video information, the scanning area updated by the image information, and the other scanning areas, and the scanning of the video information is further performed. This is done by determining the number of interlaces in the scanning area according to the size of the area.

According to this, the scanning area updated by the video information, the scanning area updated by the image information,
Since the number of interlaces is made different from that of the other scanning areas and the number of interlaces in that scanning area is determined according to the size of the scanning area of the video information, the apparent display update speed is 30 frames / It can be maintained for more than a second, and it is possible to obtain a high-quality display screen that makes full use of the partial rewriting control that is a feature of FLCD.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a block diagram of an entire information processing system in which an FLC display device having a display control device (display controller) according to an embodiment of the present invention is used as a display device of a video capture system. Is.

In the figure, reference numeral 1 is a host CPU which controls the entire information processing system, and 210 is a bridge which serves as an interface between the host CPU 1 and the high speed bus 2. Reference numeral 5 denotes a DRAM, which is used as a main memory, stores a control program executed by the host CPU 1, and is used as a work area during control processing by the host CPU 1. 2 is address bus, control bus,
A high-speed bus including a data bus, for example, a PCI bus. 3 is a medium speed bus, for example, an ISA bus, and the high speed bus 2 and the medium speed bus 3 are connected by a bridge 211. Reference numeral 4 denotes a ROM that stores a program or the like for performing initialization processing of the entire system. Reference numeral 19 is a display controller (FLCD interface unit)
It controls the interface with the LCD 20 and the interface with the video interface 8. Reference numeral 9 is a video disc player for reproducing a video disc, and 10 is a video camera for capturing video information. The video information captured by the video disc player 9 or the video camera 10 is transferred to the display controller 19 via the video interface 8 and reproduced on the FLCD 20.

Next, the portion connected to the medium speed bus 3 will be described. An I / O controller 11 has a parallel or serial interface and also has a disk interface function for the hard disk device 12 and the floppy disk device 13. Reference numeral 16 denotes a keyboard (KBD) controller, which controls an interface between a character 17 such as characters and numbers, a keyboard 17 for other input, and a mouse 18 which is a pointing device. Reference numeral 14 is a real-time clock, which also has a timer function for counting time by counting clocks. Reference numeral 15 is an audio subsystem, which receives a voice signal from a microphone and outputs the medium speed bus 3
Or output as an audible signal to the speaker based on the signal from the bus 3. The FLCD 20
Is an FLCD (FLC that can be configured using the display disclosed in, for example, JP-A-63-243993.
Display).

In the information processing system in which the various devices described above are connected, generally, the user of the system is
The operation is performed while responding to various information displayed on the display screen of the LCD 20. That is, the characters and image information supplied from the hard disk 12, the floppy disk 13, the keyboard 17 and the mouse 18, and the operation information related to the user's system operation stored in the ROM 4 and the main memory (DRAM) 5 are stored in the FLCD 20. The information is displayed on the display screen, and the user edits information and gives instructions to the system while viewing this display. Here, each of the above-mentioned various devices and the like constitutes display information supply means for the FLCD 20.

FIG. 2 shows the video interface 8 and FLC.
3 is a block diagram showing a connection example of a D interface unit 19. FIG. As shown in the figure, the FLCD interface unit 19 of this embodiment uses an SVGA 191 that uses an existing SVGA that is a display control circuit for a CRT. S
The configuration of the VGA 191 will be described with reference to FIG.

In FIG. 3, the host CPU 1 is a FLC.
In the display memory window area of the D interface unit 19, the rewriting display data to be accessed for writing is transferred via the high speed bus 2, and the FIFO (1) 1
It is temporarily stored in 911. Further, bank address data for projecting the display memory window area onto an arbitrary area of the VRAM (1) 192 is also transferred via the high speed bus 2. The image data has a form of 24-bit data representing 256 gradations for each of R, G and B. Host C
The control information such as the command from the PU1 and the bank address data described above is transferred in the form of register set data, and the register get data is transferred to the host CPU1 side so that the host CPU1 can know the state of the SVGA side. . The register set data and the image data stored in the FIFO (1) 1911 are sequentially output, and the bus interface unit 19 is output according to these data.
12 and each register in VGA 1917.
The VGA 1917 can know the bank address, its image data and the control command depending on the set state of these registers.

The VGA 1917 generates VRAM addresses in the VRAM (1) 192 corresponding to the addresses of the display memory window area and the bank addresses based on the addresses and the strobe signals RAS and CAS as memory control signals, and the chip. The select signal CS and the write enable signal WE are transferred to the VRAM (1) via the memory interface unit 1915.
Transfer to 192, which allows the image data to be written to that VRAM address. At this time, the rewritten image data is similarly transferred to the VRAM (1) 192 via the memory interface unit 1915.

On the other hand, the VGA 1917 reads the image data from the VRAM (1) 192 according to the vertical synchronizing signal, the horizontal synchronizing signal and the pixel clock input from the video interface 8, as will be described in detail later.
It is stored in the FIFO (2) 1916. FIFO (2) 1
From 916, the image data is sent to the display data switch 195 in the subsequent stage in the order in which the image data is stored.

The SVGA 191 is provided with a data manipulator 1913 and a graphics engine 1914 that perform an accelerator function. For example, the host CPU 1 is the bus interface unit 191
When a circle and its center and radius data are set in the register 2 and drawing of the circle is instructed, the graphic engine 1914 generates the circle display data, and the data manipulator 1913 stores this data in the VRAM (1) 1.
Write to 92.

The rewrite detection / flag generation circuit 1918 uses V
The VRAM address generated by GA1917 is monitored, and V
The VRAM address when the image data in the RAM (1) 192 is rewritten (written), that is, the VRAM address when the write enable signal and the chip select signal CS are valid is fetched. And this V
RAM address and VR obtained from host CPU1
A line address is calculated based on each data of the AM address offset, the total line number, and the total line bit number. The concept of this calculation is shown in FIG.

As shown in FIG. 4, VRAM (1) 1
The pixel indicated by the address X on 92 corresponds to the line N of the FLCD screen, one line is composed of a plurality of pixels, and one pixel is composed of a plurality (n) of bytes. . At this time, the line address (line number N) is calculated as follows.

[0022]

[Equation 1] The rewrite detection / flag generation circuit 1918 sets the flag of the partial rewrite line flag register 1919 according to the calculated line address. This is shown in FIG.

As is apparent from FIG. 5, when the display of the corresponding address on the VRAM (1) 192 is rewritten to display the character "L", for example, the rewritten line address is detected by the above calculation. Then, a flag is set in the register corresponding to this address (“1” is set).

Referring again to FIG. 2, the CPU 193
Can read the rewritten line address of the VRAM (1) 192 by reading the content (partial rewriting line flag information) of the rewriting line flag register of the rewriting detection / flag generation circuit 1918.

Next, the configuration of the video interface 8 in this embodiment will be described with reference to FIG. In FIG. 6, a luminance signal (Y) and a color signal (C) captured by the video camera 10 or the video disc player 9
The composite video signal in which the sync signal and the sync signal are mixed is first separated by the YC separator 801 into a luminance signal (Y) including the sync signal and a chrominance signal (C). Next, the luminance signal (Y) and the color signal (C) are transferred to the matrix circuit 80.
2 separates the three primary color signals R (red), G (green), B (blue) and the sync signal, and the three primary color signals R, G, B are further A
The signal is analog-to-digital converted by the / D converter 803 and input to the window controller 804. The sync signal separated by the matrix circuit 802 is input to the window controller 804 and used to generate address information. In addition, the matrix circuit 802
The pixel clock generated by the clock generator is A /
The three primary color signals R, G, B are input to the D converter 803.
It is used as a sampling clock of the signal, or is input to the window controller 804 and the SVGA 191 in the FLCD interface unit 19 to be used for synchronizing various operations.

In the window controller 804, size information in the X-axis direction and Y-axis direction for displaying image data fetched by the video camera 10 or the video disc player 9 transferred from the host CPU 1 in the form of register set data. In accordance with the above, signals R of the three primary colors digitized by the A / D converter 803,
Address information generation processing for enlarging / reducing G and B by a method such as bit thinning or bit interpolation, and pasting at a position determined by register information is performed. Further, the window controller 804 stores video data area information that is transferred from the host CPU 1 in the form of register set data and indicates at which position in the image data display area the video data is displayed.
By reading this information, the CPU 193 in the LCD interface unit 19 can detect at which position in the image data display area the video data is displayed. An example of this video data area information is shown in FIG. 8 shows the relationship of the video data area information shown in the example of FIG. 7 on the display screen. In FIG. 8, 30
Is a VRAM in the FLCD interface section 19.
(1) An image data display area for displaying the image data read from 192, and an image data display area 3
Graphic data 31 showing character data and a bar graph is displayed on 0. Reference numeral 32 is a video data display area for displaying the video data output from the video interface 8. X1 is the number of pixels in the horizontal direction indicating the start position of the video data when the left end of the image data display area is "0", and X2 is the number of pixels of the video data when the left end of the image data display area is "0". The number of pixels in the horizontal direction indicating the ending position, Y1 is the number of pixels in the vertical direction indicating the starting position of the video data when the upper end of the image data display region is "0", and Y2 is the upper end of the image data display region. Indicates the number of pixels in the vertical direction indicating the position where the video data ends when is set to "0".

Further, the window controller 804 is
A vertical synchronizing signal indicating the beginning of the image data display area and a horizontal synchronizing signal indicating the beginning of each display line are generated. SVGA1 in the FLCD interface section 19
At 91, according to the vertical synchronizing signal and the horizontal synchronizing signal, V
The image data is read from the RAM (1) 192 for each sequential scanning or every other scanning and is transferred to the display data switching unit 195. Furthermore, in the window controller 804 in the video interface 8, the A / D converter 803
After processing the signals R, G, B of the three primary colors from the host CPU 1 in the form of register set data, the video data display area is judged from the vertical synchronizing signal, the horizontal synchronizing signal and the pixel clock. The display data switching device 19 is provided for each of the sequential scanning of the video data or the skip scanning.
Transfer to 5.

FIG. 9 shows the configuration of the display data switch 195 according to this embodiment. In the display data switch 195, the video data from the video interface 8 and the SV
The image data from the GA 191 is combined with the FLCD 2
The state of being output as display data for 0 will be described based on the example of the screen configuration in FIG. In this embodiment, the number of pixels in the horizontal direction of the image data display area 30 is 1024, the number of pixels in the vertical direction is 768, the value of X1 is 301, and the value of X2 is 55.
The values of 0 and Y1 are 201, and the value of Y2 is 400.

The counter (1) 1951 is a counter for counting the number of pixels in the horizontal direction, which is initialized by the horizontal synchronizing signal and counts up in synchronization with the rising edge of the pixel clock. The counter (1) 1951 has a built-in frequency divider that divides the pixel clock according to the number of bits constituting one pixel, and the pixel clock is divided based on the pixel configuration information set by the CPU 193. And is used as the clock of the counter. For example, when one pixel is composed of 1 bit, the pixel clock is used as it is as the clock of the counter, and when one pixel is composed of 4 bits (that is, 16 color display or 16 gradation display) The pixel clock is divided by 4 and used as the clock of the counter. The counter (2) 1952 is a counter for counting the number of pixels in the vertical direction, which is initialized by the vertical synchronizing signal and counts up in synchronization with the rising edge of the horizontal synchronizing signal.

X1 size register 1953, X2 size register 1954, Y1 size register 1955, Y2
The value of the video data area information read by the CPU 193 from the video interface 8 is set in the size register 1956 by the CPU 193.

In the X1 size comparator 1957, the value of the X1 size register 1953 (301 in this embodiment) is compared with the value of the counter (1) 1951, and the counter (1) 19 is compared.
When the value of 51 is greater than or equal to the value of the X1 size register 1953, the output is set to high level “1”. The X2 size comparator 1958 compares the value of the X2 size register 1954 (550 in this embodiment) with the value of the counter (1) 1951, and when the value of the counter (1) 1951 is less than or equal to the value of the X2 size register 1954, The output is set to high level "1". In the Y1 size comparator 1959, the value of the Y1 size register 1955 (201 in this embodiment) and the counter (2)
When the value of the counter (2) 1952 is greater than or equal to the value of the Y1 size register 1955, the output is set to the high level “1”. In the Y2 size comparator 1960, the value of the Y2 size register 1956 (40 in this embodiment)
0) and the value of the counter (2) 1952 are compared, and when the value of the counter (2) 1952 is less than or equal to the value of the Y2 size register 1956, the output is set to the high level “1”.

The outputs of the X1 size comparator 1957, the X2 size comparator 1958, the Y1 size comparator 1959, and the Y2 size comparator 1960 are input to the 4-input AND gate 1961, and all the outputs are at the high level. When it becomes "1", the high-level "1" output from the 4-input AND element 1961 is output to the selector 1962 as a display data switching signal. In the selector 1962, one of the video data and the image data is selected according to the voltage level of the display data switching signal, and is output as the display data to the FLCD 20 to the binarization halftone processing circuit 194 in the subsequent stage. This is shown in FIG. In this embodiment, the image data is output as display data when the display data switching signal is at low level "0", and the video data is output as display data when the display data switching signal is at high level "1".

In the binarization halftone processing circuit 194, R,
256 gradations or 2 represented by 8 bits for G and B colors
A process of converting the multi-valued display data of 56 colors into binary pixel data corresponding to each pixel on the display screen of the FLCD 20 is performed. In the present embodiment, one pixel on the display screen has display cells having different areas for each color, as shown in FIG. Accordingly, as shown in FIG. 11, the data of 1 pixel also has 2 bits (R1, R1) for each color.
R2, G1, G2, B1, B2). Therefore, the binarization halftone processing circuit 194 converts 8-bit display data for each color into 2-bit data for each color (that is, 4-value data for each color).

As described above, in this embodiment, the VRAM
(1) The display data 192 is stored as 8-bit multi-valued data for each color of R, G, and B, and is binarized when these are read out and displayed. This allows the host CPU
1 can access the FLCD 20 side in the same manner as when a CRT is used, and can ensure compatibility with the CRT.

A known method can be used for the binarization halftone processing, and as such a method, for example, an error diffusion method, an average density method, a dither method, etc. are known. There is.

Referring again to FIG. 2, the display data processed by the binarization halftone processing circuit 194 is processed by the synthesis circuit 19
6 and is combined with the border pattern data from the CPU 193, and then stored in the VRAM (2) 199. The border generation circuit 197 generates pixel data of a border portion on the FLCD display screen. That is,
As shown in FIG. 11, the display screen of the FLCD 20 is
The display screen has 1024 lines each including 1280 pixels, and a border portion of the display screen that is not used for display is formed so as to frame the display screen. SVGA191
In addition to the 1024 pixels × 768 lines shown in this embodiment, the effective display area of the image data output from
There are display modes such as 0 pixel × 600 lines and 640 pixel × 480 lines, and the area other than the effective display area is the border portion.

Due to the presence of this border portion, F
The format of the pixel data transferred to the LCD 20 is
It becomes what is shown in FIG. 12 (A) or FIG. 12 (B). 12A is a data format of the display line A shown in FIG. 11, that is, the display line in which all the display lines are included in the border portion, and FIG. 12B is the display line B shown in FIG. 11, that is, the display. Is the data format of the line used for. In the data format of the display line A, a line address is attached to the head, and this is followed by border pixel data. On the other hand, since both ends of the display line B are included in the border part, the data format is as follows:
Pixel data and border pixel data follow in this order.

The border pixel data generated by the border generation circuit 197 is serially synthesized by the synthesis circuit 196 with the display data from the binarized halftone processing circuit 194.
This synthesized data is VR-processed through the memory control circuit 198.
It is stored in AM (2) 199.

In the memory control circuit 198, the FLCD 20
According to the display information output request signal HSYNC output from the VRAM (2) 199, the display data corresponding to the requested line address from the CPU 193 is read out, combined with the line address, and then output to the FLCD 20.

Further, the CPU 193 has a function of performing serial communication with the FLCD 20, and sends a command signal and a reset signal to the FLCD 20, and F
The trimmer information and other status information are received from the LCD 20.

Next, how the CPU 193 determines the required line address will be described based on the example of the screen configuration shown in FIG.

In the present embodiment, the character data and the graphic data 31 showing the bar graph drawn in the image data display area 33 for displaying the image data read from the VRAM (1) 192 in the FLCD interface section 19 are displayed. Among them, it is assumed that the character data is not updated and rewritten, and the graphic data 31 is being graph-drawn. CPU193 is VR
The area where the rewriting of AM (1) 192 is performed is SV
It can be known from the GA 191 as partial rewriting line flag information. In this embodiment, the line address in which the graphic data 31 is written is changed from 381 to 700.
Up to the line. Further, the CPU 193 can know the area where the video data captured from the video camera 10 or the video disc player 9 which is a video input device is displayed as the video data area information from the video interface 8. In this embodiment, the line address of the area where the video data is displayed is set to 201 to 400 lines.

Of these, the video data sent from the video interface 8 is moving image data whose display content is updated at a rate of 30 frames per second, and is preferentially used to improve the display quality. Need to display. Therefore, the CPU 193 determines the interlace value at the time of updating the moving image data display according to the size of the display area of the moving image data so that the apparent display update speed is 30 frames per second.

The CPU 193 is a video interface 8
From the video data area information sent from, the lines in which the video data display area 32 exists are 201 to 4 lines.
You can know that it is up to 00 line. CPU
193 determines that the size of the display area of the moving image data is 200 lines by subtracting these values.

Now, assuming that the display update rate per line of the FLCD 20 is 64 microseconds, the FLCD 2
Since the output request signal of the display data is transmitted every 0 to 64 microseconds, it is possible to update the display of 15625 lines per second. That is, in order to update the display contents at a speed of 30 frames per second, 1
It is necessary to update within about 521 lines per frame.

When the display area of the graphic data is updated with 3 interlaces and the other lines have low priority, 31 interlace display is performed. As a result, the number of interlaces in the area for displaying a moving image is as shown in Table 1. Can be determined. In the present embodiment, assuming the worst case, it is assumed that the graphic data exists in all areas other than the moving image display, and the display is updated in 3 interlaces, and the display allocated for the moving image display. Determines the number of lines for updating.

[0047]

[Table 1]

That is, if the number of lines in the area for displaying a moving image is between 1 and 350, the display is updated in a non-interlaced area, and if it is 350 or more, it is 1 interlaced. By updating the display, it is possible to display a moving image at a display update speed of 30 frames per second.

Explaining with the example of FIG. 8, since the number of display lines is 200 lines from 201 lines to 400 lines where the video data display area 32 exists, non-interlaced display is performed according to Table 1, and the graphic data 31 is displayed. From the 401st line to the 700th line, the 3 interlaced display is performed. Since the other lines have low priority, they are displayed in 31 interlaces.
Table 2 shows the relationship between the line address and the interlace mode determined as described above.

Here, 3 interlaced display means that when the line address 1 is selected first, the line address 5 is selected second, and the line address 9 is selected third. The line address is selected every 3 lines. Similarly, 31 interlaced display means that when the line address 1 is selected first, the line address 33 is selected second.
Thirdly, the line address is selected every 31 lines such that the line address 65 is selected.

[0051]

[Table 2]

According to the above operation, all the line addresses are selected in the video data display area 32, the line addresses are selected every three lines in the area of the graphic data 31 by one scan of the display screen, and the other areas are selected. Area is 31
A line address will be selected for each line.
Table 3 shows how the line address is selected by this operation.

[0053]

[Table 3]

As described above, according to the request line address generated by the above-mentioned means, VRAM (2) 1
The display data and the display line address read from 99 are transferred to the FLCD 20 and displayed.
This is shown in FIG. In this embodiment, the display line address and the pixel data are displayed as being transferred to the FLCD 20 as 8-bit parallel data from AD0 to AD7. First, the synchronization signal HSYNC indicating a data transmission request from the FLCD 20 is sent to the memory control circuit 198.
Is input to the CPU 19 in the memory control circuit 198.
VRAM199 according to the request line address from
The display data is read from (2) and output to the FLCD 20 together with the display line address. At the same time, the memory control circuit 198 transfers an AHDL signal for identifying the display line address and the pixel data to the FLCD 20. AH here
DL signal is AD0 to AD7 when high level "1"
Is a signal indicating that the display line address is being output to the signal lines up to and the pixel data is being output to the signal lines from AD0 to AD7 at the low level "0". First, the AHDL signal is set to high level "1" to transfer the output display line address to the FLCD 20, and when the transfer is completed, the AHDL signal is set to low level "0" and the display data is output to the FLCD 20.

(Second Embodiment) In the first embodiment, the image data requested to be displayed by the host CPU 1 and the image data taken in via the video interface 8 are combined and stored in the VRAM (2) 199. A means for storing, reading the data from the VRAM (2) 199 and displaying the data, detecting an area for displaying the video data, and determining an interlace mode for displaying the video data according to the size thereof will be described. did.

In the present embodiment, a means for detecting the ambient temperature of the FLCD 20 and adding the ambient temperature information of the FLCD 20 as a factor for determining the interlace mode when displaying the video data will be described.

Since the rewriting speed of the FLCD 20 changes depending on the ambient temperature, the update time of one line, that is, H
The output cycle of SYNC changes. That is, the FLCD 20
When the ambient temperature is high, the rewriting speed is fast, so the display update speed of 30 frames / sec or more was realized. However, when the temperature is low, the display update speed of 30 frames / sec or more cannot be realized. I will end up. Therefore,
Changing the number of interlaces depending on the ambient temperature of the FLCD 20 makes it possible to provide a stable moving image display that is not affected by changes in the rewriting speed of the FLCD 20 due to the temperature environment.

FIG. 14 shows a configuration example of the FLCD interface section 19 in this embodiment. In FIG. 14, 20A is a temperature sensor for monitoring the ambient temperature state of the FLCD 20. In this embodiment, the temperature state detected by the temperature sensor 20A is notified to the FLCD interface unit 19 via the serial communication function for receiving trimmer information and other status information from the FLCD 20. In the first embodiment, the update time for one line is described as 64 microseconds, but in the present embodiment, the temperature state detected by the temperature sensor 20A is notified from the FLCD 20 as 2-bit information, and the combination of each bit is It is assumed that the ambient temperature state of the FLCD 20 and the update time of one line at that time correspond as shown in Table 4.

In this embodiment, the CPU 193 in the FLCD interface 19 generates the image data from the size of the area where the image data is displayed and the ambient temperature information of the FLCD 20 sent from the FLCD 20 via the serial communication function. By determining the interlace mode for displaying and outputting the generated line address to the memory interface unit 198, the corresponding display data is read from the VRAM (2) 199 and displayed on the FLCD 20.

[0060]

[Table 4]

Table 5 shows how the interlace mode for displaying the video data is determined by the ambient temperature information and the size of the area where the video data is displayed. As shown in Table 5, if the ambient temperature of the FLCD 20 is 10 degrees or more and the number of lines for displaying the moving image is 200 lines or less, the moving image can be optimally displayed in the non-interlaced mode, Temperature is 10
Even if the number of lines is less than 200 degrees or the number of lines displayed in the moving image is 200 lines or more, changing the number of interlaces makes the apparent display update speed 30.
It can be more than a frame.

[0062]

[Table 5]

Also in the present embodiment, the operation in the case where the display is updated as shown in FIG. 8 will be described as in the first embodiment. In FIG. 8, as for the character data and the graphic data 31 showing the bar graph drawn in the image data display area 30, the character data is not updated and rewritten as in the case of the first embodiment. As for the graphic data 31, it is assumed that a graph drawing operation is being performed.

Assuming that the ambient temperature of the FLCD 20 has not risen sufficiently immediately after the power is turned on and is in the range of 10 to 15 degrees, 16 interlaced lines from the 401st line to the 700th line where the graphic data 31 exist. Is displayed. From 201 lines to 400 lines where the video data display area 32 exists, since the number of display lines is 200 lines, non-interlaced display is performed according to Table 5. Since the other lines have low priority, they are displayed with 31 interlaces. Table 6 shows the relationship between the line address and the interlace mode determined as described above.

[0065]

[Table 6]

As described above, according to the present embodiment, more delicate display control is performed by adding the ambient temperature information of the FLCD 20 as a factor that determines the number of lines to be updated in one screen scan. Is possible,
It is possible to maintain the display quality of moving image display that is not affected by the ambient temperature.

[0067]

As described above, according to the present invention,
The scanning area in which the display is updated is detected by the image information from the host CPU or the like, the scanning area of the video information from the video signal input device and its size which are combined with this image information are detected, and the image information is detected. The display information of the display update area and the display information of the display update area is preferentially output to the display device, and the display update area of the image information and the display information of the display information area are updated. The number of interlaces is made different between the region where the image is performed and the other region, and the number of interlaces of the region where the display update is performed by the video information is determined according to the size of the scanning region of the video information. As a result, the apparent display update speed of the video information from the video signal input device can be maintained at 30 frames / second or more, and the FLCD
It is possible to obtain a high-quality display screen that makes the best use of the partial rewriting control which is the characteristic of the above.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an entire information processing device incorporating a display control device according to an embodiment of the present invention.

2 is a block diagram showing a configuration of an FLCD interface unit in the apparatus of FIG.

3 is a block diagram showing a configuration example of an SVGA in the apparatus of FIG.

FIG. 4 is a schematic diagram for explaining conversion from a VRAM address to a line address in the device of FIG.

5 is a schematic diagram showing a relationship between a rewriting display pixel and a rewriting line flag register in the device of FIG.

6 is a block diagram showing a configuration of a video interface in the apparatus of FIG.

7 is a schematic diagram showing a data format of video data area information output from the video interface in the apparatus of FIG.

8 is a schematic diagram showing an example of display information output to the FLCD in the apparatus of FIG.

9 is a block diagram showing a configuration of a display data switch in the apparatus of FIG.

10 is a display data switching device of the apparatus of FIG.
7 is a timing chart showing how display data is switched.

11 is a schematic diagram showing an FLCD display screen in the apparatus of FIG.

12 is a schematic diagram showing a data format of display data in the apparatus of FIG.

13 is a timing chart showing how a line address and pixel data are transferred to the FLCD in the device of FIG.

FIG. 14 is an FLCD according to a second embodiment of the present invention.
It is a block diagram which shows the structure of an interface.

[Explanation of Codes] 1: Host CPU, 2: High-speed bus, 3: Medium-speed bus, 4:
ROM, 5: DRAM, 8: video interface,
9: Video disc player, 10: Video camera, 1
1: 1/0 controller, 12: hard disk, 1
3: Floppy disk, 14: RTC, 15: Audio subsystem, 16: KBD controller, 17:
Keyboard, 18: Mouse, 19: Display controller (FLCD interface part), 20: FLC
D, 20A: trimmer, 191: SVGA, 192: VR
AM (1), 193: CPU, 194: Binary halftone processing circuit, 195: Display data switcher, 196: Synthesis circuit, 197: Border generation circuit, 198: Memory control circuit, 199: VRAM (2), 1911: FIFO
(1), 1912: Bus interface unit, 1
913: data manipulator, 1914: graphic engine, 1914: memory interface unit, 1916: FIFO (2), 1917: VGA, 1
918: Rewrite detection / flag generation circuit, 1919: Partial rewrite line flag register, 801: YC separator, 80
2: Matrix circuit, 803: A / D converter, 80
4: window controller, 1951: counter (1), 1952: counter (2), 1953: X1 size register, 1954: X2 size register, 195
5: Y1 size register, 1956: Y2 size register, 1957: X1 size comparator, 1958X2 size comparator, 1959: Y1 size comparator, 1960: Y2
Size comparator, 1961: AND gate, 1962: selector.

Claims (8)

[Claims] 1. A display control for synthesizing video information from a video signal input device and image information from a central processing unit, and displaying based on the synthesized information by a display device having a storage state of a display state. In the method, a scanning area to be updated in the image information is detected, the scanning area of the video information in the composite information and the size thereof are detected, and based on each of the detected scanning areas, the video information and Of the image information, the one whose display is updated is preferentially output to the display device, and the preferential output is a scanning area updated by the video information and a scanning area updated by the image information. This is realized by making the number of interlaces different between the scanning area and the other scanning areas, and further, by changing the number of interlaces in the scanning area according to the size of the scanning area of the video information. Display control method, characterized by a constant. 2. The display control method according to claim 1, wherein information on the ambient temperature of the display device is further added as a factor for determining the number of interlaces. 3. The display control method according to claim 1, wherein the display device is a ferroelectric liquid crystal display device. 4. A display control for synthesizing video information from a video signal input device and image information from a central processing unit, and displaying based on the synthesized information by a display device having a memory of display state. An apparatus, comprising: first detection means for detecting a scanning area of the image information that is updated; second detection means for detecting a scanning area of the video information in the composite information; and scanning of the video information. Third detection means for detecting the size of the scanning area from the area, and one of the video information and the image information which has undergone display update based on the detection results by the first to third detection means. Display control means for preferentially outputting to the display device, wherein the display control means comprises a scanning area updated by the video information, a scanning area updated by the image information, and The display control is characterized in that the interlace number is made different from that of the outer scanning area, and further the scanning line control means is provided for determining the interlace number in the scanning area according to the size of the scanning area of the video information. apparatus. 5. A display control for synthesizing video information from a video signal input device and image information from a central processing unit, and displaying based on the synthesized information by a display device having a memory of display state. A first storage means for temporarily storing the image information; a combining means for combining the video information and the image information to generate display information to be output to the display device; Second storage means for temporarily storing information, first detection means for detecting an updated scanning area in the image information in the first storage means, and scanning area for video information in the display information Based on the detection results of the first to third detecting means, the third detecting means for detecting the size of the scanning area of the video information,
A display control unit for preferentially outputting to the display device what is being updated, of the video information and the image information, wherein the display control unit is a scanning area updated by the video information; Scan control in which the number of interlaces is changed between the scanning area updated in the image information and the other scanning areas, and the number of interlaces in the scanning area is changed according to the size of the scanning area of the video information. A display control device comprising means. 6. The display control device according to claim 4, further comprising information on an ambient temperature of the display device as a factor for determining the number of interlaces. 7. The display control device according to claim 4, wherein the display device is a ferroelectric liquid crystal display device. 8. A display system comprising the display control device according to claim 4 and a ferroelectric liquid crystal display device.