JPH09152855A - Video signal time compression device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a high-speed writing/reading in/from a field memory and also to optimize the memory capacity by a time compression device to compress a video signal into one third. SOLUTION: Samples of 910 pieces of video signals per one line are delayed by two clocks by a two-clock delay circuit 31 and by one clock (CK) by a one-clock delay circuit 32, when three successive samples are fetched in parallel into a latch 33. The samples are fetched into a one-clock delay circuit 34 at the timing of WMCK (writing clock), and are fetched into VRAMs 35-37 at the following WMCK. WMCK divides CK to 1/3 and is also formed so that the duty changes during a horizontal blanking period. Reading from VRAMs 35-37 is performed by a clock with a frequency three time as many as WMC.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention has a color liquid crystal shutter arranged in front of a monochrome image display means such as a monochrome CRT.
The present invention relates to a device for displaying a high resolution color image by controlling on / off of a color liquid crystal shutter in synchronization with a frame sequential color image signal input to a monochrome CRT. The present invention relates to a technique for enabling the writing / reading of data and optimizing its capacity.

[0002]

2. Description of the Related Art A color liquid crystal shutter is arranged in front of a black and white CRT, and a color liquid crystal shutter is turned on / off in synchronization with a frame sequential color video signal input to the black and white CRT to display a high resolution color image. Color image display devices have been successively proposed (Nikkei Electronics, No. 592, pp74-75, issued October 11, 1993).

FIG. 12 is a block diagram showing an example of such a display device. As shown in the figure, in the conventional frame sequential color image display device, R, G, and B color video signals having a field frequency fv1 = 60 Hz input at the same time are converted into field sequential color video signals having a field frequency fv2 = 180 Hz. Video signal time compression block 1, a monochrome CRT 2 to which the frame sequential color video signal output from the video signal time compression block 1 is supplied, a color liquid crystal shutter 3 arranged in front of the monochrome CRT 2, and a video signal time compression A deflection circuit 4 for performing horizontal deflection and vertical deflection of the black and white CRT 2 based on the deflection control signal output from the block 1.
And the LCS supplied from the video signal time compression block 1.
A liquid crystal shutter (LCS) drive circuit 5 for performing on / off control of the color liquid crystal shutter 3 based on a control signal is provided.

FIG. 13 is a diagram showing an example of the configuration of the color liquid crystal shutter shown in FIG. 12 and its operation. FIG.
As shown in (a), the color liquid crystal shutter is arranged on the front surface of the screen of the monochrome CRT 2 shown in FIG. 12, and the first polarizing plate 11, the first liquid crystal panel 12, and the second polarizing plate 1 are arranged.
3, a second liquid crystal panel 14, and a third polarizing plate 15.

The first polarizing plate 11 is a neutral polarizing plate and transmits R, G, B having a plane of polarization in the horizontal direction. The second polarizing plate 13 is a color polarizing plate and transmits B having a polarization plane in the horizontal direction and R and G having polarization planes in the vertical direction. Further, the third polarizing plate 15 is also a color polarizing plate and transmits R having a polarization plane in the horizontal direction and B and G having polarization planes in the vertical direction. And
The first and second liquid crystal panels 12 and 14 have the same plane of polarization when they are on (when a voltage is applied), and have a plane of polarization of 90 degrees when they are off (when no voltage is applied). The incident light is transmitted by rotating it.

Therefore, as shown in FIG.
Color display can be performed by performing on / off control of the first and second liquid crystal panels 12 and 14 in the color liquid crystal shutters in synchronization with the R, G and B signals.

First, the first liquid crystal panel 12 is turned on and the second liquid crystal panel 12 is turned on.
The case where the liquid crystal panel 14 is turned off will be described. FIG.
White light (R, G, B) emitted from the black and white CRT2
Only components having a plane of polarization in the horizontal direction are transmitted through the first polarizing plate 11. Then, since the first liquid crystal panel 12 is on, the light is transmitted with the same polarization plane, and the second polarizing plate 13
Incident on. Since the second polarizing plate 13 transmits only B having a color having a plane of polarization in the horizontal direction, only B of R, G, and B incident on the second polarizing plate 13 transmits through this, and the second It is incident on the liquid crystal panel 14. Since the second liquid crystal panel 14 is off, the polarization plane is rotated 90 degrees to become B having a polarization plane in the vertical direction, and the light enters the third polarizing plate 15. Since the third polarizing plate 15 transmits B and G, which have polarization planes in the vertical direction, only B is transmitted through the third polarizing plate 15.

Similarly, when the first liquid crystal panel 12 is off and the second liquid crystal panel 14 is on, the light transmitted through the third polarizing plate 15 becomes G, and the first liquid crystal panel 12 and the second liquid crystal panel 12 When both of the liquid crystal panels 14 are off, R is displayed.

Next, the operation of the frame sequential color image display device shown in FIG. 12 will be described. Field frequency fv1 = 60
The R, G, B signals of Hz are input in parallel to the video signal time compression block 1. Video signal time compression block 1
Performs A / D conversion of R, G, and B signals, writes the signals in an internal field memory (not shown), and reads the signals at a speed three times as high as that at the time of writing to perform time compression to 1/3. Further, it is read from this field memory as an R, G, B frame sequential signal. Read field frequency fv2
= 180 Hz R, G, B frame sequential color video signals are analogized and output.

The R, G, B frame sequential color video signals output from the video signal time pressure block 1 are sent to a black and white CRT 2 and converted into white light by electrical / optical conversion. The deflection control signal output from the video signal time pressure block 1 is sent to the deflection circuit 4. The deflection circuit 4 is based on this deflection control signal, and the black and white C
Perform horizontal and vertical deflection of RT2. Further, the liquid crystal shutter drive circuit 5 causes the two liquid crystal panels 12 and 14 shown in FIG. 13 to output the R, G, B frame sequential color video signals based on the LCS control signal supplied from the video signal time pressure block 1. The on / off control is performed so that the display color corresponds to the color.

[0011]

In the above-described frame sequential color image display device, the color video signal is written in the field memory and read out at a triple speed, so that 3
Double the time compression. Color video signal to NTSC
The clock frequency for writing is 4 fsc
When (fsc is the color subcarrier frequency) is set, the clock frequency for reading is 12 fsc. The cycle of the read clock in this case is about 23 nS, which is the current VRAM (Video Random A).
access memory) becomes faster than the upper limit of the read speed of about 35 nS.

Therefore, it is possible to reduce the writing / reading speed with respect to the field memory by providing a plurality of field memories in parallel. At this time, the number N of samples per line of the color video signal
Is divisible by the number M of field memories, the control is easy because the clock frequency for writing / reading is set to 1 / M, but if it is not divisible, the control becomes difficult.

For example, the NTSC system and VGA (Vide)
o When considering a system common to the Graphics Array, VGA requires reading at 24 fsc, and therefore three field memories must be provided. In this case, 910, which is the number of samples per line of the NTSC color video signal, is divided by 3 to obtain 303.333 ... In order to make it divisible, the number of samples per line or the number of field memories may be changed, but it is difficult to change the number of samples per line because it is often determined by the system. Further, when the number of field memories is changed, the number is increased, resulting in an increase in cost.

The present invention has been made in view of the above problems, and in the video signal time compression block in the frame sequential color image display apparatus having the above-described structure, it is faster than the field memory. It is intended to enable writing / reading and to optimize its memory capacity.

[0015]

In order to solve the above-mentioned problems, a video signal time compression apparatus according to the present invention stores a video signal sampled at a predetermined frequency fs, and a writing in the storage means. It is a device that includes a write control unit that performs control and a read control unit that performs read control of the storage unit, and compresses the video signal to ⅓ time by making the read speed in the storage unit three times the write speed. Then, the storage means has N samples of the video signal input serially (where M is an integer of 3 or more, and N is the number of samples per line of the video signal). 1) for parallelizing each of the parallel outputs of the first means, M partial storage means for storing parallel outputs of the first means, and M partial storages. The write control means divides fs into 1 / M and outputs M at the timing of the clock signal whose duty changes in the horizontal blanking period of the video signal. The read control means controls so as to simultaneously write data to each of the partial storage means, and the read control means divides the frequency of 3 fs into 1 / M and horizontally blanks the video signal compressed in time to 1/3. It is characterized in that it is controlled so that the M pieces of partial storage means are simultaneously read out at the timing of the clock signal whose duty changes during the period.

In the present invention, three sets of video signal time compression devices are provided, and R, G, or B signals are simultaneously input to each of them, whereby the R, G, and B signals are time-compressed simultaneously. Then, the time-compressed R, G, B simultaneous signals are converted into R, G, B frame sequential signals, which are supplied to the black and white image display means, and the color liquid crystal arranged in front of the black and white image display means. By controlling the on / off of the shutter in synchronization with the R, G, B frame sequential signals, a frame sequential color image is displayed.

[0017]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 shows the configuration of a video signal time compression block to which the present invention is applied. This video signal time compression block is used in the frame sequential color image display device as shown in FIG.

As shown in the figure, the video signal time compression block 1 is decoded by an RGB decoder 11 for converting an input component color video signal for luminance / color difference separation into parallel R, G, B signals. A / D converters 12, 13, 14 for converting each R, G, B signal into an 8-bit digital signal, and A / D converters 12, 1
VRAMs 15, 16, 17 for storing the outputs of 3, 14
A switch SW1 for selecting the outputs of the VRAMs 15, 16 and 17 to make them frame sequential, and a D / A converter 18 for analog-converting the color video signals made frame sequential by the switch SW1.

The video signal time compression block 1 further includes
A sync separation circuit 19 that separates a horizontal sync signal (HD) and a vertical sync signal (VD) from an input component color video signal, and also generates a sampling clock (CK) of frequency fs, and a write control signal for the VRAMs 15 to 17. VRAM write control circuit 20 for generating
And a read control circuit 21 for generating a read control signal and a read clock for the VRAMs 15 to 17, and a horizontal sync signal (TH) having a frequency three times as high as the horizontal sync signal (HD).
D), a vertical synchronizing signal (TVD) having a frequency three times as high as the vertical synchronizing signal (VD), a sampling clock (TCK) having a frequency of 3fs, a deflection control signal, and an LCS control signal x3SYNC and a display control signal generating circuit. 22 and 22. The sync separation circuit 19 may be configured to perform sync separation from the G signal.

The horizontal sync signal (HD) and the vertical sync signal (VD) output from the sync separation circuit 19 are used as timing control signals for the VRAM write control circuit 20, the x3 SYNC and the display control signal generation circuit 22. The sampling clock (CK) of the frequency fs is A /
It is used as a sampling clock for the D converters 12, 13, 14 and as a write clock for the VRAMs 15, 16, 17.

X3 SYNC and display control signal generation circuit 2
The vertical synchronizing signal (TVD), the horizontal synchronizing signal (THD), and the sampling clock (TCK) generated by
It is sent to the RAM read control circuit 21. Also, TVD
Is also used as a switching control signal for the switch SW1, and TCK is also used as a timing control signal for the D / A converter 18.

Of the VRAMs 15, 16 and 17, the VRAM
15 and 17 have a capacity of 1 field, and VR
The AM 16 has a capacity of 4/3 field so that reading does not overtake writing in the memory.

FIG. 2 is a diagram showing the memory control operation of the VRAMs 15, 16 and 17. In this figure, the horizontal axis represents time, the vertical axis represents the capacity of each VRAM, and V represents a field.

As shown in this figure, VRAMs 15, 1
Writing to R6, G17 is performed simultaneously with R, G and B, and reading is performed in order of R, G and B. More specifically, reading of G is started at the same time as writing is completed, and R is read earlier than G by 1/3 field (= one field of output signal) of the input signal. Then, B is read later than G by 1/3 field of the input signal. Therefore, if the capacity of the VRAM 16 for storing B is set to the same one field as the other VRAMs 15 and 17, the reading will overtake the writing of the next field, so the capacity is increased to 4/3 field to avoid the overtaking. ing.

FIG. 3 is a block diagram showing an example of a concrete configuration of the VRAMs 15 to 17 and the VRAM write control circuit 20 shown in FIG. In this figure, except for the sync separation circuit 19, only one system of R, G, or B of FIG. 1 is shown. Therefore, the VRAMs 35 to 37 are the VRAM 15
Or 17, the capacity required for each of the VRAMs 35 to 37 is ⅓ field, and
If 5 to 37 are VRAM 16, VRAM 35
The capacity required for each of ~ 37 is 4/9 fields.

The circuit of FIG. 3 has a delay circuit 31 of two sampling clocks (CK), a delay circuit 32 of one sampling clock (CK), an input sample LDI3, and output samples LDI of these two delay circuits 31 and 32.
Latch circuit 33 that takes in 1 and LDI2 in parallel
And parallel outputs LDO1 and LDO of the latch circuit 33.
2, a delay circuit 34 for delaying LDO3 by one sampling clock (CK), and VRAMs 35 to 37. This corresponds to one VRAM in FIG.

The circuit of FIG. 3 further includes a sync separation circuit 19
The vertical synchronizing signal (VD), the horizontal synchronizing signal (HD), and the sampling clock (CK) output from
An enable signal (XEN) that enables data to be taken into the latch circuit 33, a write clock generation circuit 38 that generates a write clock (WMCK) that is an inverted output of the enable signal, a horizontal synchronization signal (HD), and a vertical synchronization signal ( VD), a signal (WMHD) for resetting a horizontal write address and a signal (W) for resetting a vertical write address in the VRAMs 35 to 37.
And a clock transfer circuit 39 for generating MVD). This corresponds to the VRAM write control circuit 20 in FIG.

FIG. 4 shows an example of a specific configuration of the write clock generation circuit 38. This circuit is a 2-bit counter 4
1, an AND gate 42, an AND gate 43, an exclusive OR (hereinafter, EX-OR) gate 44, and an inverter 45.

The 2-bit counter 41 has an AND gate 4
The output of 2 is inverted and input. The output of the AND gate 43 and the horizontal synchronizing signal (HD) are inverted and input to the AND gate 42. The lower bit QA of the 2-bit counter 41 is inverted and input to the AND gate 43, and the upper bit QB is input as it is.

The AND gate 43 is a 2-bit counter 41.
When the counter value of 2 is 2, a high level signal is output.
Further, the EX-OR gate 44 outputs a high level signal when the counter value is 1 or 2. EX-OR gate 4
4 becomes XEN, and the output of the inverter 45 becomes WMCK. Therefore, WMCK is obtained by dividing CK by 1/3, but in the present embodiment, CK is 9 per line.
Since it is the frequency to sample 10 data,
910 is not divisible by 3. So once per line,
The 2-bit counter 41 is reset when the horizontal synchronizing signal (HD) is at a high level in the horizontal blanking period,
The duty of XEN and WMCK is changed.

FIG. 5 is a timing chart showing the operation of the circuit of FIG. The operation of the circuit of FIG. 3 will be described below with reference to this figure.

R or G output from the A / D converter
Alternatively, the sample LD 13 of B includes a 2 sampling clock (CK) delay circuit 31 and a 1 sampling clock (C
K) Input to the delay circuit 32. The output LD11 of the 2-sampling clock (CK) delay circuit 31 and the output LD12 of the 1-clock delay circuit 32 are the sample LD1 output from the A / D converter when XEN is at a low level.
It is taken into the latch 33 in parallel with 3. Then, it is fetched in parallel by the 1-clock delay circuit 34 at the timing of WMCK. The LDO1 to LDO3 fetched in the 1-clock delay circuit 34 are fetched in parallel to the VRAMs 35 to 37 by the next WMCK.

At this time, at the timing of resetting by the horizontal synchronizing signal (HD), the write data is lost and the data becomes discontinuous. In FIG. 5, the 909th data is missing. However, since this missing data is for the horizontal blanking period, it does not affect the displayed image. In FIG. 6, the reset timing by HD is C
It shows a state in which the data is shifted backward by K1 and the 0th data is missing. In this way, even if data is lost, XEN and WMC are set so that it is in the horizontal blanking period.
By changing the duty of K and controlling the data to be continuous in the effective scanning portion of one line,
I'm trying not to show any omissions in the displayed image.

FIG. 7 shows VRAMs 15 to 17 in FIG.
5 is a block diagram showing an example of a specific configuration of a part of a VRAM read control circuit 21 and a x3 SYNC and display control signal generation circuit 22. FIG. Here, VRAM is V in FIG.
The same numbers are assigned because they are the portions related to reading in the RAM.

The circuit of FIG. 7 is the output of VRAM 35 or V
It has a first selector 56 for selecting the output of the RAM 36 and a second selector 57 for selecting the output of the first selector 56 or the output of the VRAM 37. These correspond to the VRAM 15 or 16 or 17 in FIG.

The circuit of FIG. 7 also includes a vertical sync signal (V
Vertical synchronization signal (TV)
D) and the horizontal synchronizing signal (H
The horizontal sync signal (TH
D) for producing a clock and a multiplier circuit 53 for producing a clock (TCK) by multiplying the horizontal synchronizing signal (THD) by 910 times.
These multiplication circuits are part of the x3 SYNC and display control signal generation circuit 22 of FIG.

The circuit of FIG. 7 further includes a vertical sync signal (T
VD), horizontal sync signal (THD) and clock (TCK)
And the control signals (SEL1, SEL2) for controlling the data read clock (RMCK) of the VRAMs 35 to 37 and the first selector 56 and the second selector 57.
And a horizontal synchronization signal (THD) and a vertical synchronization signal (TVD).
The RAM 35 to 37 is provided with a clock transfer circuit 55 for generating a signal (RMHD) for resetting a horizontal read address and a signal (RMVD) for resetting a vertical read address. This is Figure 1
Corresponds to the VRAM read control circuit 21 in FIG.

FIG. 8 shows an example of a specific configuration of the read clock generation circuit 54. This circuit is composed of a 2-bit counter 61, an AND gate 62, an AND gate 63, and an AND gate 64 as in FIG.

The 2-bit counter 61 has an AND gate 6
The output of 2 is inverted and input. The output of the AND gate 63 and the horizontal synchronizing signal (THD) are inverted and input to the AND gate 62. The lower bit QA of the 2-bit counter 41 is inverted and input to the AND gate 63,
The upper bit QB is input as it is.

Also in this read clock generating circuit, once per line, when the horizontal synchronizing signal (THD) is at the high level in the horizontal blanking period, the 2-bit counter 61 is reset to select SEL1, SEL2, and RM.
The duty of CK is changed.

FIG. 9 is a timing chart showing the operation of the circuit of FIG. It should be noted that this figure relates to reading of data written at the timing shown in FIG. The operation of the circuit of FIG. 7 will be described below with reference to this figure.

The data stored in the VRAMs 35 to 37 are output in parallel at the rising timing of RMCK. The output RD1 of the VRAM 35 is sent to the first selector 56, and the read clock generation circuit 54
Is selected when the output of SEL1 is low level.
The output RD2 of the VRAM 36 is input to the first selector 56, and is selected when the output SEL1 of the read clock generation circuit 54 is at the high level.

The output of the first selector 56 is input to the second selector 57, and is selected when the output SEL2 of the read clock generating circuit 54 is at low level. The output RD3 of the VRAM 37 is input to the second selector 57, and is selected when the output SEL2 of the read clock generation circuit 54 is at the high level. As a result, the data output from the second selector 57 is as shown in FIG.
It is described as DAin.

At this time, the second selector 57 is set at the timing of being reset by the horizontal synchronizing signal (THD).
The output data of is discontinuous. In FIG. 9, originally 9
The 903, 906, 907, and 908th data are output at the positions that should be the 06, 907, 908, and 909th data. However, since this part is the horizontal blanking period, it does not affect the displayed image. FIG.
0 is the data written at the timing shown in FIG.
10 is a timing chart when reading is performed at the same timing as in FIG. 9. In this case, the position is deviated from that of FIG. 9 and four pieces of data become NG. in this way,
The second selector 57 depends on the reset timing.
The array of data output from changes. However, by setting the reset timing so that it becomes the horizontal blanking period and controlling the data so that it is continuous in the effective scanning portion of one line, it is possible to prevent loss or discontinuity in the displayed image. I have to.

The writing / reading in the horizontal direction has been described above. Next, vertical writing / reading will be described with reference to FIG. Here, (a) is a timing chart at the time of writing, and (b) is a timing chart at the time of reading.

WMHD and WMVD in FIG. 11 (a)
Is generated by the clock transfer circuit 39 of FIG.
It is input to the RAMs 35 to 37. Similarly, XWE is also generated by the clock transfer circuit 39, and the VRAMs 35 to
It is input to 37. And WMHD is VRAM35-
The horizontal write address of 37 is reset (FIGS. 5 and 6). Further, the WMVD resets the vertical write addresses of the VRAMs 35 to 37. And X
WE uses 240 lines which are effective lines of the image as VRAM
Control is performed so that the data is written in 35 to 37.

The same applies to the read side, and RMHD and RMVD in FIG. 11B are the clock transfer circuit 5 in FIG.
5 and is input to the VRAMs 35 to 37.
The XOE is also generated by the clock transfer circuit 55 and input to the VRAMs 35 to 37. And RMH
D resets the horizontal read address of the VRAMs 35 to 37 (FIGS. 9 and 10). Further, the RMVD resets the vertical read addresses of the VRAMs 35 to 37. XOE is the effective line of the image 2
It controls to read 40 lines from the VRAMs 35 to 37.

[0048]

As described above in detail, according to the present invention, high speed writing / reading can be performed with respect to the storage means for time-compressing the video signal. Also,
Even if the number of video signal samples per line is not divisible by the number of partial storage means, the capacity of the storage means can be optimized, so that the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a video signal time compression device to which the present invention is applied.

FIG. 2 is a diagram showing a memory control operation of the VRAM in FIG.

3 is a block diagram showing an example of a specific configuration of a VRAM and a VRAM write control circuit in FIG.

FIG. 4 is a circuit diagram showing an example of a specific configuration of a write clock generation circuit in FIG.

5 is a timing chart showing the operation of the circuit of FIG.

FIG. 6 is a timing chart showing the operation of the circuit of FIG. 3 when reset timings are different.

7 is a block diagram showing an example of a specific configuration of a part of the VRAM, the VRAM read control circuit, and the x3 SYNC and display control signal generation circuit in FIG.

8 is a circuit diagram showing an example of a specific configuration of the read clock generation circuit in FIG.

9 is a timing chart showing the operation of the circuit of FIG.

FIG. 10 is a timing chart showing the operation of the circuit of FIG. 7 when reset timings are different.

FIG. 11 is a timing chart showing a write / read operation in the vertical direction.

FIG. 12 is a block diagram showing a configuration of a conventional frame sequential color image display device.

13 is a diagram showing an example of the configuration of the color liquid crystal shutter shown in FIG. 12 and its operation.

[Explanation of symbols]

1 ... Video signal time compression block, 2 ... Monochrome CRT, 3 ...
Color liquid crystal shutter, 5 ... Liquid crystal shutter drive circuit,
15-17, 35-37 ... VRAM, 20 ... VRAM write control circuit, 21 ... VRAM read control circuit, 2
2 ... × 3 SYNC and display control signal generation circuit

Claims (3)

[Claims] 1. A storage unit for storing a video signal sampled at a predetermined frequency fs, a write control unit for performing write control of the storage unit, and a read control unit for performing read control of the storage unit, An apparatus for time-compressing a video signal to ⅓ by making the reading speed in the storage means three times as fast as the writing speed, wherein the storage means includes M samples of the video signal serially input (however, , M is an integer of 3 or more, and N is the number of samples per line of the video signal, N / M is a value set such that it does not become an integer) and a first means for parallelizing The write means further comprises M partial storage means for respectively storing parallel outputs of the first means, and second means for serializing outputs of the M partial storage means. The control means controls so as to divide fs into 1 / M and simultaneously write to the M partial storage means at the timing of the clock signal whose duty changes in the horizontal blanking period of the video signal. The read control means divides the frequency of 3 fs into 1 / M, and the duty factor changes in the horizontal blanking period of the video signal time-compressed to 1/3. 2. A video signal time compression device, wherein the video signal time compression device is controlled so as to simultaneously read from the partial storage means. 2. The video signal time compression according to claim 1, wherein the video signals are R, G, or B signals input at the same time, and the R, G, B signals are individually time-compressed. apparatus. 3. A means for converting an R, G, B simultaneous signal into an R, G, B frame sequential signal, a monochrome image display means to which the R, G, B frame sequential signal is supplied, and the monochrome image display. On / off of the color liquid crystal shutter arranged on the front surface of the means and in synchronization with the R, G, B frame sequential signals.
3. The video signal time compression apparatus according to claim 2, which is used in a field sequential color image display apparatus provided with a means for controlling off.