JPH09149345A - Display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute display in accordance with the video signal of optional resolution by generating a dot clock frequency information for displaying an image based on a synchronizing signal and generating a driving signal based on the information. SOLUTION: When a horizontal synchronizing signal fHD, a vertical synchronizing signal fVD and video signals R, G and B are received as an input signal, a cycle for the portion of one dot in the video signal is unknown at a display side. A longitudinal total line number is measured by a total line counter 3 and the horizontal deflection frequency fHD of the input signal is obtained by an HD frequency counter 1. CPU 4 reads the result of the total line counter 3 and the HD frequency counter 1 and executes output control in the total dot number of one horizontal cycle of an input signal and the deflection frequency fHU of a unit screen. A deflection staircase generator 6 generates a horizontal deflection plate driving signal fHSS so that display is executed in accordance with the video signal of optional resolution.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display suitable for displaying video signals of arbitrary resolution in a display for displaying each picture element.

[0002]

2. Description of the Related Art Image display devices such as televisions are developed in various ways depending on the application, from projection type projectors of 100 inches or more to those of viewfinders of 1-2 inches.
Alternatively, a thin type such as a liquid crystal has been developed. Also, a thin type display is disclosed in JP-A-57-
As described in Japanese Patent No. 135590, a screen is vertically divided into a plurality of sections, and an electron beam is generated for each section.
It is known that each electron beam is deflected in the vertical direction to display a plurality of lines and a television image is displayed as a whole.

The display of the above system is considered to be one of the most effective systems for thinning the television. But C
It is considered that the device cannot be applied to a high-definition display such as AD / CAM because it has a limit in beam convergence and does not reach a commonly known cathode ray tube for display (hereinafter referred to as CDT).

Therefore, a thin display device capable of high-definition display has been considered, and its configuration will be described with reference to FIGS.

FIG. 4 shows an arrangement of divided unit screens. Although a gap is provided in the unit screen for convenience of description in the figure, there is actually no gap on the display screen.

FIG. 5 is a view showing a display system of a unit screen, which includes an electron gun 51 and a horizontal electrostatic deflection plate 52.
And a vertical electrostatic deflection plate 53 and a display surface 54.
Here, the electron gun 51 is the above-mentioned CDT (Character Dispray).
Tube) has the same structure. FIG. 6 shows the configuration of one pixel on the display surface 54.

Next, the operation will be described. The entire screen is divided into i unit screens in the horizontal direction and j unit screens in the vertical direction as shown in FIG.
The deflection plates 52 and 53 shown in FIG.
In the vertical and vertical directions, raster deflection is performed with a step wave having m steps. Here, the horizontal deflection frequency f _HU of the unit screen is f
_HU = f _HD / i. Here, f _HD is the horizontal scanning frequency of the input video signal. Further, the vertical deflection frequency f _VU of the unit screen is equal to the vertical deflection frequency f _VD of the input signal.

That is, the electron beam is generated by the electron gun 51, converged, deflected by the deflecting plates 52 and 53, and radiated to the horizontal 1 to n and vertical 1 to m dots in FIG. Furthermore, in the horizontal direction, 3 dots for each dot, R, G, B
The color image is displayed by sequentially deflecting to a step. The pixel data at this time is read from the memory for all the dots that each unit screen has. It should be noted that the memory installed in each unit is rewritten in synchronization with the input video signal.

With the above system, color selection can be performed without using a shadow mask, and the time during which a 1-dot fluorescent body is irradiated with an electron beam is i × j times that in the case of a normal CDT. Therefore, if the brightness is the same as that of a normal CDT, the beam current can be extremely reduced. Therefore, although it is thin, high-definition display is possible.

However, in this display, the resolution (signal specification) is determined when the number of dots (n, m) of the unit unit screen and the number of units (i, j) are determined.

That is, a display device paired with a video signal is used, and CAD / CAE using various video signal specifications.
The development in the field of cannot be expected.

The selected dot display method (including matrix selection, etc.) like this system is intended for TVs (standard methods such as NTSC, PAL, SECAM, etc.) whose signal specifications are clear, and liquid crystal, plasma display, etc. Is being developed at.

As an example of the matrix type display device, for example, JP-A-55-79419 and JP-A-58-23.
No. 015 publication is mentioned.

Further, a selection circuit for the input synchronization signal and a sawtooth voltage generation circuit for driving the deflection yoke in accordance with the synchronization signal output from the selection circuit, and the input synchronization signal frequency are made to correspond to each other.
To keep the output amplitude value of the sawtooth voltage generation circuit constant,
An electromagnetic deflector for controlling a power supply voltage applied to a voltage generating circuit to keep a current value flowing in a deflection yoke of a display constant and keeping a deflection size constant is disclosed in JP-A-55-55.
Japanese Patent Laid-Open No. 159668 discloses a mode determination means for determining the scanning frequency of an input video signal and a mode switching means for switching the display operation mode according to the output of this means, and video signals having different scanning frequencies are input. CRT that can be displayed by switching the operation mode even in the case
A display device is disclosed in Japanese Utility Model Publication No. 60-169686.

However, the electromagnetic deflection device merely maintains a constant deflection size on the display side, and if the specifications of the video signal are different, it may not meet the demands of the display user. The CRT display device can switch and display the element constants and the like of the display according to the frequency discrimination result. However, if a video signal having substantially the same signal scanning frequency and different display periods of signal specifications is input, a desired video image is input. Can't get the display size of.
Further, when it is attempted to deal with the details, the number of switching means becomes extremely large, the circuit scale increases, and it becomes complicated.

[0016]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks of the prior art, and within a predetermined range, arbitrary video signal specifications, scanning frequency, display video resolution, video display period with respect to scanning period, etc. It is to provide a high-definition display capable of displaying a desired image with respect to the video signal.

[0017]

A display according to the present invention includes means for generating dot clock frequency information for displaying a video based on a synchronizing signal input to the display together with a video signal, and the means for generating the dot clock frequency information. Drive signal generating means for generating a drive signal of a predetermined frequency based on dot clock frequency information. Further, the drive signal generating means is a PLL (Phase Locked Loop) circuit for generating the drive signal whose drive signal frequency can be arbitrarily set by the output of the generating means. Further, the drive signal frequency is the same as the dot lock frequency of the video signal input to the display. The present invention is characterized in that, in a display capable of displaying an image by inputting a video signal, a desired image corresponding to the video signal is displayed according to a synchronization signal input together with the video signal.

[0018]

The generating means calculates the total number of dots in one scanning period of the video signal on the basis of the synchronizing signal input together with the video signal, and generates dot clock frequency information for displaying the video. Based on the information, the drive signal generating means generates a drive signal of a predetermined frequency to display a predetermined image on the display.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION The embodiments of the present invention have been described above.
This will be described in detail with reference to FIGS. 4 to 6 and FIGS. 1 to 3 and FIGS.

FIG. 1 is a block diagram showing the configuration of a deflection signal control circuit for a unit screen according to the present invention. The deflection signal control circuit includes an HD frequency counter 1, a total line number counter 3, a unit deflection signal generator 2, a CPU 4, and a deflection staircase wave generator 6.

FIG. 2 shows a total line number counter 3 and HD.
It is a figure which shows the specific circuit of the frequency counter 1. FIG.
FIG. 3 is a time chart diagram showing the operation waveforms of FIG. 2. FIG. 7 is a diagram showing a specific circuit of the unit deflection signal generator 2.

Now, as an input signal, a horizontal synchronizing signal f _HD ,
Consider a case where the vertical synchronizing signal f _VD and the video signals R, G, B are received.

Here, the period for one dot of the video signal is unknown on the display side.

Therefore, in order to synchronously display one dot when input at one dot position of each unit on the display, the unit deflection frequency f _HU and the deflection plate driving stairs are calculated by the following algorithm. _{Find the} wave f _HSS .

It is assumed that the aspect ratio when one dot of the input signal is normally displayed is α, the aspect ratio of the display area is β, the horizontal display period ratio of the signal is τ, and the vertical display period ratio is δ.

The total number of vertical lines is measured by the total line counter 3 shown in FIG. Specifically, f _{HD is} input to the A input of FIG.
Input f _VD to B input. In FIG. 2, D-type flip-flops (DFFs) 31 and 32 change the state of being input to the D input when a rising edge is input to the CP input.
Move to output. Further, the Q output is set to "L" at the logic level LOW (hereinafter referred to as "L") to the R input.

The output of each stage of the 2 (n-1) advance counter 33 is output as Q1 ... Qn. Further, when the R input is "L", all outputs Q1 ... Qn are reset to "L".

In the n-bit latch 34, the state of each D is transferred to each Q at the rising edge input to the LD terminal. D
The FF 31 is set at the rising time t ₁ of B. DFF
32 is not set for the first time at time t ₂ , the Q inverted output becomes “L”, and the Q inverted output causes the DFF 31 and
The counter 33 is reset at the same time, and the Q output becomes “L” at time t ₄ in both cases.

The latch 34 outputs the output of the counter 33 at the time t ₃ (before the counter 33 is reset at the time t ₄ and indicates the total number of vertical lines) to F of FIG.
Latch as shown in. Therefore, the latch 34, the time t ₄
Therefore, the total number of vertical lines is always output except the transition period of a slight state.

If the vertical total number of lines obtained above is Ne, the total number of dots N _DH during one horizontal period of the input signal is

[0031]

(Equation 2) Becomes

Further, the dot configuration of the unit screen is the horizontal n and vertical m configuration shown in FIG. 6 as described above.

Here, the horizontal display period ratio τ of the unit screen
_{If U} is the same τ as the input signal, the number N _U of unit screens required to display all the input signals can be obtained by an integer obtained by rounding up N _DH / n to the right of the decimal point.

Next, the horizontal deflection frequency f _HD of the input signal is obtained. f _HD is detected by the HD frequency counter. HD
The specific configuration of the frequency counter is the circuit shown in FIG. 2 having the same configuration as the total line counter 3 described above.
_{To the HD} and B inputs, a reference time Tref pulse (a cycle such as a 1-second cycle pulse is clear and 1 / f _HD << Tref) is input. Here, when Tref = 1 sec, the output F of the latch 34 can detect f _HD in units of Hz.

From this, the deflection frequency f of the unit screen
_HU is

(Equation 3)

(Here, N _U is the number of unit screens, f _HD
Is the number of horizontal dots).

F _HU is obtained by dividing f _HD by N _U by the unit deflection signal generator 2. Specifically, it can be realized by the circuit shown in FIG. Presettable subtraction counter 21
By presetting the information of N _U from the D _{1 to} Dn inputs at the time when all the flip-flops of each digit become “L” (at the time when the hanging output B becomes “H”) as a result of the subtraction. , The input signal H _D can be _divided by N _U.

Here, the total line counter 3 and H
The CPU 4 controls the reading of the result of the D frequency counter 1, the calculation of the above equations (1) and N _U , and the output of the preset value (N _U ) to the unit deflection signal generator.

Next, the frequency f of the staircase wave for driving the horizontal deflection plate
_Ask for _HSS . f _HSS needs to be exactly 3 / N _U times the dot frequency of the input video signal when the dot configuration is the vertical stripe of each color shown in FIG. (If a dot configuration for each Iroyoko stripe, f _HSS is 1 / N _U times the exact dot clock, in other dot configurations, according to calculation by the algorithm)

From the above, f _HSS is _calculated by the following equation (3).

[0041]

(Equation 4) (Here, τ _U is the horizontal display period ratio of the unit screen, n is the number of horizontal dots of the unit screen, and N _DH is the number of horizontal display dots of the input video signal.)

However, although f _HSS needs to be accurately synchronized with the input signal as described above, τ _U for obtaining the above equation (3), α for obtaining N _DH in the equation (1), β, τ,
Each value of δ is an estimated value from a general display signal. Therefore, f _HSS needs to be finely adjusted by observing the screen. That is, the video signal input to the display of the present invention is generally created on the computer side, and the number of clocks (created on the computer side) when creating the video signal with horizontal resolution, that is, the number of dot clocks. Stipulated in. On the other hand, the resolution in the vertical direction is defined by the number of horizontal scanning lines. The horizontal synchronizing signal and the vertical synchronizing signal are also created based on the dot clock. Therefore, if the number of dots in one horizontal scanning period of the video signal is obtained based on the sync signal input together with the video signal, the PLL for generating the output signal synchronized with the horizontal sync signal is obtained.
The circuit can generate a drive signal synchronized with the dot clock. At this time, the drive signal is completely synchronized with the video signal. By the way, in the calculation means for calculating the total number of dots of the present invention, since there is a part that uses the preset value, that is, the estimated value from the general display signal, the actual video signal and the drive signal of the calculation result The frequency may be slightly shifted, and the drive signal and the video signal may not be synchronized. In this case, the predetermined image cannot be obtained. Therefore, the present invention is provided with means for increasing or decreasing the output set value of the arithmetic means so as to synchronize the video signal and the drive signal.

The method of adjustment will be described below. First, a specific circuit of the deflected staircase wave generator 6 is shown in FIG. FIG.
Since this is a generally known PLL (Phase Locked Loop), detailed description thereof will be omitted. The PLL circuit includes a phase detector 6
1, a low pass filter (LPF) 62, a voltage controlled oscillator (VCO) 63, an inverter 65, and a presettable counter 64, and performs the same operation as in FIG.

The operation is based on the preset value (D ₁ input to the presettable subtraction counter 64 synchronized with the frequency of f _HU.
.About.Dn) times the frequency f _HSS is generated.

Therefore, for fine adjustment, the CPU 4 may sequentially add or subtract the presettable value of the presettable subtraction counter 64 while observing the screen.

In addition, the unit screen and the dots of the unit screen that are not effective for display in the above system are blanked.

The effective unit screen may be selected by any combination as long as the input video signal can be normally displayed.

For the sake of convenience, in the concrete circuits shown in FIGS. 2, 7, and 8, the counter addition, subtraction, or flip-flop type and its input condition are designated, but the operation algorithm is the same. If it is, the type and the input condition do not matter.

Although f _HSS is obtained by multiplying f _HU , it may be obtained directly from f _{H D according} to equations (1), (2) and (3).

[0050]

By using the display device of the present invention,
In high-definition displays, display of arbitrary signal specifications (scanning frequency, resolution, etc.) receives a sync signal and a video signal (even if the sync signal is superimposed on the video signal, but a sync signal separation circuit is required) It can be displayed only.

Further, the signal specification judgment means can control the display control means based on the calculation result to display the video signal in a predetermined state, and the calculation means can freely set the display state. Even if a video signal having signal specifications is input to the display of the present invention, the video signal can be displayed in a display state desired by the display user or in a preset display state.

Further, in the display of the present invention, the deflection driving signal frequency is desired by calculating the total number of dots in one horizontal scanning period of the video signal from the vertical line and horizontal deflection frequency of the video signal detected by the detecting means by the calculating means. And the fine adjustment of the signal frequency can be easily performed while looking at the front screen without increasing the circuit scale or complicating.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a deflection signal control circuit for a unit screen according to the present invention.

[FIG. 2] Total line number counter 3, HD frequency counter 1
3 is a block diagram showing a specific circuit configuration of FIG.

FIG. 3 is a time chart showing the operation of FIG.

FIG. 4 is an explanatory diagram showing a configuration of a unit screen.

FIG. 5 is an explanatory diagram showing a configuration of a deflection system including an electron gun on a unit screen.

FIG. 6 is an explanatory diagram showing a dot configuration of a unit screen.

FIG. 7 is a block diagram showing a specific circuit configuration of a unit deflection signal generator.

FIG. 8 is a block diagram showing a specific circuit configuration of a deflected staircase wave generator.

[Explanation of symbols]

 1 HD Frequency Counter 2 Unit Deflection Signal Generator 3 Total Line Number Counter 4 CPU 6 Deflection Step Wave Generator 21,64 Subtraction Counter 22,65 Inverter 31,32 D-type Flip-flop 33 Addition Counter 34 Latch 51 Electron Gun 52,53 Electrostatic deflector 54 Display surface 61 Phase detector 62 Low pass filter 63 Voltage controlled oscillator

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Akira Wada 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi Imaging Information Systems Co., Ltd.

Claims (5)

[Claims] 1. A display capable of displaying an image by inputting an image signal, and means for generating dot clock frequency information for displaying the image based on a synchronization signal input together with the image signal, A drive signal generating means for generating a drive signal having a predetermined frequency based on the dot clock frequency information generated by the generating means. 2. The dot clock frequency information generating means is defined by the following equation: (Here, N _DH is the total number of dots in one scanning period of the video signal, Ne is the total number of vertical lines detected by the detecting means,
τ is the horizontal display period ratio of the video signal, δ is the vertical display period ratio of the video signal, α is the aspect ratio of one dot, and β is the aspect ratio of the display area. The display according to claim 1, wherein the dot clock frequency information is generated based on the total number of dots in a constant cycle of the video signal. 3. The drive signal generating means includes a PLL (Phase Locked Loop) circuit for generating the drive signal, and the PLL circuit can arbitrarily set the drive signal frequency by the output of the generating means. The display according to claim 1 or 2, which is a transparent display. 4. The adjustment for arbitrarily setting the drive signal frequency is performed on the display driven by the drive signal from the drive signal generating means for generating the drive signal at the drive signal frequency generated by the generating means. The display according to claim 3, which is performed by increasing or decreasing the output of the generating means and finely adjusting the drive signal frequency while observing the display screen. 5. The display according to claim 1, wherein the drive signal frequency is the same as a dot lock frequency of a video signal input to the display.