JPH09114771A - Direct memory access device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To perform direct memory access only in the case of data reception when direct memory access request signals are inputted. SOLUTION: At the time of receiving data sent from a communicating party 10, a chip 3 for communication asserts interruption signals 8 and the interruption signals 8 are inputted to the /DREQ terminal 13 of this DMA device 4 as the DMA request signals. The DMA device 4 obtains an address data bus 5, reads the contents of a status register 6 by using the address data bus 5, judges the contents of interruption by a status register judgement circuit 12 and performs the DMA only in the case of the data reception.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access device for transferring data between a data input / output unit and a memory without going through a CPU (central processing unit).

[0002]

2. Description of the Related Art FIG. 5 shows an example of the configuration of an electronic device having a CPU and a memory for exchanging data with the outside. This electronic device is a CPU 101.
And a memory (random access memory) 102,
A communication chip 103 that inputs and outputs data to and from a communication partner 110 and a timing generation circuit 104 are provided.

The CPU 101, the memory 102 and the communication chip 103 are connected to each other by an address / data bus 105. The communication chip 103 has a status register 106. Timing generation circuit 10
4 is connected to the CPU 101, the memory 102, and the communication chip 103, and the memory 102 and the communication chip 1
The control signal 107 is sent to the port 03. The communication chip 103 sends an interrupt signal 108 to the CPU 101.

In the configuration shown in FIG. 5, when communicating with the communication partner 110, the communication chip 103 is usually the communication partner 1
When the data from 10 is received, the interrupt signal 1
08 is sent to the CPU 101. When the CPU 101 receives the interrupt signal 108, the CPU 101 reads the status register 106 in the interrupt routine, and only when it is found that the result is an interrupt for data reception, data (not shown) in the communication chip 103 is read. Read the register. Next, the CPU 101 writes the received data in the memory 102 and ends the communication operation. In the case of such an operation, an interrupt occurs each time data is received, and the CPU 101 has to move the data to the memory 102, which increases the load on the CPU 101 and takes time. .

Therefore, in order to solve the above problems, as shown in FIG. 6, direct memory access (hereinafter referred to as D
Also referred to as MA. ) A device is used. The electronic device shown in FIG. 6 includes a CPU 101, a memory 102, a communication chip 103, and a DMA device 111. Also,
CPU 101, memory 102, and communication chip 103
Are connected to each other by an address / data bus 105. Communication chip 103 is status register 1
06.

The DMA device 111 has a DMA request terminal (hereinafter referred to as a / DREQ terminal) 112, and the / DREQ terminal 112 receives an interrupt signal 108 from the communication chip 103 as a DMA request signal. It is supposed to be entered. The DMA device 111 is connected to the CPU 101, the memory 102 and the communication chip 103, and sends a control signal 107 to the memory 102 and the communication chip 103. In the configuration shown in FIG. 6, when the communication chip 103 receives data from the communication partner 110, it sends an interrupt signal 108 to the DMA device 111, and the DMA device 111 causes a data register (not shown) in the communication chip 103 to operate. Read and write data to memory 102.

[0007]

However, the configuration shown in FIG. 6 has a problem that the DMA device 111 goes to read the data register even when the interrupt is asserted due to a factor other than the data reception. . By the way, when writing the data from the communication partner 110 to the memory 102, normally, an area of a certain size is taken in the memory 102, and the communication partner 11 is sequentially arranged from the beginning of this area.
The data is written from 0, and when the end of the area is reached, control is returned to the beginning of the area. Conventionally, DMA
Since the size of the transfer destination area cannot be specified by the device 111, there are only the transfer destination address increment mode (mode in which the transfer destination address is sequentially increased) and the decrement mode (mode in which the transfer destination address is sequentially decreased). If the destination address reaches the end of the area (the end address of the area in the increment mode, the start address of the area in the decrement mode), C
There is a problem that the PU 101 needs to reset the DMA transfer destination address.

Conventionally, whether the device of the data transfer source is an 8-bit device or a 16-bit device, the operation of the DMA is to read the data of the transfer source once and write it once to the transfer destination. Was going on. Therefore, even if the data bus width is, for example, 32 bits, only 8-bit or 16-bit data can be transferred at one time, and the number of times of data transfer increases, and the DMA
There was a problem that it took time.

Therefore, a first object of the present invention is to provide a direct memory access device capable of performing direct memory access only when receiving data when a direct memory access request signal is input. It is in. A second object of the present invention is to
It is an object of the present invention to provide a direct memory access device capable of transferring data to a fixed area in a memory without resetting a transfer destination address. Also,
A third object of the present invention is to provide a direct memory access device capable of performing direct memory access at high speed by reducing the number of data transfers.

[0010]

According to a first aspect of the present invention, in a direct memory access device for performing direct memory access between a data input / output unit and a memory, an interrupt signal output from the data input / output unit is transmitted. Whether to input the direct memory access request signal and read the interrupt type information held in the data input / output unit when the direct memory access request signal is input, and perform direct memory access according to the contents. It is configured to select whether or not to achieve the first object. In this direct memory access device, when the interrupt signal output from the data input / output unit is input as the direct memory access request signal, the information on the type of interrupt held in the data input / output unit is read and the contents thereof are read. Whether to perform direct memory access or not is selected according to.

According to the second aspect of the invention, the area designating means for designating the area of the data transfer destination including the size of the area in the direct memory access device for performing the direct memory access between the data input / output unit and the memory. And the address of the data transfer destination is specified in ascending or descending order within the area specified by the area specifying means, and when the address of the data transfer destination reaches the end or the beginning of the area, the address of the data transfer destination is set to the area. And a data transfer destination addressing means for returning to the beginning or end of the second
Achieve the objectives. In this direct memory access device, the area designation means designates the area of the data transfer destination including the size of the area, and the data transfer destination address designation means specifies the ascending or descending order within the area designated by the area designation means. The address of the data transfer destination is designated, and when the address of the data transfer destination reaches the end or the beginning of the area, the address of the data transfer destination is returned to the beginning or the end of the area.

According to a third aspect of the present invention, in the direct memory access device according to the second aspect, a processing end address is stored which indicates up to which address the transferred data in the area designated by the area designating unit has been processed. When the data transfer destination address matches the processing end address held by the processing end address holding means, direct memory access is not performed until the processing end address changes. It is a thing. In this direct memory access device, the processing end address holding means holds the processing end address indicating up to which address the transferred data has been processed in the area designated by the area designating means, and the data transfer destination address is When it coincides with the processing end address held by the processing end address holding means, direct memory access is not performed until the processing end address changes.

According to another aspect of the present invention, in a direct memory access device for performing direct memory access between a data input / output unit and a memory, data is transferred from the data input / output unit until the total transfer data width matches the data bus width. After the data is read, the data is written in the memory in one write operation to achieve the third object. In this direct memory access device, after reading the data from the data input / output unit until the total transfer data width matches the data bus width, these data are written in the memory by one write operation.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION A preferred embodiment of a direct memory access device of the present invention will be described below with reference to FIG.
This will be described in detail with reference to FIG. FIG. 1 is a block diagram showing a configuration of an electronic device including a direct memory access device (hereinafter, referred to as a DMA device) according to a first embodiment of the present invention. This electronic device includes a CPU 1,
A memory (random access memory) 2 serving as a reception buffer, a communication chip 3 for inputting / outputting data to / from a communication partner 10, and a DMA device 4 are provided.

The CPU 1, memory 2, communication chip 3 and DMA device 4 are connected to each other by an address / data bus 5. The communication chip 3 has a status register 6 that holds status information including information on the type of interrupt, and a data register 11 that holds received data. The DMA device 4 has a status register determination circuit 12 that determines the contents of the status information in the status register 6. Further, the DMA device 4 has a DMA request terminal (hereinafter, referred to as a / DREQ terminal) 13, and a DM request terminal 13
As the A request signal, the interrupt signal 8 from the communication chip 3 is input. Also,
The DMA device 4 is connected to the CPU 1, the memory 2 and the communication chip 3, sends a control signal 7 to the memory 2 and the communication chip 3, and sends an interrupt signal 1 to the CPU 1.
4 and the bus control signal 15 are transmitted.

FIG. 2 is an explanatory diagram showing an example of the contents of the status register 6 in FIG. In this example, the status register 6 has an 8-bit configuration, and when the bit b0 is “1”, it indicates that the communication error has occurred, and when the bit b1 is “1”, it indicates that the data reception interrupt has occurred. As shown.

Next, the operation of the electronic equipment including the DMA device 4 according to the present embodiment will be described. Communication chip 3
When receiving the data sent from the communication partner 10, asserts the interrupt signal 8. This interrupt signal 8 is DM request signal, DM
It is input to the / DREQ terminal 13 of the A device 4. Then
The DMA device 4 operates according to the following procedure. 1. First, in order to acquire the address / data bus 5,
The bus control signal 15 requests the CPU 1 to release the bus. 2. When the bus is taken, the contents of the status register 6 are read using the address / data bus 5, and the contents of the interrupt are judged by the status register judging circuit 12.

3. If the bit b1 is "1", it means that the data reception is interrupted. Therefore, the received data is transferred from the data register 11 to the memory 2 by DMA. 4. If the bit b1 is "0", the interrupt is not a data reception interrupt, and therefore the CPU 1 asserts the interrupt signal 14 to cause error processing. 5. The bus is released and the usage right is returned to the CPU1.

As described above, according to the present embodiment, the DMA
When the device 4 receives the interrupt signal 8, it automatically determines whether or not the interrupt is for data reception, and the DMA is performed only when data is received. The problem that the DMA device 4 goes to read the data register 11 when the signal 8 is asserted is eliminated. Also, the CPU 1 is DM
CPU when the DMA using the device A 4 is not performed
The processing time during which one itself has transferred the data to the memory 4 can be devoted to other processing, and the performance of the electronic device as a whole is improved.

Next, D according to the second embodiment of the present invention
The MA device will be described. DMA according to the present embodiment
As shown in FIGS. 3A to 3C, the device 4 has a 16-bit DMA transfer destination setting register, D, respectively.
It has an MA transfer address counter and a DMA transfer address counter valid bit setting register. A transfer destination address is set in the DMA transfer destination setting register. The DMA transfer address counter increments or decrements each time data is transferred.

The DMA transfer address counter valid bit setting register is designed to specify the size of the area of the data transfer destination which becomes the receiving buffer in the memory 2. D
The MA transfer destination setting register and the DMA transfer address counter valid bit setting register correspond to the area designating means in the present invention.
The transfer address counter corresponds to the data transfer destination address designating means in the present invention.

In this embodiment, when the transfer destination address is set in the DMA transfer destination setting register, the same contents are loaded in the DMA transfer address counter. The DMA transfer address counter increments or decrements each time data is transferred. As shown in FIG. 3D, the actual DMA transfer address is the value of the DMA transfer address counter having the same bit as the bit set to “1” in the DMA transfer address counter valid bit setting register (FIG. 3B). , And the DMA is shown).
This is combined with the value of the DMA transfer destination setting register of the same bit as the bit set to "0" in the transfer address counter valid bit setting register (shown by the hatched portion in FIG. 3A). Therefore, when the address of the data transfer destination reaches the end or the beginning of the area of the data transfer destination, the address of the data transfer destination is returned to the beginning or the end of the area of the data transfer destination.

As described above, according to the present embodiment, the DMA
The size of the transfer destination area can be determined, and when the data transfer destination address reaches the end or the beginning of the data transfer destination area, the data transfer destination address is set to the beginning or end of the data transfer destination area. Since the data can be returned, the CPU 1 does not need to reset the address of the data transfer destination. Other configurations, operations and effects are similar to those of the first embodiment.

Next, D according to the third embodiment of the present invention
The MA device will be described. When the size of the area of the data transfer destination serving as the reception buffer is determined as in the second embodiment, the reception buffer becomes full before the CPU 1 processes the data in the reception buffer, and the data is overwritten. There is a risk that Therefore, in the present embodiment, the DMA device 4 is provided with a processing end address register that holds a processing end address that indicates up to which address the transferred data has been processed in the data transfer destination area. The processing end address register is written by the CPU 1.

The DMA device 4 performs the DMA to execute the memory 2
When receiving data is written in, the data is written up to the address indicated by the processing end address register. When the address of the data transfer destination has already become the same value as the address indicated by the processing end address register, the processing of the CPU 1 proceeds, and the address of the data transfer destination is not changed until the content of the processing end address register changes, Wait without executing DMA. CPU1 is memory 2
After the processing of the data transferred to, the processing end address is changed by the amount by which the processing is completed and written in the processing end address register. Thus, according to the present embodiment, it is possible to prevent the received data from being overwritten and the data being lost. Other configurations,
The operation and effect are similar to those of the second embodiment.

Next, D according to the fourth embodiment of the present invention.
The MA device will be described. In this embodiment, the DMA device 4 is provided with a DMA bus width register as shown in FIG. This DMA bus width register has, for example, an 8-bit configuration, and when bits b1 and b0 are "00", DM
Indicates that the A data width is 8 bits, and bit b1,
When b0 is "01", it indicates that the DMA data width is 16 bits, and when bits b1 and b0 are "10", it is DM.
Indicates that the A data width is 32 bits, and bit b
“11” of 1 and b0 is prohibited. In the present embodiment, the data bus width is 32 bits. Also, bit b2 of the DMA bus width register is
When it is "0", it indicates that it is set to BIG ENDIAN, and when it is "1", it indicates that it is set to LITTLE ENDIAN. The DMA bus width register is designed to be written by the CPU 1.

The DMA device 4 according to this embodiment operates as follows. 1. Before the DMA device 4 performs the DMA, the CPU 1 sets the DMA bus width register in advance. 2. Bits b1 and b0 of the DMA bus width register are "1"
When set to 0 ", that is, the DMA data width is 3
When it is set to 2 bits, the DMA device 4 writes once for each read. 3. Bits b1 and b0 of the DMA bus width register are "0"
When set to 1 ", that is, the DMA data width is 1
When set to 6 bits, the DMA device 4 performs two reads, creates 32-bit data, and performs one write. In this case, when bit b2 of the DMA bus width register is set to "0", that is, BI
When set to G ENDIAN, when the read data of two times are arranged in the order of upper 16 bits and lower 16 bits to make 32-bit data, and bit b2 of the DMA bus width register is set to "1" That is, when it is set to LITTLE ENDIAN, two read data are arranged in the order of lower 16 bits and upper 16 bits to form 32-bit data.
The data is latched in the data register 11 until the 32-bit data is collected.

4. Bit b1 of the DMA bus width register
When b0 is set to "00", that is, when the DMA data width is set to 8 bits, the DMA device 4
Reads out four times, creates 32-bit data, and writes once. In this case, when the bit b2 of the DMA bus width register is set to “0”, that is, when it is set to BIG ENDIAN, read data of four times are arranged in order from the upper side and 32
When bit data is created and bit b2 of the DMA bus width register is set to "1", that is, LIT
When set to TLE ENDIAN, read data of four times are arranged in order from the lower side to form 32-bit data.

As described above, according to this embodiment, when the data width is smaller than the data bus width, the data is read until the total of the data widths matches the data bus width.
Since these data are written in the memory 2 by one writing operation, the number of times of data transfer can be reduced,
DMA can be performed at high speed. Although the data bus width is 32 bits in the present embodiment, it is not limited to this. Other configurations, operations and effects are similar to those of the first, second or third embodiment.

[0030]

As described above, according to the direct memory access device of the first aspect, when the interrupt signal output from the data input / output unit is input as the direct memory access request signal, Since the information of the interrupt type held in is read and whether or not direct memory access is performed is selected according to the contents, when the direct memory access request signal is input, the data reception Direct memory access can only be done if

According to another aspect of the direct memory access device of the present invention, the area specifying means specifies the area of the data transfer destination including the size of the area, and the data transfer destination address specifying means causes the area specifying means. Specify the data transfer destination address in ascending or descending order within the area specified by, and return the data transfer destination address to the beginning or end of the area when the data transfer destination address reaches the end or beginning of the area. Since this is done, data can be transferred to a fixed area in the memory without resetting the transfer destination address.

According to another aspect of the direct memory access device of the present invention, the processing end address holding means indicates the end of processing which indicates up to which address the transferred data in the area designated by the area designating means has been processed. When the address is held and the data transfer destination address matches the processing end address held by the processing end address holding means, direct memory access is not performed until the processing end address changes.
In addition to the effect of the direct memory access device according to the second aspect, it is possible to prevent the data from being overwritten and lost in the area of the data transfer destination.

According to another aspect of the direct memory access device of the present invention, after the data is read from the data input / output unit until the total transfer data width matches the data bus width, these data are written once. Since the data is written in the memory by the operation, the number of times of data transfer can be reduced and the DMA can be performed at high speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an electronic device including a direct memory access device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an example of contents of a status register in FIG.

FIG. 3 is an explanatory diagram for explaining the operation of the direct memory access device according to the second embodiment of the present invention.

FIG. 4 is an explanatory diagram showing contents of a DMA bus width register in a direct memory access device according to a fourth embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration of a conventional electronic device that transfers received data to a memory using a CPU.

FIG. 6 is a block diagram showing a configuration of a conventional electronic device that transfers received data to a memory by a DMA device.

[Explanation of symbols]

 1 CPU 2 Memory 3 Communication Chip 4 DMA Device 5 Address / Data Bus 6 Status Register 12 Status Register Judgment Circuit

Claims (4)

[Claims] 1. A direct memory access device for performing direct memory access between a data input / output unit and a memory, wherein an interrupt signal output from the data input / output unit is input as a direct memory access request signal, and When the direct memory access request signal is input, the information of the interrupt type held in the data input / output unit is read, and whether to perform the direct memory access is selected according to the content. Direct memory access device. 2. A direct memory access device for performing direct memory access between a data input / output unit and a memory, and area specifying means for specifying a data transfer destination area including the size of the area, and this area. The address of the data transfer destination is specified in ascending or descending order within the area specified by the specifying means, and when the address of the data transfer destination reaches the end or the beginning of the area, the address of the data transfer destination is set to the beginning of the area. Alternatively, the direct memory access device is provided with a data transfer destination address designating means for returning to the end. 3. The data transfer destination address is further provided with a processing end address holding means for holding a processing end address indicating up to which address the transferred data in the area designated by the area designating means has been processed. 3. The direct memory access device according to claim 2, wherein when the processing end address held by the processing end address holding unit matches, the direct memory access is not performed until the processing end address changes. 4. A direct memory access device for performing direct memory access between a data input / output unit and a memory, wherein data is read from the data input / output unit until the total transfer data width matches the data bus width. After that, these data are written in the memory by one writing operation, a direct memory access device.