JPH09113932A - Wiring board and its production - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the productivity of a wiring board laminated and formed with wirings via insulating layers by lithography method by divided exposure. SOLUTION: This board is formed with plural pieces of the wirings 4, the first insulating layer covering the wirings 4, terminals 7 connected to the wirings 4, the plural wirings 5 on the first insulating layer, the second insulating layer covering the wirings 5 and terminals 8 connected to the wirings 5 respectively by at least the lithography method of the divided exposure. In such a case, the terminals 7 and 8 are formed of the same conductive films. The wirings 4 and the terminals 7 are connected via the contact holes formed in the first insulating layer. The wirings 5 and the terminals 8 are connected via the contact holes formed in the second insulating layer. The terminals 7 and 8 and pixel electrodes 6 of the TFT substrate for a liquid crystal display panel are formed of the same conductive films.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a plurality of first wirings, a first insulating layer that covers the first wirings, a first lead terminal connected to the first wirings, and Each of the plurality of second wirings on the first insulating layer, the second insulating layer covering the first wirings, and the second lead terminal connected to the second wirings is divided and exposed. The present invention relates to a wiring substrate formed at least by the above-mentioned lithographic method and a manufacturing method thereof, and particularly to a TFT substrate used for a liquid crystal display panel and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 4 is an explanatory view of a schematic structure of a conventional TFT substrate for a liquid crystal display panel, FIG. 5 is an explanatory view of a main structure of a conventional TFT substrate for a liquid crystal display panel, and FIG. 6 is an AA line of FIG. It is explanatory drawing of a cross section and a BB cross section.

In FIG. 4, a TFT substrate 1 in which a large number of TFTs, wirings thereof, and pixel electrodes are formed in a matrix is divided into a display area surrounded by a two-dot chain line 2 in the drawing and a terminal forming area around the display area. To be done.

The display area is divided into six exposure areas 2a, 2b, 2c, 2d, 2e and 2f, for example, as shown by the broken lines in the figure, and the terminal formation area is divided by the broken lines in the figure. As shown in Figure 3, the three areas 3a, 3b, 3c above the display area, the three areas 3d, 3e, 3f below the display area, the two areas 3g and 3h on the right side of the display area, and the left side of the display area. The two areas 3i and 3j are divided.

In FIG. 5, in which the interlayer insulating film and the like are omitted, 2
In the display area inside the dotted line 2, the gate electrode 4 of the TFT
a, a large number of gate wirings (first wirings) 4 communicating with each other, and T
A large number of source / drain wirings (second wirings) 5 communicating with the source electrode 5a of the FT, a pixel electrode 6 and the like are formed,
Outside the display region, a lead terminal 7 for the gate wiring 4 and a lead terminal 8 for the source / drain wiring 5 are formed.

In FIGS. 5 and 6, 5b is a drain electrode, 9 is a channel protective film, 10 is a glass substrate, and 11 is SiN.
Gate insulating film, 12 is an amorphous silicon layer,
Reference numeral 13 is a cover film made of SiN, the gate wiring 4 and the source / drain wiring 5 overlap with each other through the gate insulating film 11, and the drain electrode 5b and the pixel electrode 6 are contact holes provided in the cover film 13. Connected through 14.

The gate wiring 4 formed in the display areas 2a to 2f, the lead terminal 7 formed in the areas 3g to 3j, the source / drain wiring 5 formed in the display areas 2a to 2f, and the areas 3a to 3f. Each of the lead terminals 8 is formed of the same conductive film.

Therefore, in the manufacture of the conventional TFT substrate 1 by the division exposure using the photolithography technique, the gate wiring 4, the gate electrode 4a, the terminal 7 are formed, the source / drain wiring 5, the source electrode 5a and the drain electrode 5b are formed. , The formation of the terminal 8, the formation of the channel protective film 9, and the formation of the contact hole 14, respectively, five kinds of masks and 16 exposure steps, that is, one mask corresponding to the areas 2a to 2f and the areas 3a to 3c. One corresponding mask and areas 3d to 3f
One mask corresponding to 1 and 1 corresponding to the regions 3g and 3h
A total of five types of masks and one mask corresponding to the regions 3i and 3j, and regions 2a to 2f and 3a to 3j.
Therefore, a total of 16 exposure steps are required, and since one type of mask and 6 exposure steps are required to form the pixel electrode 6, a total of 21 types of masks and 70 exposure steps are required. there were.

[0009]

As described above, the conventional TFT substrate 1 requires a great variety of masks and a large number of exposure steps. However, in a display of a word processor, a personal computer or the like, a liquid crystal is used. Display panels have been widely used, and there has been a strong demand for improvement in productivity and cost reduction of the TFT substrate 1.

[0010]

SUMMARY OF THE INVENTION The present invention is intended to reduce the number of exposure masks and the number of exposures (the number of shots) required to improve the productivity and cost of a wiring board having a laminated structure. A first wiring and a first wiring covering the first wiring
Insulating layer, a first lead terminal connected to the first wiring, a plurality of second wirings on the first insulating layer, and a second insulating layer covering the second wiring. And the second lead-out terminal connected to the second wiring is formed at least by the lithography method of divided exposure, in the wiring board, the first lead-out terminal and the second lead-out terminal are the third. The first lead-out terminal and the first wiring formed from the first conductive film,
Connected through a contact hole provided in the insulating layer of
A wiring board in which the second lead terminal and the second wiring formed of the second conductive film are connected via a contact hole provided in the second insulating layer, and the first wiring
Wiring is one of a source drain wiring or a gate wiring of a thin film transistor (TFT), and the second wiring is the other of the source drain wiring or the gate wiring,
A wiring board in which a pixel electrode connected to the TFT and the first and second lead terminals are formed from the third conductive film made of a transparent conductive material by a lithography method of divided exposure, and a surface of the substrate The first wiring is formed from the first conductive film deposited on the substrate by a lithography method of divided exposure using a negative resist, and the positive resist is used from the first insulating film deposited on the first wiring. And exposing the end portion of the first wiring by the divided exposure lithography method.
Second insulating layer is formed, the second wiring is formed on the second conductive film deposited on the insulating layer by a lithography method of divided exposure using a negative resist, and the second wiring is deposited on the second wiring. The second insulating layer exposing the exposed portions of the end portions of the second wiring and the end portions of the first wiring is formed from the insulating film by a lithography method of divided exposure using a positive type resist, and A method for manufacturing a wiring board, in which the first and second lead terminals are formed from a third conductive film by a split exposure lithography method using a positive resist, and further, the first wiring is a source / drain wiring of a TFT. Alternatively, it is one of the gate wirings, the second wiring is the other of the source drain wirings or the gate wirings, and the pixel electrode connected to the TFT and the first and second lead terminals are
It is a method of manufacturing a wiring board, which is formed by a lithography method of divided exposure from a third conductive film made of a transparent conductive material.

In the wiring board having such a structure and the manufacturing method thereof, the first wiring is formed from the first conductive film, and the second wiring is formed.
Contacts formed from a first conductive film, first and second lead terminals formed from a third conductive film, and the first wires and the first terminals are contacts formed in a first insulating film. The connection is made through a hole, and the second wiring and the second terminal are connected through a contact hole formed in the second insulating film.

As a result, the liquid crystal display panel TFT substrate requires 21 kinds of exposure masks and 70 times of exposure shots as described above. However, as will be described later in detail, 9 kinds of exposure masks and 40 times of exposures are performed. Can be manufactured with a shot.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an example of application of the present invention, TF.
FIG. 2 is an explanatory diagram of a schematic configuration of a T substrate, FIG. 2 is an explanatory diagram of a main configuration of a TFT substrate that is an application example of the present invention, and FIG. 3 is an explanatory diagram of a CC cross section and a DD cross section in FIG.

In FIG. 1, a plurality of (two in the figure) TFs
In the glass substrate 21 from which the T substrate can be cut out, the one-dot chain line 22
The area surrounded by is a TFT substrate cut-out area, the area surrounded by the chain double-dashed line 2 is the display area of the TFT substrate, and the display area where a large number of TFTs, their wirings and pixel electrodes are formed is As shown by the broken lines in the figure, it is divided into six areas 2a, 2b, 2c, 2d, 2e, 2f and formed outside the display area, that is, in the area sandwiched between the one-dot chain line 22 and the two-dot chain line 2. A lead terminal formed from the pixel electrode forming conductive film in the display region is formed. Each area 2a, 2b, 2c, 2d, 2e,
Within 2f, for example, several hundreds × several hundreds of TFTs and pixel electrodes are formed.

In FIG. 2 and FIG. 3 where the same reference numerals are used for the same parts as in the conventional structure, a large number of TFTs on the substrate 21
Is a gate electrode 4a communicating with the gate wiring 4, a source electrode 5a communicating with the source / drain wiring 5, a channel protective film 9, and a source electrode 5a, as in the conventional TFT.
And a drain electrode 5b formed from the same film as
The drain electrode 5b and the pixel electrode 6 are covered by the cover film 13 (see FIG.
The contact hole 14 (see FIG. 6A) formed in FIG.
(See (a)).

Many gate wiring lead terminals 7, terminals 7
The connecting line 7a connecting the wiring 4 and the wiring 4, the source / drain wiring lead-out terminal 8, and the connecting line 8a connecting the terminal 8 and the wiring 5 are formed of the same transparent conductive film (ITO film) as the pixel electrode 6, In the display area indicated by the chain double-dashed line 2, the gate wiring 4 is connected to the connection line 7a, and the source / drain wiring 5 is connected to the connection line 8a.

In FIG. 3A showing the connection between the gate wiring 4 and the connection line 7a, the gate insulating film 11 is provided with a contact hole 23 exposing the end of the wiring 4, and the cover film 13 is provided with a contact hole 23. Wiring 4 exposed in contact holes 23 and 25 by providing contact hole 25 for exposing
The connection line 7a is connected to the end of the.

In FIG. 3B showing the connection between the source / drain wiring 5 and the connection line 8a, the end of the wiring 5 formed on the gate insulating film 11 has a contact hole 24 formed in the cover film 13. It is exposed inside, and the connecting wire 8a is connected to the exposed portion.

The photoresist film is exposed and developed to form a resist pattern, and a photolithographic technique for selectively removing an unnecessary portion of a required film is used.
When manufacturing the FT substrate, the gate wiring 4, the gate electrode 4a, the source / drain wiring 5, and the source electrode 5 are formed.
a, the drain electrode 5b, the channel protective film 9, and the contact hole 14 are subjected to six exposure steps each corresponding to one type of mask and regions 2a to 2f, and the pixel electrode 6 and the terminal 7 are formed. And 8 and the connecting lines 7a and 8a, one kind of mask for forming the pixel electrode 6 and four kinds of masks corresponding to the areas 3a to 3c, 3d to 3f, 3g and 3h, 3i and 3j, totaling 5 kinds. And the mask for forming the pixel electrode 6 are used for six times of division exposure, and four types of masks for forming terminals and the like are used to form each of the regions 3a to 3j by exposing 10 times.

Therefore, the total number of masks required is nine, and the total exposure process (the number of exposure shots) using the mask is 40 times. That is, according to the present invention, the TFT
The sequence of steps for forming the wiring pattern on the substrate is as follows. (1) Deposition of conductive film (Al film) for gate formation (2) Laminate deposition of negative type first photoresist film (3) Exposure of first photoresist film (corresponding to regions 2a to 2f) (6 division exposure) (4) Development of first photoresist film (5) Pattern formation of gate wiring 4 and gate electrode 4a (6) Adhesion of gate insulating film (SiN film: first insulating film) (7) ) Laminate deposition of positive type second photoresist film (8) Exposure of second photoresist film (6 times divided exposure by moving gate mask corresponding to regions 2a to 2f) (9) Contact hole 23 Form gate insulating film 11 with openings (10) Deposit amorphous silicon film (11) Deposit film (SiN film) for forming channel protective film (12) Deposit positive third photoresist film (13) Exposure of the third photoresist film (backside exposure using the gate wiring 4 and the gate electrode 4a as a mask) After the light exposure, the channel protective film mask is moved corresponding to the regions 2a to 2f and divided into six exposures. (14) Development of the third photoresist film (15) Pattern formation of the channel protective film 9 (16) Source / Drain forming conductive film (Al film) deposition (17) Negative-type fourth photoresist film stack deposition (18) Fourth photoresist film exposure (source / drain masks on regions 2a to 2f) (19) Developing the fourth photoresist film (20) Patterning the amorphous silicon layer 12, source / drain wiring 5, source electrode 5a and drain electrode 5b (21) Cover film (SiN film: second insulating film) deposition (22) Laminate deposition of positive type fifth photoresist film (23) Exposure of fifth photoresist film (contact hole masks in regions 2a to 2f) Move correspondingly and move 6 times separately) (24) Development of fifth photoresist film (25) Forming cover film 13 in which contact holes 25 and 25 are opened (26) Adhesion of transparent conductive film (ITO film) (24) Negative type sixth photoresist film Laminate deposition (25) Exposure of 6th photoresist film (19 times exposure using 5 kinds of terminal masks) (26) Development of 6th photoresist film (27) Pixel electrode 6, terminal 7 and terminal 8 And the connection line 7a and the connection line 8a are formed. However, the mask for forming the terminals 7 and 8 is a mask for partially penetrating into the display area and exposing the light. The contact holes 23 to 25 that are not connected to the connection lines 7a or 8a are formed in the films 11 and 13, that is, the connection holes 7 to 8 are formed in the contact holes 23 to 25 formed in the peripheral portions contacting the regions 2a to 2f.
a remains unconnected. In the embodiment of FIG. 2, a conductor pattern 26 communicating with a large number of terminals 7 and 8 is formed on the outer peripheral portion of the glass substrate 21, and the conductor pattern 26 is arranged so that the terminals 7 and 8 have the same potential. Prevents dielectric breakdown of the substrate 21 due to static electricity.

In the above embodiment, the TFT substrate in which the TFTs are arranged in a matrix for use in the liquid crystal display panel has been described. However, the present invention is not limited to the above-mentioned TFT substrate, and a plurality of first and second wirings are laminated and formed via an insulating layer, and the first and second wirings are formed.
It is apparent from the above embodiment that the present invention is applied to a wiring board in which lead-out terminals connected to each of the second wirings are formed, and the required number of exposure masks and man-hours are reduced as in the TFT substrate.

[0022]

As described above, when the present invention is applied to a TFT substrate for a liquid crystal display panel, in the prior art, 21 types of exposure masks and 70 exposure shots were required, but 9 types of exposure masks were used. It can be manufactured with a mask and 40 exposure shots. That is, the required number of exposure masks is 1/2
Below, the exposure shot is reduced to 4/7, the productivity is improved, and the defective rate accompanying the exposure process is reduced.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram of a schematic configuration of a TFT substrate which is an application example of the present invention.

FIG. 2 is an explanatory diagram of a main configuration of a TFT substrate which is an application example of the present invention.

FIG. 3 is an explanatory view of a CC cross section and a DD cross section in FIG. 2;

FIG. 4 is an explanatory diagram of a schematic configuration of a conventional TFT substrate for a liquid crystal display panel.

FIG. 5 is an explanatory diagram of a main configuration of a conventional TFT substrate for a liquid crystal display panel.

FIG. 6 is an explanatory diagram of an AA cross section and a BB cross section of FIG. 5;

[Explanation of symbols]

 4 gate wiring (first wiring) 4a gate electrode 5 source / drain wiring (second wiring) 5a source electrode 5b drain electrode 6 pixel electrode 7, 8 lead-out terminal 9 channel protective film 21 glass substrate 23, 24, 25 contact hole

Front page continued (72) Inventor Shiro Hirota 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor, Mitsuaki Sugine, Yonago, Yonago City, Tottori Prefecture 650 Otsuka Noji, Yonago Fujitsu Limited

Claims (4)

[Claims] 1. A plurality of first wirings, a first insulating layer covering the first wirings, a first lead terminal connected to the first wirings, and a first insulating layer. At least each of the plurality of second wirings on the upper side, the second insulating layer covering the second wirings, and the second lead terminals connected to the second wirings are formed by a lithography method of divided exposure. In the printed wiring board, the first lead terminal and the second lead terminal are the third
The first lead terminal and the first wiring formed of the first conductive film are connected to each other through a contact hole provided in the first insulating layer. Two
And the second wiring formed of the second conductive film are connected to each other through a contact hole provided in the second insulating layer. 2. The thin film transistor (T
FT) source / drain wiring or gate wiring, the second wiring is the other of the source / drain wiring or gate wiring, and the liquid crystal display panel pixel electrode connected to the TFT and the first lead wire. Terminal and the second
2. The wiring board according to claim 1, wherein the lead-out terminal is formed from the third conductive film made of a transparent conductive material by a divided exposure lithography method. 3. The first wiring is formed from the first conductive film deposited on the surface of the substrate by the lithography method of divided exposure using a negative resist, and the first wiring is deposited thereon. The first insulating layer having a first contact hole exposing the end of the first wiring was formed from the insulating film by a lithography method of divided exposure using a positive resist, and was deposited on the first insulating layer. The second conductive film is formed on the second conductive film by a lithography method of divided exposure using a negative resist.
Wiring is formed, and the second contact hole and the second contact hole for exposing the end portion of the second wiring from the second insulating film deposited on the second wiring by a lithography method of divided exposure using a positive resist. Third to expose the first contact hole
Forming the second insulating layer having the contact holes of the above, and using the third conductive film deposited on the second insulating layer, the first insulating film is formed by the lithography method of divided exposure using a positive resist.
Forming the lead-out terminal and the second lead-out terminal. 4. A liquid crystal display connected to the TFT, wherein the first wiring is one of a source drain wiring or a gate wiring of a TFT and the second wiring is the other of the source drain wiring or the gate wiring. A wiring board, characterized in that the panel pixel electrode, the first lead terminal, and the second lead terminal are formed from the third conductive film made of a transparent conductive material by a split exposure lithography method. Manufacturing method.