JPH089288A - Decoding circuit for discrimination control signal - Google Patents

Abstract

PURPOSE:To discriminate a signal discriminating the present television broadcasting system or new television broadcasting system called 'EDTV-II' at low cost and by reducing the circuitry and to easily produce the timing of taking in a decoding signal CONSTITUTION:The video signal supplied to the input terminal IN is demodulated by using an FM demodulation circuit 1. The demodulation output is supplied to a sample-and-hold circuit 2 and a comparison circuit 3. The output of the circuit 2 is supplied to an offset circuit 4 which generates the offset level from the output level of the sample-and-hold circuit 2. The output of the circuit 4 is supplied to the circuit 3. The circuit 3 compares the output level of the circuit 4 and the circuit 1. The result is outputted to the output OUT.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is intended to achieve wide aspect ratio, high image quality and high sound quality while maintaining compatibility between the current television broadcasting system and this system.
The present invention relates to a decoding circuit for an identification control signal for identifying which broadcasting system is being received among new television broadcasting systems called DTV-II system.

[0002]

2. Description of the Related Art Recently, as a next-generation terrestrial television broadcasting system, EDTV-I aimed at wide aspect, high image quality and high sound quality compatible with the current system.
A new broadcasting system called I system is about to be introduced.

In the EDTV-II system, identification information regarding various modes such as a difference in processing of transmitted video signals and information and sequences used as a reference such as phase and level in signal processing on the receiving side are controlled. For transmitting the control information used to
The identification control signal is inserted in the 285th horizontal video period.

FIG. 7 shows an example of the structure of the identification control signal. Here, the identification control signal in one horizontal video period is shown. First, it is located behind the color burst, and includes bit information according to two level states that are 40 IRE (1 V = 140 IRE) higher than the pedestal, and the first bit and the second bit are reference timing, and the third bit is a rater box (so-called aspect ratio). There is a first NRZ (non-return-to-zero) signal consisting of the presence or absence of a wide aspect ratio of 9:16 and the information of the first bit to the fifth bit whose fourth bit is parity information. Here, the length of 1 bit is 7 SC (cycle) of the frequency fsc (color subcarrier frequency), and the same applies to the following signals.

Next, following the first NRZ signal, the amplitude is ± 2.
A carrier of 0 IRE and a frequency of fsc, including bit information according to two phase states of in-phase and anti-phase with the color burst phase. The sixth bit is the field number, the seventh bit is the multiple phase, and the eighth bit is the vertical time reinforcement. Existence, 9th bit with or without vertical reinforcement, 10th bit with or without horizontal reinforcement, 11th
A bit is the presence or absence of horizontal reinforcement precombing, the 18th to 23rd bits include at least error correction code information, and the 6th
There is an fsc carrier signal consisting of bit to 23rd bit information.

Further following the fsc carrier signal is a second NRZ signal consisting of 24 bits of 1-bit information at the pedestal level, including bit information due to the pedestal and two level states 40IRE higher than it.

Since the above signals are inserted in the 22nd and 285th horizontal video periods of the video signal, which corresponds to the picture period in the current system, it is necessary to determine whether it is the existing video signal or the identification control signal. Therefore, the confirmation signal is inserted after the second NRZ signal. The confirmation signal has an amplitude of ± 1 due to the condition that the existing video signal cannot theoretically exist.
The carrier of 4/7 of the color subcarrier frequency is selected by 5IRE, and it is possible to distinguish from the existing video signal by the presence / absence of the amplitude, and 3 bits of the 25th to 27th bits are applied to this. .

The above signals are collectively referred to as an identification control signal. In a television receiver, it is necessary to decode and determine bit information from these signals and extract identification information and control information without misjudgment.

FIG. 8 shows a conventional discrimination circuit for discriminating an identification control signal. FIG. 8 includes four blocks of an NRZ signal decoding unit 10, an fsc carrier signal decoding unit 20, an fsc carrier signal determination unit 30, and a confirmation signal determination unit 40.

In the NRZ signal decoding unit 10, an LPF (low pass filter) 1 having a cutoff frequency of about 0.5 MHz is used.
The video signal that has passed 1 is subjected to threshold comparison by the threshold comparison circuit 12 to decode the NRZ signal. HPF (high-pass filter) with a cut-off frequency of about 0.5 MHz 13
The amplitude level of the high frequency component of the video signal extracted in step 2 is detected by the amplitude detection circuit 14 and the threshold value is compared by the threshold value comparison circuit 15. The result is N in the comprehensive judgment unit 50.
Used for determination of RZ decoded signal.

In the fsc carrier signal decoding unit 20, the fsc carrier signal is extracted from the video signal by the BPF (band pass filter) 21 having the center frequency fsc, and the output obtained by fsc demodulation by the fsc demodulation circuit 22 is sent to the threshold comparison circuit 23. Threshold comparison is performed and the fsc carrier signal is decoded.
The determination as to whether the decoded signal is a video signal or an identification control signal is determined by the determination results of the fsc carrier signal determination unit 30 and the confirmation signal determination unit 40. If either of the determination results is “identification control signal”, the comprehensive determination unit 50 determines that it is an identification control signal.

In the fsc carrier signal determining section 30, a BPF (center frequency fsc) 31 is used to calculate the fsc from the video signal.
Extract the carrier component. Further, the amplitude level of the fsc carrier component is detected by the amplitude detection circuit 32, and the amplitude level is compared by the threshold value comparison circuit 33. As a result, if the amplitude level is greater than or equal to the threshold value, it is “discrimination control signal” and below the threshold value, “not discrimination control signal”.
To determine. BSF of center frequency fsc from video signal
The amplitude level of the fsc carrier component extracted by the (band stop filter) 34 is detected by the amplitude detection circuit 35, and the amplitude level is compared by the threshold value comparison circuit 36. As a result, if the amplitude level is equal to or higher than the threshold value, it is determined to be "non-identification control signal" and equal to or lower than the threshold value, "identification control signal".

The two determination results obtained by the fsc carrier signal determination unit 30 are both "discrimination control signals".
In such a case, the comprehensive determination unit 50 outputs the decoded signal as an identification code.

In the confirmation signal determination section 40, B is detected from the video signal.
The confirmation signal component is extracted by the PF (center frequency 4 fsc / 7) 41. Further, the amplitude level of the confirmation signal component is detected by the amplitude detection circuit 42, and the amplitude level is compared by the threshold value comparison circuit 43. as a result,
If the amplitude level is equal to or higher than the threshold value, it is "identification control signal". If the amplitude level is equal to or lower than the threshold value, "not identification control signal" is determined.

On the other hand, from the video signal to the BSF (center frequency 4
The component other than the confirmation signal is extracted by fsc / 7) 44.
The amplitude level of the component other than the confirmation signal is detected by the amplitude detection circuit 45, and the amplitude level is compared by the threshold value comparison circuit 46. As a result, if the amplitude level is equal to or higher than the threshold value, it is determined to be "non-identification control signal" and equal to or lower than the threshold value, "identification control signal".

Further, a low frequency component is extracted from the video signal by an LPF (cutoff frequency of about 0.5 MHz) 47. The amplitude level of the low frequency component is detected by the amplitude detection circuit 48, and the amplitude level is compared by the threshold value comparison circuit 49. As a result, if the amplitude level is equal to or higher than the threshold value, it is determined to be "non-identification control signal" and equal to or lower than the threshold value, "identification control signal".

When all of the three determination results obtained by the confirmation signal determination section 40 are "identification control signals", the comprehensive determination section 50 outputs the decoded signal as an identification code. As described above, according to the configuration of FIG. 8, it is possible to decode the identification control signal with less misjudgment. However, the identification control signal decoding circuit of FIG. 8 requires a large number of filters and amplitude detection circuits, which increases the circuit scale and increases the cost. Moreover, the group delay of each filter is variable, and it becomes very difficult to generate a timing signal for capturing the decoded signal.

[0018]

As described above, the conventional identification control signal decoding circuit has a problem that the circuit scale is large and the cost is high, and it is very difficult to make the timing for capturing the decoded signal. It was This invention
It is intended to reduce the circuit scale of the identification signal discrimination unit to enable cost reduction and to facilitate generation of the timing of capturing the decoded signal.

[0019]

In order to solve the above-mentioned problems, the present invention focuses on the fact that the discrimination control signal is judged by confirming the presence of a signal component in a predetermined frequency range. The demodulation circuit demodulates, and the demodulation output is compared with the output of the FM demodulation circuit by comparing the output obtained by offsetting the reference output level with the output level when the color burst signal is input. is there.

[0020]

In the discrimination control signal decoding circuit configured as described above, the relative offset level with respect to the level of the FM demodulation circuit when the color burst signal is input is compared with the output level of the FM demodulation circuit. Know where the frequencies are. Therefore, the presence / absence of the frequency component in the predetermined frequency range can be determined. By using the determination result of the presence or absence of a predetermined frequency component for the determination of the identification control signal, a circuit such as a filter becomes unnecessary, the circuit scale can be reduced and the cost can be reduced, and the filter becomes unnecessary, so that the group delay This eliminates the problem and facilitates the generation of the timing for fetching the decoded signal.

[0021]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 shows a circuit configuration diagram for explaining the principle of the present invention. 1 shows the input terminal IN
The video signal supplied to is demodulated using the FM demodulation circuit 1, and the demodulated output is supplied to the sample hold circuit 2 and the comparison circuit 3. The output of the sample hold circuit 2 is supplied to an offset circuit 4 that generates a level offset from the output level of the sample hold circuit 2. The output of the offset circuit 4 is supplied to the comparison circuit 3. The comparison circuit 3 compares the output levels of the offset circuit 4 and the FM demodulation circuit 1 and outputs the result to the output OUT.

In such a configuration, when the sample-hold circuit 2 is sample-held during the color burst period of the video signal, the output of the sample-hold circuit 2 corresponds to the output level of the FM demodulation circuit when the input frequency is fsc. You can always get levels.

Since the output of the FM demodulation circuit 1 generally has a substantially linear frequency-demodulation output characteristic, as shown in FIG. 2, the output level relative to the FM demodulation output at the input frequency fsc is offset circuit 4. By setting with, it is possible to detect whether the frequency of the video signal is higher or lower than a certain frequency. In particular, in the FM demodulation circuit 1, V-like a multivibrator whose frequency vs. demodulation output characteristic passes through the origin.
When a CO (voltage controlled oscillator) is used, it is possible to detect the frequency of the video signal with high accuracy based only on the relative relationship.

By utilizing this detection result for the determination of the identification control signal, the filter or the like which has been conventionally required is not required, and the circuit scale can be greatly reduced. Further, since the filter is eliminated, the group delay that has been generated by the conventional filter is also eliminated, so that the timing signal for capturing the decoded signal can be easily generated.

FIG. 3 is a circuit configuration diagram for explaining one embodiment of the present invention, which is applied to the confirmation signal determination section 40 of FIG. An output obtained by FM demodulating the video signal by the FM demodulation circuit 1 is supplied to the sample hold circuit 2, the comparison circuit 3a and the comparison circuit 3b. The output of the sample hold circuit 2 is supplied to the offset circuit 4a and the offset circuit 4b. The outputs of the offset circuit 4a and the offset circuit 4b are supplied to the comparison circuits 3a and 3b, respectively.

In the comparison circuits 3a and 3b, the output levels from the offset circuits 4a and 4b and the FM demodulation circuit 1 respectively.
The output levels of are compared and output. The outputs of the comparison circuits 3a and 3b are logically combined by AND gates 5a and 5b. The output of AND5a is high level when the frequency component of the video signal is within a predetermined frequency range, and AN
The output of D5b becomes high level when the frequency component of the video signal is not within the predetermined frequency range. The outputs of the AND gates 5a and 5b are LPFs, respectively.
47, an amplitude detection circuit 48, and a threshold value comparison circuit 49 together with the output of the low-frequency component detection section, and the comprehensive determination circuit
0, where a comprehensive decision is made.

The sample and hold circuit 2 is similar to that shown in FIG.
The sample hold operation is performed during the color burst period. Then, the output of the sample hold circuit 2 always obtains the FM demodulation output level when the fsc frequency is input, that is, the reference level. Therefore, as shown in FIG. 4, the offset circuit 4a and the offset circuit 4b are set so that the output level is close to the output level of the FM demodulation circuit 1 when the 4fsc / 7 frequency is input.
The offset amounts are set to a and b, respectively. The outputs of the comparison circuits 3a and 3b are connected to AND gates 5a, 5
If logically synthesized with b, the frequency of the video signal is 4 fsc / 7.
It is possible to judge whether or not it is in the range of the neighborhood. The low-frequency component detecting section including the LPF 47, the amplitude detecting circuit 48, and the threshold comparing circuit 49 is the same as that described with reference to FIG. By these, the confirmation signal can be discriminated.

FIG. 5 shows the offset circuits 4a and 4b of FIG.
It is a concrete circuit diagram of. The output of the sample hold circuit 2 and the voltage source Vb are connected by a series connection of resistors R1 to R3. The different offset amounts a and b depend on the voltage source V
By setting the voltage of b to the output level of the FM demodulation circuit 1 at the time of zero frequency input, the output voltage of the offset circuits 4a and 4b corresponding to an arbitrary frequency can be appropriately set by the resistance ratio of the resistors R1 to R3. Can be easily obtained.

Of course, in the FM demodulation circuit, the frequency vs. demodulation output characteristic passes through the origin, for example, V as in a multivibrator.
When CO is used, the voltage source Vb is unnecessary. For example,
Assuming that the resistance values of the resistors R1 to R3 are R1, R2, and R3, when the voltage corresponding to 4fsc / 7 is desired to be the output of the offset circuit 4, (R2 + R3) / (R1 + R2 + R3) = (4fsc /
The ratio of the resistance values of the resistors R1, R2 and R3 may be determined so that 7) / fsc = 4/7.

FIG. 6 is a circuit configuration diagram for explaining another embodiment of the present invention. In FIG. 6, the video signal supplied to the input terminal IN is demodulated using the FM demodulation circuit 1,
The demodulated output is used as a comparison circuit 3 and an output level adjusting circuit 6.
1 to one input. Output level adjustment circuit 6
A reference voltage source Vref is connected to the other input of 1. The reference voltage source Vref is further supplied to the offset circuit 4. The output of the offset circuit 4 is supplied to the comparison circuit 3, and the comparison output is led to the output terminal OUT.

That is, in this embodiment, the reference voltage source Vref is used as the means for generating the reference output voltage instead of the sample hold circuit 2 of FIG. 1, and the output voltage of the FM demodulation circuit 1 is input when the color burst signal is input. The output level adjusting circuit 61 is provided to match the voltage Vref of Vref. The specific operation of the output level adjusting circuit 61 is nothing but adjusting the frequency vs. demodulation output characteristic of the FM demodulating circuit 1 shown in FIG.

The present invention is not limited to the above-mentioned embodiment, but various modified applications are possible. For example, the offset circuit and the comparison circuit of FIG. 3 may be further increased and applied to the other parts of FIG. Further, as the reference frequency input signal, a confirmation signal composed of, for example, 4 fsc / 7 carrier waves may be used instead of the color burst. An arbitrary offset voltage can be generated by increasing the resistance in FIG.

[0033]

As described above, according to the discrimination control signal decoding circuit of the present invention, not only is the circuit scale of the discrimination signal discrimination section reduced to enable cost reduction, but also the timing of fetching the decoded signal is improved. It can be easily generated.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram for explaining the principle of an identification control signal decoding circuit of the present invention.

FIG. 2 is a characteristic diagram of frequency vs. demodulation output of the FM demodulation circuit used in FIG.

FIG. 3 is a circuit configuration diagram for explaining an embodiment of the present invention.

4 is a characteristic diagram of frequency vs. demodulation output for explaining the operation of FIG.

FIG. 5 is a specific circuit diagram of an offset circuit used in the present invention.

FIG. 6 is a circuit configuration diagram for explaining another embodiment of the present invention.

FIG. 7 is an explanatory diagram illustrating a configuration of an identification control signal in one horizontal video period.

FIG. 8 is a circuit configuration diagram for explaining a conventional identification control signal decoding circuit.

[Explanation of symbols]

1 ... FM demodulation circuit, 2 ... Sample and hold circuit, 3, 3
a, 3b ... Comparison circuit, 4, 4a, 4b ... Offset circuit, 5a, 5b ... AND gate, 61 ... Output level adjusting circuit, Vref ... Reference voltage source.

Claims (4)

[Claims] 1. A first color subcarrier signal provided with color reference information and a first color subcarrier signal inserted at different positions during at least one horizontal video period of a television signal,
Controls the identification function information used to identify the difference in the type, combination, and processing of transmitted video and augmented signals, as well as the functions and sequences used as references for phase and level in signal processing on the receiver side. NRZ signal provided with control function information used to do so and the first color subcarrier signal and the NRZ signal inserted at different positions and different in type, combination, and processing of video / augmentation signals transmitted. The second function is provided with identification function information used for identifying a signal and control function information used for controlling a function or sequence used as a reference such as phase and level in signal processing on the receiver side. Seed of a video / augmentation signal that is inserted and transmitted at positions different from the color subcarrier signal, the first color subcarrier signal, the NRZ signal, and the second color carrier signal. -Identification function information used to identify differences in combinations and processing, and control function information used to control functions and sequences used as a reference for phase and level in signal processing on the receiver side A video signal processing circuit for processing a video signal having a confirmation carrier signal having a predetermined frequency and amplitude, comprising: an FM demodulation circuit for FM demodulating the video signal; A reference level generating means for generating an output level of the FM demodulation circuit, an offset circuit for giving an offset to the output of the reference level generating means, and a comparison circuit for comparing the output of the offset circuit with the output of the FM demodulation circuit. An identification control signal decoding circuit comprising: 2. The identification control signal decoding circuit according to claim 1, wherein the reference level generating means comprises a sample hold circuit which performs a sampling operation within a color burst signal input period and a holding operation during another period. 3. The reference level generating means includes a reference voltage source,
It comprises an adjusting circuit for controlling the demodulation characteristics of the FM demodulation circuit so that the output levels of the reference voltage source and the FM demodulation circuit match within the color burst signal input period, and the output of the reference voltage source is taken as the output of the reference level generating means. The identification control signal decoding circuit according to claim 1, wherein: 4. The offset circuit comprises a plurality of resistors connected in series between the output of the reference level generating means and the voltage source, and outputs a voltage offset from the connection point between the resistors. The identification control signal decoding circuit according to claim 1.