JPH08307839A - Decoder for identification signal - Google Patents

Abstract

PURPOSE: To provide the decoder for an identification signal decoding easily identification information from the identification signal of EDTV2. CONSTITUTION: Identification information included in an identification signal is extracted via a trap circuit 4 by a switch SW 1 controlled by a timing control signal of a prescribed period from the identification signal superimposed on a prescribed horizontal line position for a vertical blanking period. Furthermore, a confirmation signal included in the identification signal is extracted via a band pass filter 5 and a data detection section 10 samples the identification information and the confirmation signal to discriminate the identification signal and extracts the identification information from the identification signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an identification signal decoding apparatus for decoding identification information from an identification signal superimposed in a vertical blanking period of a video signal.

[0002]

2. Description of the Related Art Current television systems (NTSC, P
EDTV (Extended Definition Televisio) that achieves high quality while maintaining compatibility with AL, SECAM, etc.
Various types of n) have been developed, and the latest EDT
Some Vs (second generation EDTVs (hereinafter, referred to as “EDTV2”)) have an aspect ratio of 16: 9 and 525 scanning lines. When the video signal of the EDTV 2 is received by an existing television receiver (aspect ratio 4: 3), a so-called letter box screen with black bands at the top and bottom of the screen is displayed.

The identification signal of the EDTV 2 is transmitted by utilizing horizontal lines in the vertical blanking period of the video signal. Among these identification signals, for example, the horizontal line positions on which aspect information is superposed are 22 lines and 285. It is said to be a line.

The contents of the identification signal of the EDTV 2 as described above,
And an example of the status is shown in FIG. 8, and each bit position when the signal is converted into the video signal is shown in FIG. 3 described later. As shown in this figure, the EDTV2 identification signal is 27
The first bit (B1) and the second bit (B2) are reference timing signals, and the third bit to
The 17th bit (B3 to B17) is an identification code. On the other hand, the 18th to 23rd bits (B18
6 bits up to B23) are error corrections (hereinafter, "CRC" (Cyclic) for detecting a bit error or correcting a code.
Redundancy Check)) code.

The fifth bit (B5) and the twelfth bit to the seventeenth bit (B12 to B17) are undefined bits "0", and the twenty-fifth bit to the twenty-seventh bit (B).
25-B27), in order to prevent erroneous detection with a video signal,
It is a sine wave signal for confirmation that indicates that the identification signal is superimposed on the horizontal line. The frequency of this sine wave signal is
It is 4/7 f _SC (f _SC is a color subcarrier signal, and the frequency is 3.579545 MHz in the NTSC system).

Further, the waveforms of the 1st bit to the 5th bit (B1 to B5) and the 24th bit (B24) surrounded by the chain line are non-return zero (hereinafter referred to as "NRZ" (Non Return t).
o Zero)).

FIG. 9 shows an example of a decoding device recommended for decoding the identification signal of the EDTV 2.
The identification signal decoding device, which is not shown, specifies a predetermined horizontal line position in the vertical blanking period in which the identification signal is superimposed and a bit position of the identification signal. with the signal is input, demodulation of the color sub-carrier signal f _SC, and for detecting the sampling timing, it is assumed that the color subcarrier signal f _SC is input.

In this figure, the identification signal of the EDTV 2 extracted from a predetermined horizontal line position in the vertical blanking period by a pre-stage circuit (not shown) is input to the terminal 40, and the identification signal is supplied to the identification signal decoding unit 50 and It is input to the video signal determination unit 70. The identification signal input to the identification signal decoding unit 50 is further input to the NRZ signal decoding unit 51 and the carrier signal decoding unit 52. The identification signal supplied to the video signal determination unit 70 is further input to the confirmation signal determination unit 71 and the carrier signal determination unit 72.

The identification signal input to the NRZ signal decoding unit 51 is a low pass filter 61 and a high pass filter 62.
Respectively. The signal D ₁ of the low frequency component (up to 0.5 MHz) output from the low pass filter 61 is used as the data signal of the NRZ waveform signal (B1 to B5). As shown in the figure, this data signal is compared with a predetermined slice level A in a threshold circuit 63, converted into a digital signal and supplied to the shift register 53.

Signals of high frequency components (0.5 MHz to) other than the data signal output from the high pass filter 62 are input to the threshold circuit 65 via the absolute value conversion / smoothing circuit 64. Then, it is converted into a digital signal by the threshold circuit 65,
The inverted output is input to the determination circuit 55.

The identification signal input to the carrier signal decoding unit 52 is input to the bandpass filter 66, and the signal of the color subcarrier band component (f _{S C} ) which is the output of the bandpass filter 66 is demodulated by the demodulation circuit 67. At the color burst phase. This demodulated signal D ₂ is compared with a predetermined slice level B in a threshold circuit 68 as shown in the figure, converted into a digital signal, and its inverted output is supplied to a shift register 53. Then, the shift register 53 temporarily stores the data signal of the NRZ waveform at the timing cycle of the carrier signal demodulated by the carrier signal decoding unit 52, and then the data signal is passed through the error correction circuit 54 to the determination circuit 55.
Is supplied to.

On the other hand, the identification signal input to the confirmation signal determination unit 71 of the video signal determination unit 70 is a bandpass filter (B
PF) 81, band removal filter (BEF) 82, and low pass filter (LPF) 83.

The bandpass filter 81 receives the confirmation signal (25
The signal of the frequency band component (4 / 7f _SC ) of (bit to 27 bits) is passed and supplied to the threshold circuit 85 via the absolute value conversion / smoothing circuit 84. Then, when the confirmation signal reaches the predetermined amplitude level in the threshold circuit 85, the detection signal is supplied to the AND circuit 90. The band elimination filter 82 allows signals other than the band component (4 / 7f _SC ) of the confirmation signal to pass therethrough, and the threshold value circuit 87 is passed through the absolute value conversion / smoothing circuit 86.
Is being supplied to. Then, when the confirmation signal is detected to be equal to or lower than the predetermined amplitude level, the detection signal is supplied to the AND circuit 90.

Further, the low-pass filter 83 passes a signal of a low frequency component (up to 0.5 MHz), which is a data signal,
It is supplied to the threshold circuit 89 via the absolute value conversion / smoothing circuit 88. Then, when the threshold circuit 89 detects that the amplitude level of the data signal is equal to or lower than a predetermined value, the AND circuit 90 is supplied with a detection signal.

In other words, when the AND circuit 90 detects the signal of the band component (4 / 7f _SC ) of the confirmation signal and the signals other than the band component of the confirmation signal and the data signal are not detected, they are distinguished from the confirmation signal. The signal is discriminated as a signal and the discrimination result is output to the OR circuit 73.

The identification signal input to the carrier signal determination unit 72 is input to the bandpass filter 91 and the band removal filter 92, and the signal of the color subcarrier band component (f _SC ) which is the output of the bandpass filter 91. Is an absolute value
It is supplied to the threshold circuit 94 via the smoothing circuit 93. Then, when the color subcarrier signal has a predetermined amplitude or more in the threshold circuit 94, a detection signal is supplied to the AND circuit 95.

Signals other than the carrier band component output from the band elimination filter 92 are made into an absolute value / smoothing circuit 9.
6 is supplied to the threshold circuit 97. Then, when the threshold circuit 97 detects that the color subcarrier signal has a predetermined amplitude or less, the detection signal is supplied to the AND circuit 95 and the determination circuit 55.

The AND circuit 95 determines that it is a carrier signal when the input signal of the color subcarrier band component has a predetermined amplitude or more and the signals other than the color subcarrier band component have a predetermined amplitude or less. The determination result is output to the OR circuit 73. When the detection signal is input from the confirmation signal determination unit 71 or the carrier wave signal determination unit 72, the OR circuit 73 outputs the determination result that it is the identification signal to the determination circuit 55.

That is, the determination circuit 55 determines the identification signal from the high frequency component signal supplied from the NRZ signal decoding unit 51 and the low frequency component data signal, and the confirmation signal and the carrier signal of the video signal determination unit 70. It is determined whether the signal extracted from the predetermined horizontal line position is the identification signal of the EDTV 2 from the determination result of. Then, when it is discriminated as an identification signal, a television device or the like equipped with a decoding device for the identification signal performs processing according to the information of the identification signal.

[0020]

By the way, as described above, in the conventional identification signal decoding apparatus, in order to determine the identification signal, the determination circuit for determining the decoding circuit and the confirmation signal for decoding the NRZ waveform signal of the identification signal is determined. It is necessary to provide a circuit, a decoding circuit for decoding the carrier wave signal, and a determination circuit, which causes a problem that the circuit configuration is complicated, the circuit scale is increased, and the cost is increased.

The present invention has been made in view of the above problems, and an object thereof is to provide a decoding device for an identification signal which can easily identify the identification signal of the EDTV 2 and has high reliability. To do.

[0022]

To achieve the above object, the identification information modulated by a predetermined modulation method and the identification information of a predetermined frequency are superimposed on a predetermined horizontal line position in a vertical blanking period in which a confirmation signal is formed. In an identification signal decoding device for decoding an identification signal, a signal generation means for generating a plurality of timing control signals and sampling clock signals of a predetermined cycle from a vertical synchronization signal and a horizontal synchronization signal, and a band of identification information from the identification signal Trap means for removing noise of the component, filter means for extracting the band component of the confirmation signal from the identification signal, first switching means which is switch-controlled in conjunction with a timing control signal of a predetermined cycle, and first Clamping means for clamping the identification signal input through the switching means and the identification information from the output signal of the clamping means. And a second switching means for extracting the confirmation signal, a data detecting means for sampling the identification information and the confirmation signal extracted based on the sampling clock signal, and a predetermined signal based on the sampling signal detected by the data detecting means. It is configured to include a control unit that determines whether or not the signal is an identification signal and, when it is determined that the signal is an identification signal, decodes the identification content of the identification information.

[0023]

According to the present invention, the identification information of the identification signal and the noise of the band component of the confirmation signal are removed, and only the identification information and the confirmation signal are respectively extracted from the identification signal, and sampling is performed to determine the identification signal. Therefore, it is possible to realize a highly reliable identification signal decoding device with a simple circuit configuration.

[0024]

Embodiments of the identification signal decoding apparatus of the present invention will be described below. FIG. 1 shows an example of the overall configuration when the identification signal decoding apparatus of the present embodiment is installed in a television receiver. The composite is received by an antenna 20, tuned by a tuner 21, and extracted as an intermediate frequency signal. The video signal or the composite video signal input from the line input terminal 22 is supplied to the video signal processing circuit 24 via the input switching unit 23.

In the video signal processing circuit 24, after Y / C separation, luminance signal processing, color difference signal processing, etc. are executed, R, G,
The signal is decoded into a B signal, supplied to a cathode ray tube (hereinafter referred to as “CRT”) 25, and output as an image. Further, the video signal processing circuit 24 extracts the horizontal synchronizing signal and the vertical synchronizing signal to generate a deflection current, and supplies the deflection current to the deflection coil 26. The microcomputer 27 controls the operation of each part of the television receiver.

The identification signal decoding apparatus 1 according to the present embodiment is
The identification signal superimposed on a predetermined horizontal line position in the vertical blanking period is extracted, and various information transmitted by the identification signal is supplied to the microcomputer 27 which controls the main body of the television receiver, and the microcomputer 27
Controls the television receiver according to this information.

An example of a block diagram of such an identification signal decoding apparatus 1 is shown in FIG. In the present embodiment, a case will be described in which the identification signal of the horizontal line (22 lines or 285 lines) on which the aspect information is superimposed is decoded.

In this figure, a terminal 2 receives a composite video signal such as a television receiver or VTR (not shown) or a cable television signal. The low-pass filter 3 removes unnecessary high-frequency components contained in the identification signal, and the trap circuit 4 decodes the non-return-zero (hereinafter referred to as NRZ) waveform signal of the identification signal to reduce the influence of the ghost due to the burst signal. It is provided for removal. The band pass filter 5 is provided to remove interference due to a weak electric field, a ghost, a video signal, or the like when decoding the confirmation waveform signal (4/7 f _C ) of the identification signal.

The sync separation circuit 6 separates the vertical sync signal V _S and the horizontal sync signal H _S from the identification signal from which unnecessary high frequency components have been removed by the low pass filter 3. The timing control circuit 7 is controlled by the microcomputer 12 and has a timing control signal S ₁ of a predetermined timing cycle.
~ S ₄ is generated, and the clock generation circuit 8 outputs the horizontal synchronization signal H.
_S, and based on the timing control signals S ₁ and generates a sampling clock CLK having a predetermined period. The switch SW1 and the switch SW2 are the timing control circuit 7
Is controlled by the timing control signal S ₂ at predetermined timing.

The pedestal clamp circuit 9 uses the clamp voltage V _CL and the timing control signal S ₂ to determine the identification signal input via the switch SW1 to the data detector 10.
For example, the pedestal level of the signal is clamped so that it can be sliced accurately.

The switch SW3 is a timing control signal S ₄
The switching control is performed by the contact control circuit, and the pedestal clamp circuit 9 supplies the data signal in the predetermined section of the identification signal to the data detection unit 10 while being connected to the contact a only for a predetermined period, and is connected to the contact b for the other period. The masking voltage V _m is supplied to the data detector 10.

The data detector 10 includes a comparator 10a,
And a D flip-flop circuit 10b, and the comparator 10a outputs a signal in a predetermined bit section input via the switch SW3, for example, a data signal (B1 to B5) having an NRZ waveform or a sine wave signal (B25 for confirmation).
~ B27) is compared with a predetermined slice potential V _S1 or slice potential V _S2 , converted into a digital signal, and supplied to the D flip-flop circuit 10b. The D flip-flop circuit 10b samples the digital signal with the sampling clock CLK generated by the clock generation circuit 8.

The shift register 11 temporarily stores the input sampling data and then outputs it to the microcomputer 12. The microcomputer 12 determines from the input sampling data whether or not it is the identification signal of the EDTV 2, and if it is determined that it is the identification signal, it extracts the bit data of, for example, aspect information of the identification signal, and the television shown in FIG. The signal is output to the microcomputer 27 of the main body of the television receiver, and as a result, the aspect ratio of the television receiver is controlled.

When the identification signal decoding device 1 is mounted on a television receiver or the like as shown in this embodiment, for example, the microcomputer 12 of the identification signal decoding device 1 is used.
The microcomputer 2 of the main body of the television receiver
6 may be added.

Next, the decoding operation of the above-mentioned identification signal decoding apparatus 1 will be described with reference to the waveforms of the respective portions of FIGS. The identification signal of Ass Bae transfected information superimposed on e.g. the vertical blanking period of the composite video signal inputted from the input terminal 2 is a Fomatto as shown in FIG. 3 (a), the horizontal sync signal H _S , A color burst signal CB, an identification data signal (1 bit to 5 bits) of an NRZ waveform, and then a data signal (6 bits to 2 bits).
3 bits), and then a sine wave signal (25 bits to 27 bits) for confirmation.

Firstly, when decoding the identification data signal NRZ waveforms from the identification signal (1 bit 5 bit), the timing control circuit 7 will be described later predetermined cycle of the timing control signal S ₃ by the switch SW1 and the switch SW from
2 is connected to the contact a, and is connected to 3.5 via the trap circuit 4.
The identification signal from which the influence of the 8 MHz burst signal (CB) is removed is input to the pedestal clamp circuit 9, and the slice potential V _S1 is input as the reference voltage of the comparator 10 a of the data detection unit 10.

The identification signal input via the switch SW1 is clamped by the pedestal clamp circuit 9 to a predetermined clamp voltage V _CL and supplied to the data detection section 10 via the switch SW3. In this case, the switch SW3 is 3 in (b) only during the period T ₁ to indicate so, contact from the timing control circuit 7 a timing control signal S ₄ is applied a
The identification signal supplied to the comparator 10a of the data detector 10 is only the identification data signal of the NRZ waveform. In addition, the switch SW3 is connected to the contact b during the other period, and the masking voltage V _m is supplied to the data detection unit 10.

The identification data signal supplied to the data detector 10 is sampled by the flip-flop circuit 10b, and an example of the sampling method is shown in FIG. As shown in this figure (a), the identification data signal of the NRZ waveform is the predetermined sampling clock CLK (frequency is, for example, 4.08 MHz (8f _SC / 8f _SC /
In 7)), 8 points (1 byte) are sampled per bit.

Further, as shown in FIG. 3B, 1 bit is used to prevent erroneous detection of the identification data signal having the NRZ waveform due to a ghost, a repeater or the like shifting in the time axis direction or a sampling start point shifting. Of the per-sampling data (8 points), only the central sampling data is validated and the sampling data is output to the shift register 11.

On the other hand, when decoding the sine wave signal for confirmation (25 bits to 27 bits) from the identification signal, the timing control circuit 7 connects the switch SW1 and the switch SW2 to the contact b by the timing control signal S ₃ . An identification signal from which a weak electric field, ghost, or interference due to a video signal has been removed is input to the pedestal clamp circuit 9 via the bandpass filter 5, and the slice potential V _S2
Is input as the reference voltage of the comparator 10a of the data detection unit 10.

In this case, the switch SW3 is adapted to be applied with the timing control signal S ₄ from the timing control circuit 7 and connected to the contact a only during the period T ₂ as shown in FIG. 3C. The identification signal supplied to the comparator 10a of the data detector 10 is only the sine wave signal for confirmation. In addition, the switch SW3 is in the contact b during the other period.
The masking voltage V _m is supplied to the data detection unit 10 by being connected to.

FIG. 5 shows an example of a sampling method of the sine wave signal for confirmation performed in the data detection section 10. In this case also, a predetermined sampling clock CLK (generated by the clock generation circuit 8 For example, the frequency is 4.08MHz (8f _SC /
7)) is used for sampling. Further, the sampling clock CLK is retriggered at the rising edge in order to enable detection by the 1-bit comparator.

That is, in order to prevent malfunction due to noise near the pedestal potential, the slice potential V _S2 is applied to provide an offset voltage, and the rising edge of the sampling signal is delayed by Td from the edge for confirmation. If the sine wave signal of 10101 exists, the inversion bit string of 10101 ... Is surely obtained as the sampling data.

Therefore, the number of sampling points obtained from 1 bit of the 1-bit confirmation sine wave signal is 8
This is the point, and a 24-bit sampling inversion data string is obtained from the 3-bit confirmation sine wave signal of 25 bits to 27 bits and is supplied to the shift register 11.

The sampling data obtained from the NRZ waveform signal thus supplied to the shift register 11 and the sine wave signal for confirmation are once accumulated and then supplied to the microcomputer 12 to be discriminated from these sampling data. Whether or not it is a signal is determined. For example, in the array of 24-bit sampling data originally obtained from the sine wave signal for confirmation, if 70% or more are alternately inverted, it is determined to be the confirmation sine wave signal, and it is determined to be the confirmation signal. In this case, for example, bit data (third bit) indicating aspect information is extracted to control the aspect ratio of the television receiver, for example.

By the way, in the signal processing sequence of the identification signal decoding apparatus 1, for example, as shown in FIG. 6, the NRZ waveform signal of the identification signal is sampled every two fields and the sine wave signal for confirmation of the identification signal is sampled every two fields. A 4-field sequence is used, and the fields for extracting the NRZ waveform signal and the sine wave signal for confirmation are alternately inverted for each frame. Therefore, the switching of the switches SW1 and SW2 controlled in conjunction with each other is performed once in one frame.
The switching of the timing cycle of the switch SW3 only needs to be performed once in two fields, and control can be easily performed.

FIG. 7 shows a flowchart of the signal processing of such a 4-field sequence. Note that this signal processing is for extracting aspect information. When the identification signal decoding device 1 detects the vertical synchronizing signal V after being initialized, it detects an NRZ waveform signal from a horizontal line position (for example, 22 lines on which aspect information is superimposed) in a predetermined vertical blanking period. Control to do.
(F100, F101, F102) Then, when the vertical synchronizing signal V is detected again, control is performed so as to detect the NRZ waveform signal from a predetermined horizontal line position (285 lines). (F103, F104)

Next, when the vertical synchronizing signal V is detected, control is performed so as to detect a sine wave signal for confirmation from a predetermined horizontal line position (22 lines). (F105, F106) Then, when the vertical synchronizing signal V is detected again, control is performed so as to detect a sine wave signal for confirmation from the horizontal line position (285 lines). (F107, F108)

The NRZ waveform signal thus detected and the sine wave signal for confirmation are discriminated at step 109 to see if they are identification signals of the EDTV2.
If it is determined that the status signal is in the letterbox (third bit) status, and if there is bit data, the result of the aspect ratio determination that the screen aspect ratio is 16: 9 is output. . (F110, F111, F112) On the other hand, if there is no bit data in the letterbox in step 110, the aspect determination result that the aspect ratio of the screen remains 4: 3 is output. (F110, F
113, F112)

In the identification signal decoding apparatus of this embodiment, a case has been described where the identification signal of aspect information is used, but the present invention is not limited to this, and identification information superimposed on another horizontal line can be extracted. You can also Further, in the present embodiment, in order to determine whether or not it is the identification signal of the EDTV 2, the NRZ waveform signal (1st bit to 5th bit) and the sine wave signal for confirmation (25th bit to 27th bit).
However, the discrimination signal may be discriminated by detecting the bit data of the 6th to 23rd bits, for example.

Further, the detection of the NRZ signal and the detection of the confirmation signal do not necessarily have to be performed in the same field, but may be detected in a time division manner across different fields. Furthermore, the sampling clock is 2.04MHz 2
It is also possible to detect with a double clock signal.

[0052]

As described above, the identification signal decoding apparatus of the present invention removes the identification information of the identification signal or the noise of the band component of the confirmation signal, and extracts only the identification information or the confirmation signal by the switching means. Since the sampling is performed by using the conventional identification signal decoding device, it is not necessary to provide a carrier wave signal decoding circuit and a determination circuit as compared with the conventional identification signal decoding device, and a simple circuit configuration can be realized at low cost. Further, since the identification information of the identification signal and the noise component of the confirmation signal are removed, high reliability can be maintained even against interference such as a weak electric field or a ghost.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an apparatus in which an identification signal decoding device according to an embodiment of the present invention is mounted.

FIG. 2 is a block diagram of an identification signal decoding apparatus that is an embodiment of the present invention.

FIG. 3 is a timing chart of a format of an identification signal superimposed on a vertical blanking period and a switch SW3.

FIG. 4 is a diagram showing an example of a method of sampling identification information according to the embodiment.

FIG. 5 is a diagram showing an example of a confirmation signal sampling method according to an embodiment.

FIG. 6 is a diagram showing an example of a signal processing sequence of the embodiment.

FIG. 7 is a diagram showing a flowchart of signal processing by the microcomputer of the embodiment.

FIG. 8 is a diagram showing an example of the content and status of an identification signal.

FIG. 9 is a diagram showing an example of a conventional identification signal demodulation circuit.

[Explanation of symbols]

 1 Identification Signal Decoding Device 2 Terminal 3 Low Pass Filter 4 Trap Circuit 5 Band Pass Filter 6 Sync Separation Circuit 7 Timing Control Circuit 8 Clock Generation Circuit 9 Pedestal Clamp Circuit 10 Data Detection Section 10a Comparator 10b D Flip-Flop Circuit 11 Shift Register 12 Micro Computer

Claims (3)

[Claims] 1. Decoding of an identification signal which is decoded by a predetermined modulation method and an identification signal which is superimposed on a predetermined horizontal line position in a vertical blanking period in which a confirmation signal of a predetermined frequency is formed. In the device, signal generating means for generating a plurality of timing control signals and sampling clock signals of a predetermined cycle from the vertical synchronizing signal and the horizontal synchronizing signal, and trap means for removing noise of the band component of the identification information from the identification signal, Filter means for extracting the band component of the confirmation signal from the identification signal, first switching means which is switch-controlled in conjunction with the timing control signal of the predetermined cycle, and input through the first switching means. Clamping means for clamping the identification signal, and identification information and confirmation signal from the output signal of the clamping means. Second switching means for extracting, data detecting means for sampling the identification information and confirmation signal extracted based on the sampling clock signal, and a predetermined identification signal based on the sampling signal detected by the data detecting means An identification signal decoding apparatus, comprising: a control unit that determines whether or not the identification signal is present, and decodes the identification content of the identification information when determined as an identification signal. 2. The decoding device for an identification signal according to claim 1, wherein the sampling clock signal has a frequency that is at least twice as high as the frequency of the confirmation signal included in the identification signal. 3. The identification signal decoding apparatus according to claim 1, wherein the first switching means performs switching control at least once within one frame period.