JPH086849A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To lower the price of the collector, reduce the size, and improve the package density, to shorten the transmission distance of various internal signals and reducing skew, and to speed up the operation by equipping a memory module card with a memory control integrated circuit. CONSTITUTION:The memory control integrated circuit 113 is mounted on the memory module card 110. Signals repeated and transmitted by connectors 120 and 220 are only an address signal AD, a control signal CNT, a bank specification signal BD, and write data DB from a host system circuit 210, and read data to the host system circuit 210. The collectors 120 and 220 are therefore reducible in cost and reduced in size, so the package density can be increased. Further, the distances between the memory control integrated circuit 113, and respective RAM chips MC11-MCIm, and MC21-MC2n are shortened to make the signal line lengths of signals between them short, enabling fast operation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a semiconductor memory device including a single in-line memory module and used in a data processing system or the like.

[0002]

2. Description of the Related Art A data processing system such as a personal computer is equipped with a semiconductor memory device including a memory module having a plurality of RAM chips each having a predetermined memory capacity. As a form of this memory module, a connector is installed at a predetermined position of a memory module card in which a plurality of RAM chips are installed, and a single module is attached to a connector provided in a mother card of a host system such as a data processing system. In-line memory module (SIMM) type is often adopted.

An example of a conventional semiconductor memory device of this type is shown in FIG.

This semiconductor memory device includes a plurality of arranged memory cells and an internal address signal AD1, transmitted.
According to the internal control signal CNT1, a predetermined memory cell is selected from the plurality of memory cells, the stored data is read from the memory cell, and the written write data D is transmitted.
A plurality of first RAM chips MC11 for writing W1
To MC1m, and similarly, a predetermined memory cell is selected from the plurality of memory cells according to the transmitted internal address signal AD2 and internal control signal CNT2 including the plurality of memory cells, and the stored data is read from this memory cell. , A memory module card 110x having a plurality of second RAM chips MC21 to MC2n for writing the transmitted write data DW2, a data control unit 114, an address control unit 115, and an access control unit 116,
The address signal A transmitted from the host system circuit 210x installed in the host system card 200x equipped with the host system circuit 210x such as a data processing system.
Internal address signals AD1 and AD2, internal control signal CNT according to D, control signal CNT, and bank designation signal BD
1, CNT2 are generated and host system circuit 210
x and RAM chips MC11 to MC1m, MC21 to MC
The memory control integrated circuit 113 for controlling the transmission of the write data DW, DW1, DW2 and the read data DR, DR2, DR between 2n and the 2n, and the memory control integrated circuit 113 installed at a predetermined position of the memory module card to the upper system card 200x. The memory control integrated circuit 113 and the RAM chips MC11 to MC1m and MC2 are connected to the equipped connector 220x.
Internal address signals AD1, AD2 between 1 and 2n, internal control signals CNT1, CNT2, write data DW
1, DW2 and relay of read data DR1, DR2,
It is configured to have a connector 120x that forms a memory module 100x together with the memory module card 110x for transmitting information. In this example, the first R
The AM chips MC11 to MC1m are the first memory bank 1
11 to form the second RAM chips MC21 to MC2n
Form a second memory bank 112, and control of writing and reading of data is performed in units of these memory banks 111 and 112.

As described above, in the conventional semiconductor memory device, the S
The IMM type memory module 100x is equipped with only the RAM chips MC11 to MC1m and MC21 to MC2n, and the memory control integrated circuit 113 (memory controller) for controlling the operation of these RAM chips is equipped in the upper system card 200a ( For example, Japanese Patent Laid-Open No. 4-2
No. 33046, JP-A-4-230544).

[0006]

This conventional semiconductor memory device has a plurality of RAM chips MC11 to MC1m and MC21 to MC21 forming first and second memory banks 111 and 112 in a SIMM type memory module 100x.
A memory integrated circuit 113 (memory controller) that is equipped only with 2n and controls the operation of these RAM chips in memory bank units is provided in the upper system card 200a, and has an internal address for controlling the RAM chips of these memory banks. Signals AD1 and AD2, internal control signals CNT1 and CNT2, and write data DW1 and DW
2 and the transmission of the read data DR1 and DR2 are performed by the connector 1
Since it is configured to perform through 20x and 220x,
There are problems that the number of pins of the connectors 120x and 220x increases, the connectors become expensive, the connector becomes large and the mounting density decreases, and the internal address signals AD1 and AD2 and the internal control signals CNT1 and CNT2. , Write data DW1, DW2 and read data DR
There is a problem that the transmission distance of 1 and DR2 is long, the skew of these signals increases, the operation time becomes long, and high-speed operation is difficult.

An object of the present invention is to reduce the number of pins of the connector to reduce the cost, downsize, and improve the mounting density of the connector, and to shorten the transmission distance of various internal signals to reduce the skew and to operate. An object of the present invention is to provide a semiconductor memory device capable of achieving high speed.

[0008]

A semiconductor memory device of the present invention includes a plurality of arranged memory cells, and selects a predetermined memory cell among the plurality of memory cells according to an internal address signal and an internal control signal transmitted. A plurality of memory banks each including a plurality of memory chips for selecting and reading stored data from the memory cell and writing the transmitted write data, and the internal address signal and the internal address signal according to the transmitted address signal and control signal. An internal control signal is generated and transmitted to each memory chip of each of the plurality of memory banks to control the operation of the plurality of memory chips, and the transmitted write data to the plurality of memory chips. Memory control integrated circuit that controls the transmission of data and the transmission of read data from these multiple memory chips. A memory module card equipped with a memory module card and a connector of a host system card installed at a predetermined position of the memory module card and equipped with a host system circuit, for connecting the address signal, the control signal and the write signal from the host system circuit. Connector for relaying and transmitting the data of (1) to the memory control integrated circuit and relaying and transmitting the read data from the memory control integrated circuit to the upper system circuit to form a single in-line memory module together with the memory module card. And have.

The writing data and the reading data are relayed and transmitted through the same pin of the connector.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this embodiment, a predetermined memory cell is selected from the plurality of memory cells according to the transmitted internal address signal AD1 and internal control signal CNT1 including a plurality of arranged memory cells, and the selected memory cell is selected. On the other hand, a plurality of first RAM chips MC11 to MC for reading the stored data and writing the transmitted write data DW1
A first memory bank 111 of 1 m, which also includes a plurality of memory cells, selects a predetermined memory cell from the plurality of memory cells in accordance with the transmitted internal address signal AD2 and internal control signal CNT2, and selects this memory cell. Data DW for reading and transmitting transmitted memory data
A plurality of second RAM chips MC21 to
The second memory bank 112 composed of MC2n and the data control unit 114, the address control unit 115 and the access control unit 116 are included, and the internal address signals AD1 and AD2 are transmitted in accordance with the transmitted address signal AD, control signal CNT and bank designation signal BD. And internal control signals CNT1, C
NT2 is generated, and the RAM chips MC11 to MC1 of these memory banks 111 and 112 are generated for each memory bank 111, 112.
m, MC21 to MC2n to control the operation of these RAM chips, and at the same time, control the transmission of the write data (DW) transmitted to these RAM chips.
A memory module card 110 including a memory control integrated circuit 113 for controlling transmission of read data (DR1, DR2) from the M chip, and a host system circuit 21 installed at a predetermined position of the memory module card 110.
Connector 2 of host system card 200 equipped with 0
20 and relays and transmits the address signal AD, the control signal CNT, the bank designation signal BD, and the write data DW from the host system circuit 210 to the memory control integrated circuit 113, and the read data from the memory control integrated circuit 113. It is configured to have a connector 120 that relays and transmits the DR to the host system circuit 210 and forms the SIMM type memory module 100 together with the memory module card 110.

FIG. 2 is a side view of the semiconductor memory device of this embodiment mounted on a host system card 200.

In this embodiment, since the memory module integrated circuit 113 is installed in the memory module card 110, the signals relayed and transmitted by the connectors 120 and 220 are the address signal A from the host system circuit 210.
D, control signal CNT, bank designation signal BD, write data DW, and read data DR to the upper system circuit 210 are all that is required, and internal address signals AD1 and AD2 and internal control signal CN are set for each memory bank 111 and 112.
Compared with the conventional example in which T1 and CNT2, the write data DW1 and DW2, and the read data DR1 and DR2 are relayed and transmitted, the amount is reduced to approximately 1/2. Therefore, the cost of the connectors 120 and 220 can be reduced and the connectors can be downsized, so that the mounting density can be increased. Further, since the distance between the memory control integrated circuit 113 and each of the RAM chips MC11 to MC1m and MC21 to MC2n becomes shorter and the signal line length of each signal between them becomes short, the skew of these signals is reduced, High-speed operation becomes possible.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

In this embodiment, the host system circuit 210a is used.
The write data DW and the read data DR between the memory control integrated circuit 113a and the memory control integrated circuit 113a are transmitted and relayed by the same signal line and the same connector pin. Therefore, the number of pins of the connectors 120a and 220a can be further reduced.

Along with this, it is necessary to provide the memory control integrated circuit 113a and the host system circuit 210a with means for switching between the data DW for writing and the read data DR.

[0018]

As described above, according to the present invention, the memory module integrated circuit is mounted on the memory module card, so that the relay is performed by the connector of the memory module.
Since the number of signals to be transmitted can be significantly reduced compared to the conventional example required for each memory bank, the cost of the connector can be reduced, and the connector can be miniaturized and the mounting density can be reduced. Moreover, since the distance between the memory control integrated circuit and the memory chip is close and the length of the signal line between them is shortened, the skew of each signal is reduced and the operation speed is increased. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

2 is a side view of the embodiment shown in FIG. 1. FIG.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing one row of a conventional semiconductor memory device.

[Explanation of symbols]

100, 100a, 100x memory module 110, 110a, 110x memory module card 111, 112 memory bank 113, 113a memory control integrated circuit 114 data control unit 115 address control unit 116 access control unit 120, 120a, 120x connector 200, 200a, 200x Host system card 210, 210a, 210x Host system circuit 220, 220a, 220x Connector MC11-MC1m, MC21-MC2n RAM chip

Claims (3)

[Claims] 1. A predetermined memory cell is selected from the plurality of memory cells according to an internal address signal and an internal control signal transmitted including a plurality of arranged memory cells, and stored data is read from the selected memory cell. A plurality of memory banks configured to write the transmitted write data, and a plurality of memory banks that generate the internal address signal and the internal control signal according to the transmitted address signal and control signal For each memory chip of the memory bank to control the operation of the plurality of memory chips, and to control the transfer of the write data transmitted to the plurality of memory chips, and read from the plurality of memory chips. A memory module card having a memory control integrated circuit for controlling data transmission, and this memory module card. To the memory control integrated circuit of the address signal, the control signal and the write data from the host system circuit, which is installed at a predetermined position of the memory module card and is connected to the connector of the host system card equipped with the host system circuit. And a connector forming a single in-line memory module together with the memory module card for relaying and transmitting the data, and relaying and transmitting the read data from the memory control integrated circuit to the host system circuit. Storage device. 2. The semiconductor memory device according to claim 1, wherein write data and read data are relayed and transmitted through the same pin of the connector. 3. The semiconductor memory device according to claim 2, wherein the memory control integrated circuit and the host system circuit are provided with a switching means for switching between write data and read data.