JPH0552979B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having multiple ports.

[Conventional technology]

Some conventional semiconductor memory devices have multiple ports for inputting control signals, address signals, and data input/output, and multiple external devices can be connected to the semiconductor memory device independently through each port. can be accessed.

A case where there are two ports will be described below.

A conventional example will be explained with reference to FIG.

In FIG. 3, a third memory 300 has two ports 301 and 302. The first port 301 has a first central processing unit (hereinafter referred to as CPU).
) 303 and the first memory 304 are
address bus 305 and a first data bus 30
On the other hand, a second CPU 307 and a second memory 308 are connected to the second port 302 via a second address bus 309 and a second data bus 310. has been done.

This connection connects the first CPU 303 and the second CPU 303.
The CPU 307 can write and read data from the respective ports 301 and 302 to the third memory 300, and as a result, the third memory 300 can be shared.

However, since it is generally difficult to increase the density of a memory having multiple ports, it is expensive and the storage capacity of the memory cannot be increased. As a result, each CPU 303, 307 is also equipped with a dedicated memory 304, 308 with a large storage capacity.
In FIG. 3, third memory 300 has a small capacity, and first memory 304 and second memory 308 have relatively large capacities.

[Problem that the invention seeks to solve]

Therefore, in a conventional system including a semiconductor memory device with multiple ports, in order to secure sufficient storage capacity without increasing manufacturing costs, each CPU must be provided with a dedicated memory device. As a result, in order to access data stored in the dedicated memory device of another CPU, the data must be transferred to the shared semiconductor memory device in advance, which reduces system efficiency. arise.

An object of the present invention is to provide a semiconductor memory device having multiple ports capable of high-speed data transfer.

[Means for solving problems]

The present invention provides a semiconductor memory device having a common internal memory capable of storing data and having a plurality of ports to which control signals and address signals are supplied and which enable data to be exchanged between the internal memory and external equipment. A first means for transferring an address signal and a control signal between a selected port and another selected port of the plurality of ports; and a first means for transferring an address signal and a control signal between the selected port and the other selected port. The present invention is characterized in that it further comprises a second means for transferring data stored in the internal memory between the two without changing the data.

[Effect]

When a system as shown in FIG. 3 is configured using the semiconductor storage device having the above configuration, the CPU connected to one of the multiple ports sends address signals and control signals to the memory connected to the other ports. etc., and data can be directly exchanged with the memory.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an electrical circuit diagram showing the configuration of a first embodiment of the present invention. In the first embodiment, two sets of ports 1
00 and 101 are connected to the internal memory 102. The address signal or control signal input terminal 103 of the first port 100 is connected to the first inverter 1
04 and the output of the first output driver 105, and the first inverter 10
The output of 4 is the memory address input or control signal input of the first port and the second output driver 106.
The address signal or control signal input terminal 107 of the second port 101 is connected to the input of the second inverter 108 and the second
is connected to the output of the output driver 106.
The output of the second inverter 108 is connected to the second port 1
It is connected to the address input or control signal input of the memory No. 01 and the input of the first output driver 105. The signal ψ ₁ is provided to the first output driver 105 to control the impedance and output of the output driver. The signal ψ ₂ is the second output driver 1
06 to control the impedance and output of the output driver.

Regarding the control signal output terminal 110, the first AND circuit 111 is supplied with the negative phase signal of the signal ψ ₁ and the negative phase signal of the signal ψ ₂ , and its output is supplied to the seventh output driver 112 and the eighth output driver 112. It is connected to the output driver 113 to control the impedance of the output driver. Seventh output driver 11
2 inputs the first port control output signal of the memory and is connected to the control signal output terminal 110 of the first port. The eighth output driver 113 inputs the control output signal of the second port 101 of the memory,
It is connected to the control signal output terminal 114 of the second port. The input of the ninth output driver 115 is
The output is connected to the control signal output terminal 114 of the first port 101, and the impedance state is controlled by the signal ψ ₂ . The input of the tenth output driver 116 is connected to the control signal output terminal 110 of the first port 100, the output thereof is connected to the control signal output terminal 114 of the second port 101, and the impedance state is changed by the signal ψ ₁ . is controlled.

Data input/output terminal 120 of first port 100
are connected to the input of the third inverter 121, the output of the third output driver 122, the input of the fifth inverter 123, and the output of the fifth output driver 124, respectively. The input of the output driver 122 is the first port 1
00 memory input/output (hereinafter referred to as I/O), and the output of the fifth inverter 123 and the input of the fifth output driver 124 are connected to the sixth inverter 12.
5 and the input of the sixth output driver 126. The data input/output terminal 127 of the second port 101 is connected to the input of the fourth inverter 128, the output of the fourth output driver 129, the input of the sixth inverter 125, and the output of the sixth output driver 126, respectively. , fourth inverter 1
The output of 28 and the input of the third output driver 122 are connected to the memory I/O of the second port 101. The signal ψ ₃ is sent to the third output driver 122,
The signal ψ ₅ is input to the third inverter 121, and the signal ψ ₄ is input to the fourth output driver 129.
The signals ψ ₆ are respectively input to fourth inverters 128 . Signal ψ ₉ is the fifth output driver 1
24, the signal ψ ₇ is input to the fifth inverter 123, the signal ψ ₁₀ is input to the sixth output driver 126, and the signal ψ ₈ is input to the sixth inverter 125.

Next, the operation in this embodiment will be explained. Normally, when writing to and reading from memory, both signals ψ ₁ and ψ ₂ are set to low level. This puts the first output driver 105 and the second output driver 106 in a high impedance state,
The address input signal or control input signal input to the first port 100 and the second port 101 is input to the first inverter 104 and the second inverter 1.
It becomes a signal input to the internal memory 102 via 08. Further, the signal ψ ₇ , the signal ψ ₈ , the signal ψ ₉ , and the signal ψ ₁₀ are all set to low level. As a result, the fifth inverter 123 and the sixth inverter 12
The output of No. 5 is in a high impedance state. Furthermore, when the signal ψ ₉ and the signal ψ ₁₀ go low, the fifth output driver 124 and the sixth output driver 126 enter a high impedance state. Therefore, the data input/output terminals 120 of the first port 100 and the second port 101 are controlled by the fifth output driver 124 and the sixth output driver 126
127 will not be affected. To perform a write operation from the first port 100 to the memory, the third inverter 121 transfers the data from the data input/output terminal 120 to the memory I by setting the signal ψ ₅ to high level and the signal ψ ₃ to low level. Output to /O. On the other hand, the third output driver 12
2 is in a high impedance state, so it does not affect the data at the data input/output terminal 120. Also, when reading, the signal ψ ₅ is set to low level,
When the signal ψ ₃ is respectively shifted to a high level, the third inverter 121 is in a high impedance state and has no effect on the memory I/O, and the third output driver 122 is connected to the memory I/O. The data supplied from the input/output terminal 120 is outputted to the data input/output terminal 120.

Similarly, when writing to the second port 101, the signal ψ ₆ is set to high level, and the signal ψ ₄ is set to high level.
is shifted to a low level, thereby causing the fourth inverter 128 to transfer the data at the data input/output terminal 127 to the memory I/O. On the other hand, the fourth
Since the output driver 129 is in a high impedance state, it does not affect the data at the data input/output terminal. On the other hand, when reading, the signal ψ ₆ is shifted to a low level, the signal ψ ₄ is shifted to a high level,
The fourth inverter 128 is placed in a high impedance state to eliminate the influence on memory I/O.
Therefore, the fourth output driver 129 transfers the data appearing at the memory I/O to the data input/output terminal. At the control signal output terminal, the signal ψ ₁
and signal ψ ₂ are both at low level, the output of the first AND circuit 111 becomes high level, and the output of the seventh output driver 112 and the eighth output driver 11
3 outputs respective data to the first port 100 and the second port 101 in accordance with the control signal output of the memory. Further, when the signal ψ ₁ and the signal ψ ₂ are at low level, the ninth output driver 115 and the tenth output driver 116 are in a high impedance state and have no influence on the control signal output terminals 110 and 114.

Next, the operation when passing address signals, control signals, and data from one port to another port will be described. First, consider a case where an address signal and a control signal are passed from the first port 100 to the second port 101, and the CPU on the first port side inputs and outputs data on the second port side. In this case, the signal ψ ₁ is shifted to a low level and the signal ψ ₂ is shifted to a high level. This makes the first
The output driver 105 is in a high impedance state and does not affect the address or control signal input terminal 103 of the first port 100. The first inverter 104 and the second inverter 108 operate and output an address or control signal to the internal memory 102, but since the memory is not operated in this mode, it has nothing to do with the memory. The second output driver 106 receives the output of the first inverter 104 and outputs the address or control signal input signal of the first port 100 to the address or control signal input/output terminal 107 of the second port 101 . Note that the signal ψ ₃ , the signal ψ ₅ , the signal ψ ₄ , and the signal ψ ₆ are all at low level. As a result, the third inverter 121, the third output driver 122, the fourth
inverter 128, fourth output driver 129
are all in a high impedance state and have no effect on the internal memory 102.

Next, from the first port 100 to the second port 1
In the case of an operation to move the data appearing at 01, the signal ψ ₇ and the signal ψ ₁₀ are set to low level, and the signal ψ ₈
and signal ψ ₉ to high level. This allows the fifth
inverter 123 and sixth output driver 12
6 is in a high impedance state and does not affect input/output data. On the other hand, the sixth inverter 125 receives the data from the second port 101 and outputs the data appearing at the data input/output terminal 127 of the second port 101 to the fifth output driver 124 . The fifth output driver 124 is the sixth
It receives the output data of the inverter 125 and outputs the data of the second port 101 to the data input/output terminal 120 of the first port 100.

The operation for moving data appearing at the first port 100 from the second port 101 is similar, with the signals ψ ₈ and ψ 9 being set to low level, and the signals ψ ₇ and ψ ₉ being at low level.
Set signal ψ ₁₀ to high level. In this case, contrary to the above, the fifth output driver 124 and the sixth inverter 125 are in a high impedance state and have no effect on data. The fifth inverter 123 receives the data from the first port 100 and outputs the data from the data input/output terminal 120 of the first port 100 to the sixth output driver 126 . The sixth output driver 126 receives the output of the fifth inverter 123 and outputs the data of the first port 100 to the data input/output terminal 127 of the second port.

As a result, the first port 100 outputs an address and a control signal to the second port 101, and data can be input/output between the first port 100 and the second port 101. Also the signal ψ ₂
is at a high level, the first AND circuit 111
The output of the seventh output driver 1 becomes low level.
The twelfth and eighth output drivers 113 are in a high impedance state and have no effect on the control signal output terminal. The ninth output driver 115 outputs the data at the control signal terminal 114 of the second port 101 to the control signal terminal 110 of the first port 100 due to the high level of the signal ψ ₂ . Since the signal ψ ₁ is at a low level, the tenth driver 116 is in a high impedance state and has no effect on the control signal terminal. This allows the second port 101 to output a response control signal to the first port 100 in response to the request control signal for this mode from the first port 100 to the second port 101.

Then from the second port 101 to the first port 1
Outputs address and control signals to 00,
Consider the case of inputting and outputting data. In this case, the signal ψ ₁ is set to high level and the signal ψ ₂ is set to low level.
As a result, the second output driver 106 enters a high impedance state with respect to the address and control signal inputs, eliminating the influence of data, and the first output driver 105 receives the output of the second inverter 108 and The address or control signal of the port 101 is output to the address or control signal input/output terminal 103 of the first port 100. Regarding the control signal output, the seventh output driver 112 and the eighth output driver 113 enter a high impedance state due to the low level of the signal ψ ₂ , and have no effect. Furthermore, the ninth output driver 115 enters a high impedance state due to the low level of the signal ψ ₂ and is similarly unaffected. On the other hand, the tenth output driver 116 transfers the data at the control signal output terminal 110 of the first port 100 to the control signal output terminal 114 of the second port 101 due to the high level of the signal ψ ₁ .
Output to. 1st port 10 for data
0 to the second port 101 and from the second port 101 to the first port 100.
This is the same as when outputting an address and control signal to port 101.

In the first embodiment, the first and second inverters 104,
108, the first means is constituted by the first, second, seventh, eighth, ninth, and tenth output drivers, and the third to sixth inverters 121, 128, 123, 1
25 and the third to sixth output drivers 122, 12
9, 124, and 126 constitute a second means.

FIG. 2 is a circuit diagram showing the configuration of a second embodiment of the present invention.

The structure related to address signals is common to the embodiment shown in FIG. 1, and the explanation thereof will be omitted here. In FIG. 2, a first inverter 201 receives data input from a first port 202 and outputs data to the memory I/O. The first output driver 203 receives memory I/O data and outputs the data to the data input/output terminal 204 of the first port 202 . The second inverter 205
Memory I/
Output data to O. The second output driver 207 receives the memory I/O data and outputs the data to the data input/output terminal 208 of the second port 206 . The first buffer 209 and the second buffer 210 receive the output of the second inverter 205 as input, and the output is controlled by the signal _A1 , and the output is sent to the first output driver 203.
becomes the input signal. Third buffer 211 and fourth
The buffer 212 receives the output of the first inverter 201 as an input, and its output is controlled by the signal A ₂ , and its output becomes the input signal of the second output driver 207 .

Next, the operation of this embodiment will be explained. In the case of write or read operations from the first port 202 or the second port 206 to the memory, the signal
A ₁ and signal A ₂ are both set to low level. As a result, the first buffer 209, the second buffer 210,
The third buffer 211 and the fourth buffer 212 are all in an output high impedance state, and do not pose any problem when writing to or reading from the memory. The operations of the first inverter 201, first output driver 203, second inverter 205, and second output driver 207 for normal memory are the same as in the first embodiment.

Next, consider the case where data moves from the first port 202 to the second port 206. In this mode, the operation of the memory is prohibited as in the first embodiment. Signal W ₁ high level,
Signal R ₁ low level, signal W ₂ low level, signal R ₂
is set to high level, signal _A1 is set to low level, and signal _A2 is set to high level. At this time, the outputs of the first output driver 203, the first buffer 209, the second buffer 210, and the second inverter 205 are in a high impedance state. The first inverter 201 receives the input of the first port 202 and outputs the data of the first port 202 to the inputs of the third buffer 211 and the fourth buffer 212 . The third buffer 211 and the fourth buffer 212 receive the data and output the data to the input of the second output driver 207. The second output driver 207 receives the data and outputs the input data of the first port 202 to the input/output terminal of the second port 206. This moves data from the first port 202 to the second port 206.

Also, from the second port 206 to the first port 20
When moving data to 2, similarly set signal W ₁ to low level, signal R ₁ to high level,
A ₁ is set to high level, signal A ₂ is set to low level, signal W ₂ is set to high level, and signal R ₂ is set to low level. As a result, the outputs of the first inverter 201, the third buffer 211, the fourth buffer 212, and the second output driver 207 enter a high impedance state. Data input from the second port 206 is input to the first buffer 209 and the second buffer 210 by the second inverter 205 . First buffer 209 and second buffer 2
10 outputs the data to the input of the first output driver 203, and the first output driver 203 outputs the data input at the second port 206 to the input/output terminal 204 of the first port 202.

This allows data to be moved from the second port 206 to the first port 202.

Compared to the first embodiment, this embodiment has the advantage that the memory I/O bus and input/output circuits are shared, so that the circuit can be made smaller.

the first and second inverters 201, 205;
First and second output drivers 203, 207 and first to fourth buffers 209, 210, 211, 2
12 constitutes the second means as a whole.

〔Effect of the invention〕

As explained above, the present invention has a common internal memory that can store data, and has a plurality of ports that are supplied with control signals and address signals and that enable data to be exchanged between the internal memory and external devices. A semiconductor memory device comprising: a first means for transferring an address signal and a control signal between a selected port and another selected port of the plurality of ports; The device further includes a second means for transferring the data stored in the internal memory to the selected port without changing the data, so that data is transferred directly from one port to another port. It becomes possible to
This has the effect of allowing faster data transfer for systems with multiple CPUs and multiple buses, making it possible to configure a more efficient system.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of the second embodiment of the present invention, and FIG. 3 is a conventional example and an example of application of the present invention. It is a block diagram. 100,202...first port, 101,2
06...Second port, 102...Internal memory,
103, 107...address input/control signal input terminal, 104...first inverter, 105...first output driver, 106...second output driver,
108...Second inverter, 110, 114...
Control signal output terminal, 111...first AND circuit,
112...7th output driver, 113...8th output driver, 115...9th output driver, 11
6...10th output driver, 120, 127...data input/output terminal, 121...3rd inverter, 1
22...Third output driver, 123...Fifth inverter, 124...Fifth output driver, 125...
...Sixth inverter, 126...Sixth output driver, 128...Fourth inverter, 129...Fourth
Output driver, 201...first inverter, 2
03...First output driver, 204, 208...
Data input/output terminal, 205... second inverter, 207... second output driver, 209...
First buffer, 210...Second buffer, 2
11...Third Batsuhua, 212...Fourth Batsuhua.

Claims (1)

[Claims] 1. A device having a common internal memory capable of storing data, and having a plurality of ports to which control signals and address signals are supplied and which enable data to be exchanged between the internal memory and an external device. A semiconductor memory device comprising: a first means for transferring an address signal and a control signal between a selected port of the plurality of ports and another selected port; and a first means for transferring an address signal and a control signal between the selected port and the other selected port. A semiconductor memory device further comprising: second means for transferring data stored in the internal memory to and from a port without changing the data stored in the internal memory.