JPH0846659A - Symbol clock controller - Google Patents

Abstract

PURPOSE:To prevent the increase in the arithmetic amount for extracting timing due to increase in the number of carriers by providing a clock generator outputting a symbol clock signal synchronously with a baud rate of a received signal to an external device. CONSTITUTION:A cross correlation device 140 obtains cross correlation between an output signal from a power computing element 120 and an output signal from a reference pilot signal generator 130 in a timing synchronous with a sample clock signal and a correlation arithmetic clock signal. Upon the receipt of an output signal from the cross correlation device 140, a maximum part detector 150 detects a time of a highest correlation value as a timing optimum point for each period of a pilot clock signal. A clock generator 160 changes a phase of a clock signal so that a DC component of an output signal from the maximum part detector 150 is zero and generates a pilot clock signal and a symbol clock signal synchronous with the reception signal and the symbol clock signal is outputted to an external device from an output terminal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION In mobile radio communication transmitting digital signals, deterioration of signal quality due to fading caused by multiple propagation and delay dispersion distortion is a serious problem.

As a method of reducing the deterioration due to fading, there is a pilot insertion method in which a pilot signal is inserted into a transmission data signal at regular intervals, the receiving side detects it, and the data signal is corrected.

As a method of reducing delay dispersion distortion, there is a multi-carrier method that reduces the influence of delay dispersion distortion by lowering the transmission rate per wave by a frequency division method.

In mobile communication, as the high speed transmission becomes necessary, the importance of the pilot signal insertion method and the multi-carrier method will increase.

On the other hand, data transmission requires synchronization of frequency and symbol clock on both sides of the transmitter and receiver.

The present invention relates to a symbol clock control device for performing symbol clock synchronization when a pilot signal insertion system and a multicarrier system are used.

[0007]

2. Description of the Related Art FIG. 2 shows a symbol clock control device using a conventional single carrier system.

From the terminal 200, the real and imaginary components of the complex baseband signal are converted into bandpass filters 210, 21.
1 is input.

In the bandpass filters 210 and 211, as shown in FIG. 3, a signal component of a portion apart from the center frequency by half the baud frequency is extracted. The bandpass filter 210 takes out the upper part of the spectrum, and the bandpass filter 211 takes out the lower part of the spectrum.

The complex output signal of the bandpass filter 210 and the conjugate complex output signal of the bandpass filter 211 are input to the complex multiplier 220 and subjected to complex multiplication.

Since the output signal of the complex multiplier 220 includes the data signal component in addition to the symbol clock signal component, it is usually a symbol clock signal that contains a considerable amount of jitter. Therefore, the output signal of the multiplier 220 is further P
The clock signal 240 is input to the LL 230, and the PLL 230 outputs the clock signal 240 synchronized with the high-quality symbol clock from which the jitter component is removed.

[0012]

However, in the multi-carrier type modulation system, when trying to extract a clock for each carrier, the number of bandpass filters increases in proportion to the number of carriers. Since the bandpass filter generally has a large amount of calculation in order to obtain a narrow band characteristic, there is a drawback that the calculation process for timing extraction becomes larger than other calculation processes.

Therefore, an object of the present invention is to prevent an increase in the calculation amount of timing extraction due to an increase in the number of carriers.

[0014]

As means for solving the above problems in the present invention, multi-carrier modulation of a baseband signal composed of two or more in which a pilot signal is periodically time-divided into a data signal sequence on the transmission side is carried out. In a receiver for receiving the received signal as a received signal, a sampler for receiving the received signal and a sampling clock signal that are temporally continuous and sampling the received signal in synchronization with the sampling clock signal and outputting it as a discrete received signal, A power calculator that inputs the output signal of the sampler and the sample clock signal, calculates the square value of the sampler output signal in synchronization with the sample clock signal, and outputs the same, and the power calculator that receives the sample clock signal and is the same as the pilot signal. A reference pilot signal generator for outputting discrete power values of a signal, said power Cross-correlation that receives the output signal of the calculator, the output signal of the reference pilot signal generator, and the sample clock signal, and calculates and outputs the cross-correlation between the output signal of the power calculator and the output signal of the reference pilot signal generator Receiving the output signal of the cross-correlator, the pilot clock signal and the sample clock signal, the temporal position of the highest cross-correlation among the output signals of the cross-correlator within one period of the pilot clock signal. And a pilot detecting unit that outputs a phase shift signal from the pilot clock signal, and receives the output signal of the maximum unit detector so that the phase shift signal of the maximum unit detector becomes zero. The symbol clock signal synchronized with the baud rate of the received signal is output externally while outputting the clock signal and the sample clock signal. Characterized by comprising the output clock generator.

[0015]

Next, the present invention will be described with reference to the drawings.

FIG. 4 is a diagram showing a signal structure on a time axis of each carrier of a transmission signal composed of four waves.

In each carrier, three symbols of pilot signals are inserted in a data signal arranged at a symbol rate T _b at a constant period T _p . In FIG. 4, T _p is 16 times T _b .

In the present invention, symbol clock control is performed using amplitude information of the received signal. If the phase information of the received signal is also used for symbol clock control, further improvement in control capability can be expected, but for that purpose, it is necessary to synchronize the modulation frequency on the transmission side and the demodulation frequency on the reception side in advance. Therefore, here, control is performed using only the amplitude component of the received signal that is not affected by the frequency shift.

FIG. 5 shows an example of temporal changes in the amplitude component of the four-wave synthesized signal. As shown in FIG. 5, the signal waveform of the portion in which the pilot signal is inserted is the same everywhere, so that the signal shape can be detected by using cross-correlation. Here, the case of four-wave synthesis will be described, but the case of five or more waves can be similarly processed.

FIG. 1 is a block diagram showing an embodiment of the present invention.

The complex reception signal demodulated into the baseband signal is input from the input terminal 100, and is converted by the sampler 110 from a continuous signal into a temporally discrete signal synchronized with the sample clock signal. When the cycle of the sample clock signal is T _s and the input signal of the sampler is r (t), the output signal can be expressed as r (nT _s ). Here, the period T _s of the sample clock signal is four times the period T _b of the symbol clock signal.

In the power calculator 120, the input signal r (nT
_In order to obtain the amplitude component of _s ), the square operation is performed and the power component p (nT _s ) is obtained as shown in (1).

Here, r ^* (nT _s ) is a conjugate complex signal of r (nT _s ).

P (nT _s ) = r (nT _s ) × r ^* (nT _s ) (1) In the reference pilot signal generator 130, the discrete values of the power components of the four-wave combined pilot signal are stored as replica signals. Has been done. FIG. 6 shows an example of a replica signal consisting of 12 samples. The reference pilot signal generator 130 is composed of 12 memories as shown in FIG.

In the cross-correlator 140, the power calculator 120
From the reference pilot signal generator 140 and the output signal from the reference pilot signal generator 140 are obtained at the timing synchronized with the sample clock signal and the correlation calculation clock signal.

The output signal from the power calculator 120 is q (n
T _s ), and the 12 replica signals output from the reference pilot signal generator 130 are g (0) to g (11T _s ), the cross-correlation value h (nT _s ) is calculated as in equation (2). To be

[0027]

[Equation 1]

In the maximum part detector 150, the cross-correlator 14
When the output signal from 0 is received, the time of the correlation value having the highest correlation value is detected as the optimum timing point for each period T _p of the pilot clock signal. The time difference between the optimum point and the falling point of the pilot clock signal is output as a phase difference. The optimum point of the cross-correlation value, the temporal relationship between the pilot clock signal and the output signal are shown in a and b of FIG. 8A is a diagram when the phase of the pilot clock signal is advanced, and FIG. 8B is a diagram when the phase of the pilot clock signal is delayed.

In the clock generator 160, the maximum detector 1
The phase of the clock is changed so that the DC component of the output signal from 50 becomes 0, the pilot clock signal and the symbol clock signal which are synchronized with the received signal are generated, and the symbol clock signal is output from the output terminal 170 to the outside. .
FIG. 9A is a diagram showing the phases of the received signal and each clock signal when the DC component of the output signal from the maximum detector 150 is not zero. FIG. 9B shows the maximum detector 150.
It is a figure when the direct-current component of the output signal from is 0.

As described above, the symbol clock synchronization signal can be obtained from the received signal.

[0031]

As described above, according to the present invention, even if the number of carriers increases, the arithmetic processing system is not affected, so that the symbol clock signal control can be performed with the same amount of calculation as in the single carrier system. it can.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a conventional symbol clock control circuit.

FIG. 3 is a diagram showing a received signal spectrum and a frequency characteristic of a bandpass filter in a conventional symbol clock control circuit.

FIG. 4 is a diagram showing insertion positions of pilot signals of respective waves in a 4-wave multicarrier system.

FIG. 5 is a diagram showing a temporal change of a power component of a four-wave combined signal.

FIG. 6 is 4 stored in a reference pilot signal generator
It is the power component of the pilot signal portion of the wave-combined signal.

FIG. 7 is a diagram showing an internal structure of a reference pilot signal generator.

FIG. 8 is a diagram showing a relationship between an output signal from the maximum part detector 140 and a symbol clock signal. a is a state in which the phase of the symbol clock signal is advanced, and b is a state in which the phase of the symbol clock signal is delayed.

9 is a diagram showing a relationship between an input signal and an output signal of the clock generator 160. FIG. “A” is in a non-synchronized state, and “b” is in a synchronized state.

[Explanation of symbols]

 100 Input Terminal 110 Sampler 120 Power Calculator 130 Reference Pilot Signal Generator 140 Cross Correlator 150 Maximum Part Detector 160 Clock Generator 170 Output Terminal 200 Input Terminal 201 Input Terminal 210 Bandpass Filter 211 Bandpass Filter 220 Complex Multiplier 230 PLL 240 output terminal

Claims (1)

[Claims] 1. A receiver for receiving as a reception signal a signal obtained by multicarrier-modulating a baseband signal composed of two or more, in which a pilot signal is periodically time-divided into a data signal sequence on the transmission side, A sampler which receives the continuous reception signal and sampling clock signal and samples the reception signal in synchronization with the sampling clock signal to output as a discrete reception signal; and an input signal of the sampler output signal and the sample clock signal A power calculator that calculates and outputs a squared value of the sampler output signal in synchronization with a clock signal; a reference pilot signal generator that receives the sample clock signal and outputs a discrete power value of the same signal as the pilot signal; An output signal of the power calculator and an output signal of the reference pilot signal generator A cross-correlator that receives the sample clock signal and obtains and outputs the cross-correlation between the output signal of the power calculator and the output signal of the reference pilot signal generator; and an output signal of the cross-correlator, a pilot clock signal, and A maximum of receiving a sample clock signal, detecting the temporal position of the highest cross-correlation among the output signals of the cross-correlator within one cycle of the pilot clock signal, and outputting a phase shift signal with respect to the pilot clock signal. Part detector and the output signal of the maximum part detector, and outputs the pilot clock signal and the sample clock signal so that the phase shift signal of the maximum part detector becomes 0 and the baud rate of the received signal. Symbol consisting of a clock generator that outputs a symbol clock signal synchronized with Lock control device.