JPH0836496A - Microcomputer - Google Patents

Abstract

PURPOSE:To increase processing speed when an instruction which is impossible to be executed in an emulation mode is executed in a native mode. CONSTITUTION:A microcomputer 700 has an emulation mode and a native mode. The microcomputer 700 contains a general purpose register group 111. In the general purpose register group 111, a register XR which is not used in the emultion mode exists. When a prescribed instruction code to be trap factor is supplied to the microcomputer 700 when the microcomputer operates in the emulation mode, the microcomputer stores a value showing the code length from the first byte of a prescribed instruction code to the trap operation instruction and the instruction code which can be recognized in the register XR and shifts the mode to the native mode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer which generates an interrupt when a predetermined instruction code is input during emulation.

[0002]

2. Description of the Related Art The performance of microcomputers (hereinafter referred to as "microcomputers") has been remarkably improved, and the microcomputers used have been upgraded to higher-level microcomputers.

However, when a higher-order microcomputer is used, one problem is whether or not the software for the lower-order microcomputer which has been conventionally used can be used as it is. Generally, since the higher-level microcomputer has a different architecture from the lower-level microcomputer, the software developed for the lower-level microcomputer cannot be operated by the higher-level microcomputer as it is. Therefore, if the higher-level microcomputer does not have the function of executing the instructions of the lower-level microcomputer (hereinafter referred to as the emulation function), the work for porting the software for the lower-level microcomputer to the higher-level microcomputer is required. Due to restrictions such as man-hours, work becomes more difficult as the amount of software to be ported increases.

Therefore, it is very effective to provide the host microcomputer with an emulation function in terms of effective use of conventional software resources and cost and man-hours required for software porting.

By the way, in a microcomputer having an emulation function, if an instruction that cannot be executed in a mode in which emulation is performed (hereinafter referred to as an emulation mode) is possible due to a hardware limitation, such an instruction In the emulation mode, an interrupt (hereinafter referred to as a trap) is generated in order to process the command, and the control is transferred to a mode for executing the original instruction of the microcomputer (hereinafter referred to as a native mode). There is a microcomputer that does.

An example of such a conventional microcomputer will be described below.

First, an example of the configuration of a conventional microcomputer, the connection between the microcomputer and an external memory, and the arrangement of programs in the external memory will be described with reference to FIGS. 11 to 13.

FIG. 11 is a block diagram showing the structure of a conventional microcomputer and the connection between the microcomputer and an external memory.

The microcomputer 1100 has an arithmetic processing unit 1101 for performing various arithmetic processes, an instruction queue 1103, and a queue bus 110 to which instruction codes are output from the instruction queue 1103.
8. Input and decode the instruction code of the queue bus 1108 and send various control signals to the arithmetic processing unit 1101 and the address bus terminal 1.
104, data bus terminal 1105 and external memory 11
17, the control unit 1102 that outputs information to the external processor 17 and inputs information from the arithmetic processing unit 1101, and the external address bus 111.
5 and an internal address bus 1106 are connected to each other, and an external data bus 1116 and an internal data bus 1107 are connected to each other. The microcomputer 1100 and the external memory 111 are connected to each other.
7 is an external address bus 1115 and an external data bus 11
It is connected through 16.

An arithmetic processing unit 1101 is an arithmetic unit 1109, a program status word (hereinafter referred to as PSW) 11 which is a 16-bit register indicating the execution status of a program.
10, a general-purpose register group 1111, a stack pointer (hereinafter referred to as SP) 1112 that is a 16-bit register that points to a pointer of a stack area, and a program that is a 16-bit counter that holds offset information of a program memory address that the microcomputer 1100 is about to execute. A counter (hereinafter referred to as a PC) 1113 is connected to each other via an internal bus 1114.

The most significant bit of the PSW 1110 is a status flag (hereinafter referred to as MD flag) indicating the mode in which the microcomputer 1100 is operating.
00 operates in the emulation mode when the MD flag is "0", and operates in the native mode when the MD flag is "1". (See FIG. 12) By the way, in a microcomputer having an emulation function, a register in a native mode is often used as it is in an emulation mode in order to prevent an increase in hardware. In such a case, since the higher-order microcomputer usually has more registers than the lower-order microcomputer, unused registers can be created in the emulation mode. For this microcomputer XR in general-purpose register group 1111
Assume that the register is an unused register.

Of the instructions in the emulation mode of the microcomputer 1100, one of the instruction codes which is trapped among the instructions whose operation is determined by the first byte and which is composed of 1 byte is "57H", which is normally executed. One of the instruction codes (hereinafter referred to as 1-byte definition instruction)
And Note that "20H" is the code of the instruction to increment the value of the X register in the general ranger group 1111.

Next, an example of program arrangement in the external memory 1117 will be shown.

FIG. 13 shows an example of program arrangement in the external memory 1117.

The external memory 117 is composed of a vector area program area, a stack area, an instruction code analysis routine, and a processing routine for each instruction.

Each area will be described below.

The vector area is an area in which the start address of interrupt processing reach due to a trap during emulation is stored, and one vector consists of 2 bytes (1 word). When an interrupt such as a trap during emulation occurs, Under the control of the control unit 1102, the contents of the vector corresponding to the interrupt factor are updated by the PC 111.
Loaded in 3. It is assumed that the vector number of the trap being emulated is set to 16 (vector address is "0020H").

The vector area is "0000H" to "00H".
It is located at address "FFH".

The program area is divided into a native mode program area and an emulation mode program area. The program area in the native mode stores a program for initializing the registers and the like necessary for executing the program in the emulation mode, and the program area in the emulation mode stores a program for a lower microcomputer to be emulated by the microcomputer 1100. It is an area that has been. In addition, the program area is from "0200H"
It is located at address "05FFH", and the program area for native mode is "0200H" to "03FFH".
The program areas in the emulation mode are arranged at addresses "0400H" to "04FFH".

The stack area is used for PS during program execution when a trap occurs during emulation.
Used for saving W and PC information. Stack area is "2000H" to "2FFEH"
It is located at the address.

In the instruction code analysis routine executed after the microcomputer 1100 causes the trap, the instruction code portion that caused the trap is recognized, and the instruction code value is used to branch to the instruction-specific processing routine. The instruction code analysis routine is "3200H" to "32".
It is located at address "FFH".

In the instruction-by-instruction processing routine, an appropriate software process performed by the user for the instruction causing the trap, a PC correction necessary for returning from the trap, and a return instruction from the trap (hereinafter referred to as a return instruction)
Is performed. The return instruction is arranged so as to be the final processing of this routine. The instruction-specific processing routines are arranged at addresses "5700H" to "57FFH".

In the program area of the emulation mode, the code "20H" of the 1-byte definition instruction is located at the address "0400H", and the instruction code "0H" is determined by the first byte and is trapped by the instruction composed of 1 byte. 57H "is arranged at the address" 0425H ".

The operation of the microcomputer 1100 will be described below with reference to FIGS. 14 and 15.

First, by resetting, the PC 1112 of the microcomputer 1100 is initialized to "0200H", the MD flag in the PSW 1110 is initialized to "1", and the microcomputer 1100 executes the program in the native mode after the address "0200H". And

In the native mode program, after the process of initializing the value of the stack pointer SP1112 used in the emulation mode program to "2FFEH", etc., the MD flag is set to "0",
"0400H" is stored in the PC 1113, and the process for fetching the instruction code at the start address of the program in emulation mode is performed.

After that, 1 in the emulation mode
The operation of the microcomputer 1100 in the case where the code "20H" of the byte definition instruction and the instruction code "57H" which is determined by the first byte and is composed of 1 byte and becomes a trap are input will be described.

[1] First, the 1-byte definition instruction code "2
The operation of the present microcomputer when processing "0H" will be described.

First of all, the control unit 1102 operates the external memory 111.
The instruction code “20H” at the address “0400H” pointed to by the PC 1113 from 7 is fetched into the instruction queue 1103, and a control signal for incrementing the value of the PC 1113 is generated.

Next, when "20H" is output from the instruction queue 1103 to the queue bus 1108 and input to the control unit 1102, the control unit 1102 causes the arithmetic processing unit 1101.
In addition, after the value of the X register is output to the internal bus 1114 and input to the arithmetic processing unit 1101, 1 is added in the arithmetic unit 1109, and the operation result is output to the internal bus 1115, and the instruction execution status of the instruction register is output to the X register again. Information to PSW1110
A control signal for performing a series of processing of storing in each is output.

[2] Next, the operation of this microcomputer for the instruction code "57H" which becomes a trap at the first byte will be described.

First, the control unit 1102 determines that the external memory 111
The instruction code "57H" at the address "0425H" pointed to by the PC 1113 from 7 is fetched into the instruction queue 1103, and a control signal for incrementing the value of the PC 1113 is generated.

Next, when "57H" is output from the instruction queue 1103 to the queue bus 1108 and is input to the control unit 1102, the control unit 1102 is the same as when the instruction code that becomes a trap at the first byte is input. Control unit 1102
A control signal for performing the processing shown in FIG. 14, that is, a control signal is output to the arithmetic processing unit 1101.

That is, the control unit 1102 causes the SP 11
The value “2FFEH” of 12 is output to the internal bus 1114 and input to the arithmetic unit 1109. Then, 2 is subtracted and the arithmetic result “2FFCH” is output to the internal bus 1114.
It controls to store in 12.

The control unit 1102 sends the value of SP 1112 to the external address bus 1115 via the internal bus 1114, the internal address bus 1106, and the address terminal 1104.
Further, the value of the SPW 1110 is output to the external data bus 1116 via the internal bus 1114, the internal data bus 1107, and the data bus terminal 1105, and the value of the PSW 1110 is controlled to be written in the address “2FFCH” of the external memory 1117.

The value “2FFCH” of PS1112 updated by the processing of 1 is output to the internal bus 1114 and input to the arithmetic unit 1109, and then subtracted by 2 to obtain the arithmetic result “2FFA”.
The control unit outputs “H” to the internal bus 1114 and stores it in the SP 1112.

The value of SP1112 is set to the internal bus 111.
4, internal address bus 1106, address bus terminal 11
It outputs to the external address bus 1115 through 04. At the same time, the PC updated to "0426H" in order to fetch the instruction code at the address next to the address "0425H"
The value of 1113 is decremented, and the start address "0425H" of the instruction causing the trap is set to the internal bus 1114,
Output to the external data bus 1116 through the internal data bus 1107 and the data bus terminal 1105, and the external memory 11
The control is performed so that the value of the PC 1113 is written in the address “2FFAH” of 17.

(By the processing of to, the stack area of the external memory 1117 becomes the state of FIG. 5.) The MD flag in the PSW 1110 is set to "1", and the native mode is changed.

The vector 16 (10H) is referenced and branched. That is, the address “0020 of the external memory 1117
The value "3200H" at address "H" is set to the external data bus 111
6, data bus terminal 1105, internal data bus 110
7. Write to the PC 1113 via the internal bus 1114, and control is performed so that the instruction code at the address "3200H" of the external memory 1117 indicated by the PC 1113 is fetched.

By the processing described above, the operation branches to the start address of the instruction code analysis routine.

The instruction code analysis routine and instruction-specific processing routine whose processing flow is shown in FIG. 15, that is, the program processing executed by the microcomputer 1100 after the trap operation will be described.

In the instruction code analysis routines (a) to (d), (1) the contents of the address "2FFAH" of the external memory 1117 pointed to by the SP 112 and updated by the above control (the start of the instruction that caused the trap) Address "0425
H ") to the XR register. (First memory read) Then, the data "57H" of the address "0425H" of the external memory 1117 indicated by the value of the XR register is transferred to the XR register. (Second memory read) (2) The value of the XR register is left shifted by 8 bits, and this is branched as the start address of the instruction-specific processing routine.

Processing is performed. Then, FIG. 15 (e)-
In the instruction-specific processing routine of (g), (3) appropriate software processing by the user corresponding to the instruction causing the trap is performed.

(4) To execute the instruction at the address next to the instruction that caused the trap due to the execution of the return instruction, which is the final processing of the instruction-specific processing routine, SP1112
Address value "2FFAH" of external memory 1117 pointed to by
, That is, the start address value “0425H” of the instruction that caused the trap is incremented.

(5) The return instruction is executed.

Processing is performed.

[0047]

In the conventional microcomputer described above, in order to branch to an appropriate software process performed by the user for each instruction causing a trap in the instruction-specific processing routine, an instruction code analysis routine is executed. Two memory accents were required for software processing to recognize the instruction code portion that caused the trap. Also,
In the microcomputer as shown in the conventional example, instructions with different byte lengths that cause a trap are often mixed. Therefore, in order to recognize the code portion that causes the trap in the instruction code that becomes the trap, in addition to the processing shown in FIGS. 15A and 15B, the instruction code stored in the working XR register However, software processing is required to determine whether or not it matches the instruction code part that becomes a trap. At this time, when the instruction code group to be trapped is arranged in the memory, the instruction to be trapped at the first byte has the above-mentioned two times of memory access, and the instruction code and trap at the first byte read into the XR register. The same number of times as the number of times the instruction code table (not shown in FIG. 13) is referred to for comparison with the instruction code that becomes Memory access is required three times.

If there is no matching instruction code in the first byte, memory access is required once to read the second byte instruction code from the external memory, and the read instruction code is the second byte. In order to compare with the instruction code that becomes a trap, the memory access is required at least once when referring to the instruction code table that causes the trap. If the above "at least 3 times" is added, a total of 5 times is required. Memory access is required.

As described above, there is a problem that the memory access in the instruction code analysis routine increases as the number of instruction codes having different byte lengths of trap instructions increases.

[0050]

A microcomputer of the present invention has an emulation function, and when a predetermined instruction code is input during execution of emulation, the predetermined instruction code or a part thereof is stored in a predetermined register, It has a control means for generating an interrupt.

Furthermore, the microcomputer of the present invention has an emulation function, and when a predetermined instruction code is input during execution of emulation, the first byte of the predetermined instruction code to the instruction code portion which can be recognized as an interrupt operation instruction. It has a control means for storing a value indicating the code length in a predetermined register and generating an interrupt.

[0052]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As described in the section of the conventional example, in a microcomputer for emulation, a register in native mode is often used as it is in emulation mode in order to prevent an increase in hardware. In this case, since the higher-order microcomputer usually has more registers than the lower-order microcomputer, unused registers are often created in the emulation mode.

In this embodiment, a microcomputer that stores an instruction code that causes a trap in an unused general-purpose register will be described.

First, the structure of the microcomputer of this embodiment, the connection between the microcomputer and the memory, and the program layout in the external memory will be described with reference to FIGS.

FIG. 1 is a block diagram showing the structure of the microcomputer of the present invention and the connection between the microcomputer and an external memory.

The microcomputer 100 has an arithmetic processing unit 101 for performing various arithmetic processing, an instruction queue 103, and an instruction queue 103.
The instruction code is output from the queue bus 108, the instruction code on the queue bus 108 is input and decoded, and various control signals are output to the arithmetic processing unit 101, the address bus terminal 104, the data bus terminal 105, and the external memory 117. And a control unit 102 for inputting information from the arithmetic processing unit 101, an address bus terminal 104 connecting the external address bus 116 and the internal address bus 106, and a data bus connecting the external data bus 117 and the internal data bus 107. It is composed of the terminal 105.

The arithmetic processing unit 101 includes an arithmetic unit 109 and a PSW.
110, general-purpose register group 111, stack pointer SP
112 and a program counter PC 113 are connected to each other via an internal bus 114. In addition, the microcomputer 10
0 and the external memory 117 are connected via an external address bus 115 and an external data bus 116.

The most significant bit of the PSW 110 is a status flag (hereinafter referred to as MD flag) indicating the mode in which the microcomputer 100 is operating, and the microcomputer 100 emulates the mode when the MD flag is "0".
When it is "1", it shall operate in the native mode.
(See FIG. 2) Further, in the case of this microcomputer, it is assumed that the XR register in the general-purpose register 111 is an unused register.

In the emulation mode instruction of the microcomputer 100, the operation is determined by the first byte and
Among the instructions composed of bytes, one of the trapping instruction codes is "57H" and one of the byte defining instruction codes is "20H". Note that "20H" is a code of an instruction to increment the value of the X register in the general register group 111.

Next, an example of program arrangement in the external memory 117 is shown.

FIG. 3 shows an example of program arrangement in the external memory 117.

The external memory 117 has a vector area.
Program area Stack area This consists of instruction code analysis routines and instruction-specific processing routines.

Each area will be described below.

The vector area is an area in which an interrupt processing routine start address due to a trap during emulation is stored, and one vector is composed of 2 bytes (1 word). When an interrupt such as a trap during emulation occurs, control is performed. By the control of the part 1202,
The contents of the vector corresponding to the interrupt factor are loaded into the PC 113. It is assumed that the vector number of the trap being emulated is set to 16 (vector address is "0020H").

The vector area is "0000H"-"0H".
It is located at address "0FFH".

The program area is divided into a native mode program area and an emulation mode program area. The program area in the native mode stores a program for initializing the registers and the like necessary to execute the program in the emulation mode, and the program area in the emulation mode stores a program for a lower microcomputer to be emulated by the microcomputer 100. It is an area that has been. The program area is from "0200H" to "0
The program area of the emulation mode is arranged at the address "3FFH" to the addresses "0400H" to "05FFH".

The stack area is a PC that is executing a program when a trap occurs during emulation.
Used for saving W and PC information. Stack area is "2000H" to "2FFEH"
It is located at the address.

In the instruction code analysis routine that is executed after the microcomputer 100 causes the trap, the instruction code portion that caused the trap is recognized, and the instruction code value is used to branch to the instruction-specific processing routine.
The instruction code analysis routine is "3200H" to "32FF
It is located at address "H".

In the instruction-specific processing routine, appropriate software processing performed by the user for the instruction that caused the trap, PC correction necessary for returning from the trap, and a return instruction from the trap (hereinafter referred to as a return instruction)
Is performed. The return instruction is arranged so as to be the final processing of this routine. The instruction-specific processing routines are arranged at addresses "5700H" to "57FFH".

In the program area of the emulation mode, the code "20H" of the 1-byte definition instruction is located at the address "0400H", and the code of the instruction which becomes a trap when the operation is determined by the first byte and is composed of 1 byte. "57H" is arranged at the address "0425H".

Next, the operation of the microcomputer 100 will be described with reference to FIGS. 4 to 7.

First, by resetting, the P of the microcomputer 100 is
The C113 is initialized to "0200H", the MD flag in the PSW 110 is initialized to "1", and the microcomputer 100 is initialized to "020H".
It is assumed that the native mode program after the address "0H" is executed.

In the native mode program, after the process of initializing the value of the stack pointer SP112 used in the emulation mode program to "2FFEH", etc., the MD flag is set to "0" and P
"0400H" is stored in C113, and the processing for fetching the instruction code at the start address of the program in the emulation mode is performed.

The operation of the microcomputer 100 when the instruction operation is determined by the first byte and the instruction code that becomes the trap among the instructions formed by the first byte is input will be described.

[1] First, the 1-byte definition instruction code "2
The operation of the present microcomputer when processing "0H" will be described.

First, the control unit 102 fetches the instruction code "20H" at the address "0400H" pointed to by the PC 113 from the external memory 117 into the instruction queue 103, and the PC
A control signal for incrementing the value of 113 is generated.

Next, when “20H” is output from the instruction queue 103 to the queue bus 108 and input to the control unit 102, the control unit 102 sends X to the arithmetic processing unit 101.
After selecting a register and outputting the value to the internal bus 114 and inputting it to the arithmetic processing unit 101, 1 is added in the arithmetic unit 109. Then, the calculation result is output to the internal bus 114 and X is again output.
Information on the instruction execution status is stored in the registers in the PSW 110.

[2] Next, the operation of the microcomputer for the instruction code "57H" which becomes a trap at the first byte will be described.

First, the control unit 102 fetches the instruction code “57H” at the address “0425H” pointed to by the PC 113 from the external memory 117 into the instruction queue 103, and
A control signal for incrementing the value of 113 is generated.

Next, when "57H" is output from the instruction queue 103 to the queue bus 108 and input to the control unit 102, the control unit 102 first sends to the arithmetic processing unit 101 a control signal for performing the processing shown in FIG. Output to.

The control unit 102 controls the SP 112 value “2F
It outputs "FEH" to the internal bus 114, inputs it to the arithmetic unit 109, subtracts 2 and outputs "2FFCH" of the arithmetic result to the internal bus 114, and stores it in the SP 112.

The control unit 102 transfers the value of SP 112 to the external address bus 115 through the internal bus 114, the internal address bus 106, and the address bus terminal 104, and P
The value of SW110 is set to the internal bus 114 and the internal data bus 10.
7. External data bus 11 through data bus terminal 105
6, and outputs to the external data bus 116 through the internal data bus 107 and the data bus terminal 105, respectively, and controls to write the value of the PSW 110 to the address “2FFCH” of the external memory 117.

The value “2FFCH” of the SP 112 updated in the processing of 1 is output to the internal bus 114, and the arithmetic unit 1
After being input to 09, it subtracts 2 and outputs "2FFAH" of the calculation result to the internal bus 114 and controls it to be stored in SP112.

The value of SP 112 is output to the external address bus 115 through the internal bus 114, the internal address bus 106, and the address bus terminal 104. Next, "042
The value of the PC 113 updated to "0426H" for fetching the instruction code at the address next to the address "5H" is decremented, and the start address "0425" of the trap instruction is decremented.
"H" is output to the external data bus 116 through the internal bus 115, the internal data bus 107, and the data bus terminal 105, respectively, and the address "2FFAH" of the external memory 118 is output.
The value of the PC 113 is controlled to be written in.

The code “57” on the cue bus 108
"H" is output to the internal bus 114 and written to the lower side of the XR register.

(By the processes up to, the stack area of the external memory 117 becomes the state shown in FIG. 5.) The MD flag is set to "1" and the mode is changed to the native mode.

The process branches with reference to the vector 16 (10H). That is, the address “0020 of the external memory 117
The value “3200H” at the address “H” is set to the external data bus 116,
The instruction is stored in the PC 113 through the data bus terminal 105, the internal data bus 107, and the internal bus 114, and the instruction code at the address “3200H” of the external memory 117 designated by the PC 113 is fetched.

By the processing described above, the operation branches to the start address of the instruction code analysis routine.

Next, the instruction code analysis routine and the instruction-specific processing routine shown in FIGS. 6A to 6E, that is, the program processing executed by the microcomputer 100 after the trap operation will be described.

First, in the instruction code analysis routine, the software processing of FIGS. 6A and 6B, that is, (1) the value of the XR register is left-shifted by 8 bits, and this is separated as the start address of the instruction-specific processing routine. Perform processing.

Next, the processing of the instruction-specific processing routine shown in FIGS. 6C to 6E, that is, (2) appropriate software processing by the user corresponding to the instruction causing the trap is performed.

(3) The address value "2FFAH" of the external memory 117 pointed to by the SP 112 in order to execute the instruction at the address next to the instruction that caused the trap due to the execution of the return instruction, which is the final processing of the instruction-specific processing routine. , That is, the start address value “0425H” of the instruction that caused the trap is incremented.

(4) Execute a return instruction.

Regarding the instruction which is determined by the second byte and which is trapped at the second byte in the instruction composed of two bytes, the operation of the instruction is not decided by the first byte. Read
When the instruction code of the second byte is input to the control unit 102, it becomes a trap, and thereafter, the same processing as that of the instruction which becomes the trap at the first byte is performed.

That is, the XR register contains the instruction code 2
The byte is stored.

In this embodiment, the instruction code is stored in the unused general-purpose register. However, if an unused register cannot be created during emulation, a means for adding a dedicated register can be considered.

The microcomputer of this embodiment is effective when all instruction code parts that can be determined to cause a trap have different values, but even if they match, an interrupt vector is generated depending on the type of byte position causing a trap. This can be easily implemented by separately setting and setting a different instruction code analysis routine.

As a second embodiment, a microcomputer for storing a value representing the code length from the first byte of the instruction that caused the trap to the instruction code portion that can be recognized as causing the trap in an unused general-purpose register will be described.

FIG. 7 is a block diagram of a microcomputer according to the second embodiment of the present invention and a connection diagram between the microcomputer and an external memory. The microcomputer 700 is different from the microcomputer of the first embodiment in that it can be recognized that the control unit 701 causes the constant generation circuit 702 (not explicitly shown in the microcomputer of the first embodiment) to generate a trap from the first byte of the instruction. The control is to generate a value representing the code length up to the instruction code part and output the value to the internal bus 114.

In the microcomputer 700, one of the codes of the 1-byte definition instruction is "20H" and one of the instruction codes trapped at the first byte is "57H", which is the same as the first embodiment, but other than that. The instruction code is determined by the nth byte (n is an integer of 2 or more), and the instruction code "9FH""40H" configured by 3 bytes is one of the instructions that are trapped in the instruction configured by n bytes. "7
5H ”.

FIG. 8 shows the external memory 117 in this embodiment.
It is a program layout diagram in the inside, and is from "7500H"
The instruction-specific processing routine 2 at the address "75FFH" is set to the instruction-specific processing routine with the instruction codes "9FH", "40H", and "75H", and the instruction codes "9FH" and "4".
0H "and" 75H "from" 0580H "to" 0582 "
The program layout is the same as that of the external memory 117 in the first embodiment except that it is located at the address "H".

The operation of the microcomputer of this embodiment will be described below.

The control of the control unit 701 when the microcomputer 700 processes the native mode program and the code "20H" of the 1-byte definition instruction is the same as that of the first embodiment.

Next, the microcomputer 700 fetches the instruction code "57H" which becomes a trap at the first byte from the external memory 117 into the instruction queue 103, and the instruction code "57H".
Is output from the instruction queue 103 to the queue bus 108 and input to the control unit 701, first, a control signal for performing the processing of FIG. 9A, that is, the processing similar to FIG. 4A and FIG. It is output to the unit 101.

Next, the control section 701 outputs a control signal for performing the processing shown in FIG. 9 (b). That is, the first instruction that causes a trap in the constant generation circuit 702.
The value "0000H" representing the code length from the byte to the instruction code part that can be recognized as causing a trap is set to the internal bus 11
The output is controlled to 4.

The XR register in the general-purpose register group 111 is controlled to store the value “0000H” on the internal bus 114.

Next, the processing shown in FIG. 9C, that is, FIG.
The same processing as in (d) and (c) is executed to branch to the start address of the instruction code analysis routine.

The instruction code analysis routine and instruction-specific processing routine shown in FIG. 10, that is, the program processing executed by the microcomputer 700 after the trap operation will be described.

In the instruction code analysis routine (1) SP updated by the processing shown in FIG.
External memory 117 indicated by the value “2FFAH” of 112
The address content "0425H" and the value "0000H" in the XR register are added and the result is stored in the XR register. (First memory read) (2) The content "57H" of the address of the external memory 117 indicated by the value "0425H" of the XR register is stored in the XR register. (Second memory read) (3) The value of XR is left-shifted by 8 bits, and this is branched as the start address of the instruction-specific processing routine 1.

FIG. 9C shows the processing in the instruction-specific processing routine 1, which performs the same software processing as the instruction-specific processing routine in the microcomputer of the first embodiment.

When the microcomputer 800 processes the instruction code "9FH""40H""75H" which becomes a trap at the third byte, the same processing as that of the instruction code "57H" is performed except that the following points are different. I do.

“0002H” is stored in the XR register.

In the instruction-specific processing routine 2, “0
"002H" is added to the contents of the memory pointed to by SP.

The microcomputer of this embodiment is also effective in the case where the values of the instruction code portion that can be recognized as causing a trap do not match, but even if these values match, the first byte of the instruction code causing a trap Can be easily implemented by separately setting an interrupt vector according to the type of byte length from the to the instruction code part that can be recognized when a trap is generated and setting a different instruction code analysis routine.

[0115]

As described above, in the case of the microcomputer that stores the instruction code that caused the trap, the first byte is used to recognize the instruction code portion that caused the trap, as in the conventional microcomputer. The instruction code part stores the instruction code in a predetermined register as compared with the case where the memory access is required at least 3 times in the case of the instruction which becomes the second instruction and at least 5 times in the case of the instruction which becomes the trap in the second byte. Does not require any memory access to recognize. In the case of a microcomputer that stores the code length value from the beginning of the instruction that caused the trap to the instruction code portion that caused the trap, a memory for recognizing the instruction code portion regardless of the byte position of the instruction code that causes the trap. Access is only twice. Therefore, there is an effect that the processing in the instruction code analysis routine can be speeded up.

A method of storing the value of the instruction code portion that causes a trap in a predetermined register and a value representing the code length from the first byte of the instruction that causes a trap to the instruction code portion that can be recognized as causing a trap are predetermined. It is also possible to mix the method of storing in the register. For example, in the case of an instruction that becomes a trap at the 1st byte and an instruction that becomes a trap at the 2nd byte, if the value of the instruction code part that causes the trap is generated, and if it is an undefined instruction, the trap is generated from the first byte of the instruction that causes the trap. Control is performed to store a value representing a code length up to a recognizable instruction code part in a predetermined register. In this case, the first instruction that causes a trap
Which of the two is the value in the instruction code analysis routine when the value indicating the code length from the byte to the instruction code part that can be recognized as causing a trap matches the instruction code that becomes the trap at the first and second bytes. If is not recognized, take a simple action such as setting the trap vector separately for the instruction that becomes a trap at the 1st byte and the instruction that becomes a trap at the 2nd byte, and for the undefined instruction. Good. Thus, the application effect of the present invention is great.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a microcomputer and a connection between a microcomputer and an external memory in a first embodiment of the present invention.

FIG. 2 is a bit configuration diagram of a PSW in the embodiment.

FIG. 3 is a program layout diagram of an external memory in the embodiment.

FIG. 4 shows an instruction code “57” in the microcomputer of the embodiment.
It is a control flow of a control part when "H" is input.

FIG. 5 is a state diagram of a stack area by the processing shown in FIG.

FIG. 6 is a processing flow of an instruction code analysis routine and an instruction-specific processing routine of the microcomputer of the embodiment.

FIG. 7 is a block diagram showing a configuration of a microcomputer according to a second embodiment of the present invention and a connection between the microcomputer and an external memory.

FIG. 8 is a program layout diagram of an external memory in the embodiment.

FIG. 9 is a control flow of the control unit when the microcomputer of the embodiment processes the instruction code “57H”.

FIG. 10 is a processing flow of an instruction code analysis routine and an instruction-specific processing routine 1 of the microcomputer of the embodiment.

FIG. 11 is a block diagram showing a configuration of a conventional microcomputer and a connection between the microcomputer and an external memory.

FIG. 12 is a bit configuration diagram of PSW.

FIG. 13 is a program layout diagram of an external memory.

FIG. 14 is a control flow of a control unit when a conventional microcomputer processes an instruction code “57H”.

FIG. 15 is a processing flow of a conventional microcomputer instruction code analysis routine and instruction-specific processing routine.

[Explanation of symbols]

 100 microcomputer 101 arithmetic processing unit 102 control unit 103 instruction queue 104 address bus terminal 105 data bus terminal 106 internal address bus 107 internal data bus 108 queue bus 109 arithmetic unit 110 PSW 111 general-purpose register group 112 SP 113 PC 114 internal bus 115 external address Bus 116 External data bus 117 External memory 700 Microcomputer 701 Control unit 702 Constant generation circuit 1100 Microcomputer 1101 Arithmetic processing unit 1102 Control unit 1103 Instruction queue 1104 Address bus terminal 1105 Data bus terminal 1106 Internal address bus 1107 Internal data bus 1108 Queue bus 1109 Operation Part 1110 PSW 1111 General-purpose register group 1112 SP 1113 PC 1114 Internal bus 1115 External adapter Dress bus 1116 External data bus 1117 External memory

Claims (1)

[Claims] 1. In a microcomputer having an emulation function, when a predetermined instruction code is input during execution of the emulation, a code length from a first byte of the predetermined instruction code to an instruction code which can be recognized as an interrupt operation instruction. A microcomputer characterized by including control means for storing an indicated value in a predetermined register and generating an interrupt.