JP2002157115A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a means of improving the usability of a data processor such as a microcomputer, reducing program capacity, and cutting down the number of execution states, while minimizing an increase in its logical scale. SOLUTION: In this data processor, a return command from a sub-routine, or from exception handling, has a command code including information for assigning a plurality of general-purpose registers. When the command code is executed, the assigned registers are returned in addition to the resetting of a program counter. Further, the combination of assigned registers is made to be serial. An evacuation command allowing similar assignment is enabled for the registers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus, and more particularly to a microcomputer including a semiconductor integrated circuit device, a central processing unit (CPU), and a data processing system using the same. Further, the present invention relates to a technology effective for use in the development device.

[0002]

2. Description of the Related Art With the advancement of manufacturing technology of semiconductor integrated circuit devices, a central processing unit (Central Processing Unit) is mounted on a single chip made of a semiconductor single crystal.
g Unit; hereinafter, simply referred to as CPU), ROM (Read Only Memory) for storing programs
y), a RAM (R
2. Description of the Related Art Microcomputers, which are manufactured by integrating constituent elements including an Random Access Memory, etc., have become widespread and have been used as data processing apparatuses for various purposes. The performance of this microcomputer varies depending on the amount of information that can be simultaneously processed by the CPU.
Bits are classified as microcomputers.

In such a microcomputer, an address space is expanded, an instruction set is expanded, a speed is increased, and the like. Further, since the performance of the CPU is defined by software, even in a microcomputer in which the address space is expanded, the instruction set is expanded, and the speed is increased as described above, the software resources of the existing microcomputer are used. It is desirable that it can be used effectively.

For this reason, while maintaining compatibility at the object level, expansion of the address space, expansion of the instruction set,
For example, Japanese Patent Application Laid-Open No. 6-51981 previously proposed by the inventor of the present invention has realized an example in which the speed is increased. This is 16
A variable-length instruction in bit units, a so-called general-purpose register type.
Alternatively, it is shown that a load store type architecture is adopted.

In the case of a single-chip type having a built-in ROM serving as a program memory, a built-in ROM
Is smaller than when a memory is connected externally, it is desirable to reduce the program capacity.

When a 16-bit variable length instruction is employed, the return (RTS) is used as a meaningful instruction that has only an operation code and does not specify an effective address.
/ RTE) instruction. When such a return instruction is assigned to a 16-bit instruction, all bits of the 16-bit instruction code are often not used.

For example, an instruction code H'5470 is a return instruction from a subroutine, and H'5471, H'5
In the case where 472 and H'5473 are undefined (not defined as another instruction), bit 0 and bit 1 are not used.

On the other hand, Japanese Patent Laid-Open No.
The CPU described in JP-263290A fixes a combination of a plurality of general-purpose registers that can be specified to a control unit that controls an execution unit that executes an instruction, and has a save / restore instruction for a stack of a plurality of general-purpose registers. A plurality of general-purpose registers are sequentially saved / restored. By fixing the combination of general-purpose registers, the number of bits required for specifying the general-purpose registers can be saved.

The save / restore instruction is used for the purpose of preserving the state of previous processing at a break in processing such as a subroutine or exception processing, and the addressing mode is used for pre-decrement (save) / post of the stack pointer. Can be used for increment (return).

That is, the return instruction of the general-purpose register is often placed before the return instruction (RTS / RTE) from the subroutine or the exception processing.

In a CPU having a so-called accumulator type architecture, when branching to a subroutine or returning from a subroutine, the accumulator may be saved / restored in addition to the PC. This is because data processing is performed on a small number of accumulators, and when processing changes as in a subroutine, the accumulator must be opened. In other words, automatically saving / restoring the accumulator will not be wasted.

On the other hand, a general-purpose register-type architecture CPU has a high degree of freedom as to which of the general-purpose registers data is to be stored, and the argument at the time of branching to the subroutine / returning from the subroutine is general-purpose. It may be assigned to a register. For this reason, if saving / restoring of a predetermined (all or a part) general-purpose register is automatically performed, it tends to be useless. This is because the number of execution states and the amount of stack usage increase due to the undesired saving / restoring of general-purpose registers.

Microcomputer programs are often described in C language. Functions frequently used in the C language are implemented as subroutines.

[0014]

The problem to be solved by the present invention is to improve the usability and reduce the program capacity while minimizing the increase in the logical scale of a data processing device such as a microcomputer. And means for reducing the number of execution states.

Particularly, in a program using the C language or the like, the program capacity can be reduced when many functions are used.
The purpose is to reduce the number of execution states.

In addition, the existing software resources can be effectively used, the development efficiency of the user can be improved, and the development equipment can be commonly used to improve the development efficiency of the development equipment. It is possible to provide.

The above and other objects and novel features of the present invention will become apparent from the description of the present invention and the accompanying drawings.

[0018]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

According to the data processing device of the present invention, in a return instruction from a subroutine or from exception processing, the instruction code includes information designating a plurality of general-purpose registers,
When the instruction code is executed, the designated general-purpose register is restored in addition to the program counter.

Further, the combination of designated general-purpose registers is made continuous.

It is possible to execute a general-purpose register save instruction which enables the same designation.

According to the above-described means, the return instruction from the subroutine or from the exception processing and the return instruction of the general-purpose register are the same instruction (for example, 16 bits), so that the usability is improved and the program capacity is reduced. it can.

Even in the case of using a variable-length instruction code system in 16-bit units, the overall program efficiency can be improved by effectively using instruction codes while simplifying instruction prefetching and instruction decoding.

A general-purpose register save instruction enabling the same designation is executed at the beginning of a subroutine or an exception handling routine, and finally, the return instruction of the present invention is executed, thereby further improving usability. Can be improved.

By fixing the combination of designated general-purpose registers, information for designating general-purpose registers can be shortened, and even a limited instruction code (for example, 16 bits) can be designated.

The continuous operation of the general-purpose registers and the return of the program counter and the like facilitates the internal operation and speeds up the operation.

[0027]

FIG. 1 is a block diagram of a microcomputer to which the present invention is applied.

The microcomputer is a single-chip microcomputer, a CPU for controlling the entire system, an interrupt controller (INT), a ROM for storing a processing program of the CPU, a work area of the CPU, and a memory for temporarily storing data. And a RAM that can be used as a stack memory, a timer, a serial communication interface (SCI), an A / D converter, first to ninth input / output ports (IOP1 to IOP9), and a clock oscillator (CP).
G) is composed of functional blocks or modules, and is formed on one semiconductor substrate by a known semiconductor manufacturing technique.

Such a microcomputer has power supply terminals such as a ground level (Vss), a power supply voltage level (Vcc), an analog ground level (AVss), an analog power supply voltage level (AVcc), an analog reference voltage (Vref), and others. Reset (R
ES), standby (STBY), mode control (MD
0, MD1), clock input (EXTAL, XTAL)
Has terminals.

The microcomputer operates in synchronization with a crystal oscillator connected to the terminals EXTAL and XTAL of the CPG or a reference clock (system clock) generated based on an external clock input to the EXTAL terminal. One cycle of this reference clock is called a state.

The functional blocks of the microcomputer are as follows:
Interconnected by internal bus. Control the bus,
A bus controller (not shown) is incorporated. Internal buses include address buses, data buses, read signals,
Includes a write signal and a bus size signal, which are coded as bus commands.

These functional blocks and modules are read / written by the CPU via the internal bus. The data bus width of the internal bus is 32 bits. Built-in RO
M, RAM read / write is enabled in one state.

Timer, SCI, A / D converter, IOP1
The control registers included in .about.IOP9, SYSC, INT, CPG and the like are collectively referred to as internal I / O registers.

Each input / output port is also used as an input / output terminal of an address bus, a data bus, a bus control signal or a timer, an SCI, and an A / D converter. That is, timer, SC
The I and A / D converters have input / output signals, respectively, and are input / output to / from the outside via terminals shared with input / output ports. For example, IOPs 5 and 6 are also used as input / output terminals of the timer, and IOP 7 is also used as an input / output terminal of the SCI. Analog data input / output (AIN0-AIN
7) The terminal is also used as IOP8.

The external interrupt input is also used for IOP9.

When a reset signal RES is supplied to the microcomputer, the microcomputer including the CPU is reset. When this reset is released, the operation mode is set to the operation mode specified by the mode control (single chip, external bus expansion, built-in ROM enabled, etc.), and the CPU reads the start address from a predetermined address (vector address). Performs reset exception processing to start reading instructions from the start address. Thereafter, the CPU sequentially reads instructions from the ROM or the like,
Based on the decrypted contents, it performs data processing including determination and manipulation of flags and bits, or data transfer with RAM, timer, SCI, A / D converter, input / output port, and the like. That is, the CPU has a timer, SCI, A /
While referring to data input from a D converter, an input / output port, or the state or instruction (switch, volume, etc.) of the device, processing is performed based on an instruction stored in a ROM or the like, and processing is performed based on the result. , Input / output ports, timers, etc., and output signals to the outside to control devices.

The interrupt controller (INT) receives each interrupt signal of a timer, an SCI, an A / D converter, and an external input, and outputs an interrupt request signal to the CPU.

When an interrupt request signal is given to the CPU, C
The PU interrupts the processing being executed, branches to a predetermined processing routine via an interrupt exception processing state, performs desired processing, and clears an interrupt factor. At the end of the predetermined processing routine, a normal return instruction is placed, and the interrupted processing is resumed by executing this instruction.

At the time of executing the interrupt exception processing, a program counter (PC) and a condition code register (CCR), which will be described later, are saved in a RAM or the like. When the return instruction is executed, the program counter (PC), the condition code register (CCR), etc. Is restored.

Furthermore, in order to perform required processing in the interrupt processing routine, it is necessary to use general-purpose registers. At the beginning of the interrupt processing routine, necessary general-purpose registers are saved on the stack in order to save the state immediately before the occurrence of the interrupt.
This is described, for example, as STM ER0-ER3, ＠ -SP. At the end of the interrupt processing routine, after restoring the saved general-purpose register, a return instruction (RTE) is executed to continue the program immediately before the interrupt occurred. This is described in the related art as, for example, LDM @ SP +, ER0-ER3 RTE.

According to the present invention, the above LDM and RTE instructions are executed by one instruction, and may be described as RTE / 4 ER0-ER3.

Similarly, in the subroutine,
Use general purpose registers to perform the required processing. For example, at the beginning of the subroutine, STM ER0-ER1, ＠ -SP is described, and finally, LDM ＠ SP +, ER0-ER1 RTS is described.

According to the present invention, the LDM and RTE instructions are executed by one instruction, and can be described as RTS / 2 ER0-ER1.

FIG. 2 shows a configuration example (programming model) of general-purpose registers and control registers built in the CPU.

The CPU has eight 32-bit general-purpose registers. All general-purpose registers have the same function, and can be used as both an address register and a data register.

As a data register, 32 bits, 16 bits
Can be used as bit and 8-bit registers. The address register and the 32-bit register are collectively used as general-purpose registers ER (ER0 to ER7). 1
As the 6-bit register, the general-purpose register ER is divided into general-purpose registers E (E0 to E7) and a general-purpose register R (R
0 to R7). These have the same function, and up to 16 16-bit registers can be used. Note that the general-purpose registers E (E0 to E7) are
Particularly, it may be called an extension register. As an 8-bit register, the general-purpose register R is divided into general-purpose registers RH.
(R0H to R7H), general-purpose register RL (R0L to R7)
L). These have equivalent functions and can use up to 16 8-bit registers. The method of use can be selected independently for each register.

The general-purpose register ER7 is assigned a function as a stack pointer (SP) in addition to the function as the general-purpose register, and is used implicitly in exception processing and subroutine branching. The exception processing includes the interrupt processing.

PC is a 24-bit counter, which indicates the address of an instruction to be executed next by the CPU. Although not particularly limited, all instructions of the CPU are in units of 2 bytes (words), so the least significant bit is invalid, and the least significant bit is regarded as 0 when reading the instruction.

The CCR is an 8-bit register and includes an interrupt mask bit (I), a half carry (H), a negative (N), a zero (Z), an overflow (V), and a carry (C) flag. Each flag of half carry (H), negative (N), zero (Z), overflow (V), and carry (C) inspects data at the time of executing a transfer instruction or an operation instruction and reflects the state. Half carry (H) is used only for decimal correction.

FIG. 3 shows a configuration example of the CPU.

The CPU comprises: a control unit;
It comprises an execution unit including R0 to ER31, a program counter PC, and a condition code register CCR.

The control section includes an instruction register IR1, an instruction decoder DEC, a register selector RDEC, and an interrupt receiving circuit INT. The instruction decoder DEC is, for example, a micro ROM or a PLA (Programmable L
Logic or wired logic.
Part of the output of the instruction decoder DEC is the instruction decoder DEC.
Feedback. This includes a stage code (TMG) used for transition within each instruction code, and a control signal (MOD) used between instruction codes. That is, the ST
The first word of the M instruction generates a control signal designating the number of general-purpose registers, outputs an interrupt mask signal, and inhibits acceptance of an interrupt.

The interrupt controller INT receives an interrupt request signal output from an interrupt controller shown in FIG. 1 described later. Also, referring to the interrupt mask signal output by the instruction decoder, if the interrupt is not masked, the instruction change unit CHG is instructed to execute an interrupt, and the instruction code for interrupt exception processing is executed.

The execution unit further includes a temporary register T
R, arithmetic logic unit ALU, incrementer INC, read data buffer DBR, write data buffer DB
W, including an address buffer AB. These blocks are interconnected by a GB bus, a DB bus, and a WB bus.

The arithmetic and logic unit ALU uses various operations specified by instructions and calculation of effective addresses.

The incrementer INC is mainly used for adding PCs and calculating addresses.

The DBR temporarily stores instruction codes and data read from a ROM, a RAM, an internal I / O register, or an external memory (not shown). The DBW temporarily stores write data to a ROM, a RAM, an internal I / O register, or an external memory. DBR, DB
The timing of the internal operation of the CPU and the read / write operation outside the CPU is adjusted by W.

The address buffer AB temporarily stores an address to be read / written by the CPU.

FIG. 4 is a detailed block diagram of a part of the register selector RDEC.

The register decoder RDEC receives the register field information output from the IR 1 holding the register field and the control signal output of the instruction decoder DEC, and generates a register selection signal corresponding to each general-purpose register.

There are two register designation fields (r
1, r2).

Second register specification field (r2)
Is generated from bits 3 to 0 of IR1 and the control signal output (inc, dec) of the instruction decoder.

The incrementer (RIN
The output of C) is latched at the inverted φ # of the system clock, and becomes the second register designation field (r2).

For example, in the case of STM ER0-ER3, ＠ -SP, 0 is given as an initial value of r2. Thereafter, at a predetermined timing described later, r2 is changed from 0 → 1 → 2 → 3 by the increment signal (inc).

In the case of LDM ， SP +, ER0-ER1 or RTS / 2 ER0-ER1, 1 is given as an initial value of r2. Thereafter, at a predetermined timing described later, r2 is changed from 1 to 0 by an increment signal (dec = rd--).

As a result, sharing the register selection circuit itself with other instructions can suppress an increase in logical scale.

Since bit 3 of r2 is not used in these instructions, the incrementer (RINC) may be 3 bits. By having an incrementer (RINC)
It is possible to specify any combination of consecutive general-purpose registers without increasing the logical scale.

The details of the other RDEC are omitted.

FIG. 5 shows a first return instruction (RTS / n) including a return of a plurality of general-purpose registers and a second return instruction (RTE / RTE).
/ N).

The first return instruction (RTS / n) is a return instruction from a subroutine, and the first return instruction (RTE / RTS)
/ N) is a return instruction from the exception handling routine.

Bits 15 to 7 are an operation field for designating a return instruction.

When bit 6 is 0, bits 5 and 4 specify the number of general purpose registers. 2 when 01
In the case of 10, the number is set to 3 and in the case of 11, the number is set to 4. For selection of general-purpose registers, continuous selection of 2, 3, and 4 registers is possible. For example, in the case of four, ER0-3, ER1
-4, ER2-5, and ER3-6 can be specified. E
R7 is also used as a stack pointer and is not targeted.

When the bit 6 is 1, the general-purpose register is not restored. That is, it is the same as the return instruction of the prior art, and has a common instruction code (H'5470).

Bits 3 to 0 specify a general-purpose register to be used first. Bit 3 shall be reserved and 0
And

For example, in the case of RTS / 4 ER0-3, since it returns from ER3, the instruction code is H'5433.

The second return instruction (RTE / n) is similar to the above except that the operation field is different.

The instruction format of the STM instruction is a two-word instruction, and the bits 3 to 0 of the second word specify the general-purpose register to be used first. This is shared with the return instruction.

The same applies to the instruction format of the LDM instruction.

FIG. 6 shows a first return instruction (RTS / n) including a return of a plurality of general-purpose registers and a second return instruction (RTE / RTE).
/ N) shows an example of a stack configuration.

The stack is a stack pointer (SP: ER
7) indicates the last address of the stack.

The program counter is saved on the stack by a subroutine branch instruction (for example, a BSR instruction). Thereafter, at the beginning of the subroutine, required general-purpose registers are saved (for example, STM ER0-ER1,
＠ -SP).

In response to this, the first return instruction (for example, RTS / 2 ER0-ER1) first reads from the stack to return the specified general-purpose register, and returns to the specified general-purpose register (ER1, ER0). Subsequently, as the return of the program counter, the read from the stack is performed, the result is stored in the program counter, and the instruction is read according to the contents.

Similarly, the program counter and the condition code register are saved on the stack by the exception processing. The program counter is 24 bits and is saved on the stack in combination with the condition code register. Then, at the beginning of the subroutine, the required general purpose registers are saved (for example, STM ER0-ER
3, ＠ -SP).

In response to this, the second return instruction (for example, RTE / 4 ER0-ER3) first reads from the stack to return the specified general-purpose register, and returns to the specified general-purpose register (ER3, ER3, ER3). ER2, ER1,
ER0). Subsequently, as the return of the program counter and the condition code register, reading from the stack is performed, predetermined contents are stored in the program counter and the condition code register, and an instruction is read.

FIG. 7 shows an operation flow of the first return instruction (RTS / n).

In step 1, the contents of the stack pointer (SP) are output to the address bus (IAB) by the control signal A, and a long word read is instructed. Also, SP
Is incremented (+4). The control signal C instructs storage of the read data in the DBR.

In steps 2 to 5, the control signal B instructs the general-purpose register to write the contents read in the previous step. Specifically, output to the internal bus GB once,
The signal is output to the internal bus WB via the ALU and written to the designated general-purpose register. Register decoder RDEC
Is decremented (-1) in the register field. Similarly to the above, the control signal A instructs the output of the contents of the stack pointer (SP) to the address bus (IAB), the reading of the long word, and the increment (+4) of the contents of the SP. The control signal C instructs storage of the read data in the DBR. Steps 2 to 4 are executed a predetermined number of times according to the specified number (n) of general-purpose registers.

In step 6, the control signal B instructs the program counter (PC) to write the contents read in the previous step.

At step 7, the contents of the program counter (PC) are output to the address bus (IAB) as an instruction read by the control signal A, and a memory word read is instructed. In addition, an increment (+2) of the content of the PC is instructed. With the control signal C, the read instruction is stored in the IR.

In step 8, similarly, the control signal A is used to control the address bus (IA) of the contents of the program counter (PC).
B) and an instruction to read a memory word are issued.
Is incremented (+2). Control signal B instructs the input of the instruction (IR) read in the previous step to the instruction decoder. Execution of the next instruction is started.

When returning the PC, the contents read from the stack are temporarily stored in the PC. However, this may not be performed, and the contents may be read from the DBR instead of the PC in step 7.

In the case of a return instruction that does not return the general-purpose register, steps 2 to 5 may be skipped. In other words, steps 2 to 5 may be added to the conventional return instruction.

According to the operation flow, a hardware description language (HDL) can be described, and an instruction decoder DEC can be generated. The part related to the first return instruction (RTS / n) is as follows.

Casex (opcode) (1) 16′b01010100 — 0001? ? ? ? : Begin (2) case (tmg) (3) 4'b0001: begin (4) nextmg = 4'b0100; (5) bcmd = long_read; (6). . . end (7) 4′b0100: begin (8) nextmg = 4′b0101; (9) bcmd = long_read; (10). . . end (11). . . end (12) 16'b01010100_0010? ? ? ? : Begin (13) case (tmg) (14) 4′b0001: begin (15) nextmg = 4′b0010; (16). . . 4′b0010: begin (17) nextmg = 4′b0100; (18). . . This description is based on H standardized as IEEE1364.
It follows the DL description language. The HDL description language itself is described in “Introduction to Verilog-HDL Description” issued by CQ Publishing Co., Ltd. in July 1996.

The caseex and the case follow the subsequent values (16'b01010100_0001 ???) according to the following variables (opcode, tmg) in parentheses.
? :, 4'b0001: etc.). One operation is described by begin to end.

In (1), the input of the instruction decoder (opco
de). Under these conditions, (2)-
In (12), the operation of the instruction code corresponding to RTS / 2 is described. Further, for each instruction code, a condition based on the input (tmg) of the instruction decoder corresponding to the step is indicated. The operation of the first step of RTS / 2 is (4) to
It is described in (7). In (5), the next step (nex)
ttmg) is specified as the fourth step. n
extmg is input to the instruction decoder as tmg after one state. At (6), the bus command is read long word. The long_read is set so that a predetermined code is assigned as a parameter.
After this, other control signals are described. Similarly,
The operation of the fourth step is described in (8) to (11). The operations of the fifth to eighth steps will be described hereafter (12).

Similarly, the input (opcode) of the instruction decoder
The condition of e) describes the operation of the instruction code corresponding to RTS / 3 after (13). In the operation description of the first step, in (15), the next step (next
mg) is the second step. Also,
The operation of the second step will be described after (17). Furthermore, the operations of the fourth to eighth steps are described.

Further, after that, the operation of the instruction code corresponding to RTS / 4 is described, and the second return instruction (RTE /
n), a multiple register save instruction (STM), and other instruction codes are also described.

FIG. 8 shows the execution timing of the first return instruction (RTS / n).

This is an example when n = 2.

Although not particularly limited, the built-in ROM,
This figure shows the timing when the read / write of the RAM can be performed in one state and the program is stored in the internal ROM and the stack is disposed in the internal RAM.

When φ # of T0 (# indicates inverted logic), C
PU address buffer (MAB) or address is IAB
Is output to Further, a bus command (BCMD) indicating an instruction fetch (if) is output from the instruction decoder.

At φ of T1, the contents of IAB are output to PAB, a read cycle is started based on a bus command, and data is output to PDB. At φ #, PDB read data is obtained on the internal data bus IDB,
Is latched in the IR at φ. The above operation is performed by controlling the execution of the previous instruction (prefetch). here,
Although the built-in ROM and RAM are not connected to the PAB and PDB, operations equivalent to PAB and PDB are performed in the module, and the timing chart shows the operation in the module.

When the execution of the immediately preceding instruction is completed and the execution of the instruction is started earliest, the instruction code is input to DEC at φ of T2, and the contents of the instruction are decoded. According to the decoding result, a control signal is output to control each unit. Part of the instruction (register designation feed: r) is given to the register select.

In step 1 described above, by φ # of T2,
The contents of SP are read out to the internal bus GB, and AB and INC are read.
To enter. The address IAB is output from AB. A longword read bus command is output.

At φ of T3, increment by INC (+
4) The result is written to the SP via the internal bus WB. From φ # at T3, data read from the stack is output to the IDB, and at φ at T4, stored in the DBR.

As step 4, by φ and φ # of T4,
The contents of the DBR are written to the designated general register via the internal buses GB, ALU, and internal bus WB. The register specification field is decremented. Similarly to the above, at φ # of T3, the contents of SP are read out to the internal bus GB and input to AB and INC. AB to address IA
B is output. A longword read bus command is output. At φ of T4, the result incremented (+4) by INC is written to SP via the internal bus WB. From φ # at T4, data read from the stack is output to the IDB, and at φ at T5, stored in the DBR.

As step 5, by using φ and φ # of T5,
The contents of the DBR are written to the designated general register via the internal buses GB, ALU, and internal bus WB. The register specification field is decremented. Similarly to the above, at φ # of T4, the contents of SP are read out to the internal bus GB and input to AB and INC. AB to address IA
B is output. A longword read bus command is output. At φ of T5, the result incremented (+4) by INC is written to SP via the internal bus WB. From φ # at T5, data read from the stack is output to the IDB, and at φ at T6, stored in the DBR.

As step 6, by φ and φ # of T6,
The contents of the DBR are written to the PC via the internal buses GB, ALU, and internal bus WB.

In step 7, the contents of the PC are read out to the internal bus GB at φ # of T6 and input to AB and INC. The address IAB is output from AB. Φ of T7
Then, the result incremented (+2) by INC is written to the PC via the internal bus WB.

In step 8, the contents of the PC are read out to the internal bus GB at φ # of T7 and input to AB and INC. The address IAB is output from AB. Φ of T8
Then, the result incremented (+2) by INC is written to the PC via the internal bus WB. The instruction code read at φ of T8 is input to the DEC via the IR, and the next instruction is executed.

FIG. 9 shows an operation flow of the second return instruction (RTE / n).

In response to the first return instruction (RTS / n),
In step 6, writing to the CCR is performed together with the PC. Other operations can be similarly performed.

FIG. 10 shows a second return instruction (RTE / n).
This shows the execution timing.

This is an example when n = 4.

In the same manner as described above, the instruction code is
Input to C, the contents of the instruction are decoded. According to the decoding result, a control signal is output to control each unit. Part of the instruction (register designation feed: r) is given to the register select.

In step 1 described above, by φ # of T2,
The contents of SP are read out to the internal bus GB, and AB and INC are read out.
To enter. The address IAB is output from AB. A longword read bus command is output.

At φ of T3, increment by INC (+
4) The result is written to the SP via the internal bus WB. From φ # at T3, data read from the stack is output to the IDB, and at φ at T4, stored in the DBR.

As step 2, by using φ and φ # of T4,
The contents of the DBR are written to the designated general register via the internal buses GB, ALU, and internal bus WB. The register specification field is decremented. Similarly to the above, at φ # of T3, the contents of SP are read out to the internal bus GB and input to AB and INC. AB to address IA
B is output. A longword read bus command is output. At φ of T4, the result incremented (+4) by INC is written to SP via the internal bus WB. From φ # at T4, data read from the stack is output to the IDB, and at φ at T5, stored in the DBR.

As step 3, by φ and φ # of T5,
The contents of the DBR are written to the designated general register via the internal buses GB, ALU, and internal bus WB. The register specification field is decremented. Similarly to the above, at φ # of T4, the contents of SP are read out to the internal bus GB and input to AB and INC. AB to address IA
B is output. A longword read bus command is output. At φ of T5, the result incremented (+4) by INC is written to SP via the internal bus WB. From φ # at T5, data read from the stack is output to the IDB, and at φ at T6, stored in the DBR.

As step 4, by φ and φ # of T6,
The contents of the DBR are written to the designated general register via the internal buses GB, ALU, and internal bus WB. The register specification field is decremented. Similarly to the above, at φ # of T5, the contents of SP are read out to the internal bus GB and input to AB and INC. AB to address IA
B is output. A longword read bus command is output. At φ of T6, the result incremented (+4) by INC is written to SP via the internal bus WB. From φ # at T6, data read from the stack is output to the IDB, and at φ at T7, stored in the DBR.

As step 5, with φ and φ # of T7,
The contents of the DBR are written to the designated general register via the internal buses GB, ALU, and internal bus WB. The register specification field is decremented. In the same manner as described above, the content of SP is read out to the internal bus GB at φ # of T6, and is input to AB and INC. AB to address IA
B is output. A longword read bus command is output. At φ of T7, the result incremented (+4) by INC is written to SP via the internal bus WB. From φ # at T7, data read from the stack is output to the IDB, and at φ at T6, stored in the DBR.

As step 6, by φ and φ # of T6,
The contents of the DBR are written to the CCR and the PC via the internal buses GB, ALU, and internal bus WB. DBR bit 3
Bits 1 to 24 are written to the CCR and bits 23 to 0 are written to the PC.

In step 7, the contents of the PC are read out to the internal bus GB at φ # of T8 and input to AB and INC. The address IAB is output from AB. Φ of T9
Then, the result incremented (+2) by INC is written to the PC via the internal bus WB.

In step 8, the contents of the PC are read out to the internal bus GB at φ # of T9 and input to AB and INC. The address IAB is output from AB. At φ of T10, the result incremented (+2) by INC is:
The data is written to the PC via the internal bus WB. The instruction code read at φ of T10 is DEC via IR
And the next instruction is executed.

FIG. 11 shows an operation flow of a save instruction (STM) for a plurality of general purpose registers.

Step 0 is controlled by the first word of the instruction code. With the control signal A, the program counter (P
Output of the contents of C) to the address bus (IAB) and read of the memory word are instructed, and increment (+2) of the contents of the PC is instructed. The control signal B indicates the input of the second word of the instruction code to the instruction decoder and the information (MOD) of the number of general-purpose registers specified by the first word.

In step 1, decrement (-4) of the contents of the stack pointer (SP) is indicated by the control signal A. In steps 2 to 5, the control signal A instructs output of the contents of the stack pointer (SP) to the address bus (IAB) and writing of a long word. Control signal B
Indicates that the contents of the general-purpose register are to be stored in the DBW. Control signal C instructs output of the contents of DBW to IDB. The register decoder RDEC is instructed to increment the register field (-1). In steps 2 to 4, decrement (-4) of the SP contents is instructed. Steps 2 to 5 are executed a predetermined number of times according to the designated number (n) of general-purpose registers.

At step 6, the control signal A instructs the output of the contents of the program counter (PC) to the address bus (IAB), the reading of the memory word, and the increment (+2) of the contents of the PC. With control signal B,
Input of the instruction (IR) read in the previous step to the instruction decoder is designated. Execution of the next instruction is started.

In steps 2 to 5, the contents of the general-purpose register are transferred to DBW, and then the contents of the general-purpose register are set to 0.
It is better to clear it. After saving the general-purpose register, it is cleared to 0 and its contents are determined, so that the subsequent processing can be simplified.

For example, when 0 is subsequently substituted into the general-purpose register, the MOV instruction can be omitted. When substituting 1 or the like, use MOV. L # 1, ERn instead of using MOV. B # 1, RnL can be used. Since the immediate data has an area corresponding to the data size in the instruction code, the MOV. L than the instruction code length (for example, 3 words) of MOV. The instruction code length of B (for example, one word) is shorter. This can contribute to a reduction in program capacity.

The constant values used in the program are:
Generally, there are many relatively small values such as 0 and 1.

FIG. 12 shows the execution timing of the save instruction (STM) for a plurality of general purpose registers.

This is an example when n = 2.

At φ of T2, the first word of the instruction code (st
m-1) is input to the DEC, and the contents of the command are decoded. According to the decoding result, a control signal is output to control each unit. Part of the instruction (register designation feed: r) is given to the register select.

In step 0, the contents of the PC are read out to the internal bus GB at φ # of T2 and input to AB and INC. The address IAB is output from AB. Φ of T2
Then, the result incremented (+2) by INC is written to the PC via the internal bus WB. The instruction code read at φ of T3 is input to the DEC via the IR, and the next instruction is executed.

At φ of T3, the second word of the instruction code (st
m-2) is input to the DEC, and the contents of the instruction are decoded. According to the decoding result, a control signal is output to control each unit. Part of the instruction (register designation feed: r) is given to the register select.

In step 1 described above, at φ # of T3,
The contents of the SP are read out to the internal bus GB and input to the INC. At φ of T3, the result decremented (-4) by INC is written to SP via the internal bus WB.

In step 2, the contents of SP are read out to the internal bus GB at φ # of T4 and input to AB and INC. The address IAB is output from AB. A long word write bus command is output. Φ of T5
Then, the result decremented (-4) by INC is written to SP via the internal bus WB. Further, the contents of the designated general register are written into the DBW via the internal bus DB. The register specification field is incremented. From φ # of T5, the content of DBW is ID
B.

In step 5, the contents of SP are read out to the internal bus GB at φ # of T5, and the address IAB is output via AB. A long word write bus command is output. At φ of T5, the contents of the designated general-purpose register (r) are written to DBW via the internal bus DB. The register specification field is incremented. From φ # at T5, the contents of DBW are output to IDB.

In step 6, the contents of the PC are read out to the internal bus GB at φ # of T6 and input to AB and INC. The address IAB is output from AB. Φ of T7
Then, the result incremented (+2) by INC is written to the PC via the internal bus WB. The prefetched instruction code (next) is transmitted to the D via the IR.
The next command is input to the EC and executed.

As described above, in steps 2 to 5, T
5. The contents of the general-purpose register are cleared to 0 at φ # of T6. This means that the internal bus WB at the timing is set to 0,
This should be written to a general-purpose register.

FIG. 13 shows an outline of a development environment of the CPU of the present invention.

The user can use various editors to edit C
Create a program in language or assembly language. This is usually created by dividing into a plurality of modules.

The C compiler inputs each C language source program created by the user and outputs an assembly language source program or an object module.

For example, when creating a program in C language, Is written as follows for the CPU of the present invention.

[0147] General-purpose registers ER3 and ER4 used in the function are STM
It is saved on the stack by an instruction and cleared to 0. It is recovered from the stack when a return instruction is issued.

In the main program, the function seq
When calling 0, it is described as seq0 (); and is compiled into JSR $ _seq0 and a subroutine branch instruction.

The assembler inputs an assembly language source program and outputs an object module.

The linkage editor inputs a plurality of object modules generated by the C compiler or assembler, resolves external references and relative addresses of each module, combines them into one program, and loads the load module. Output.

The load module is input to a simulator / debugger to simulate the operation of the CPU on a system development device such as a personal computer.
The execution results can be displayed, and the program can be analyzed and evaluated. Also, by inputting to an emulator, so-called in-circuit emulation that operates on an actual application system or the like is performed, analysis and evaluation of the actual operation of the entire microcomputer can be performed.

Further, by inputting the load module into a ROM writing device such as a PROM writer, the created program can be loaded into the case where the built-in ROM of the microcomputer is a flash memory or an external flash memory. Alternatively, it is also possible to write the data in the built-in ROM in the microcomputer manufacturing process. If necessary, the data is converted into a desired format by an object converter or the like.

In addition, a general-purpose subroutine can be provided as a librarian.

The CPU definition information file designates a CPU to be compiled, and makes it possible to use a common development environment between a CPU (existing) having no return instruction according to the present invention and a CPU according to the present invention.

For example, by describing SET CPU = CPU1; in the CPU definition information file, the CPU of the present invention is selected.

At the time of compiling, by referring to the CPU definition information file and selecting a CPU having no return instruction according to the present invention, the function becomes: Becomes MOV. L is determined according to the processing contents of the function.
May change.

The C compiler itself has a function of converting a program in C language into a command of the CPU, and a function of C ++.
Improvements in functions that are not directly related to the instruction set of the CPU, such as compiling a program in a language and optimizing between modules, are being made. Must be applied to the compiler. If a common C compiler is used as in the present invention, it is easy to improve functions not directly related to the instruction set of the CPU, and it is possible to improve development efficiency and the like.

According to the above embodiment, the following operation and effect can be obtained.

By performing a return operation from a plurality of general-purpose registers and a subroutine or an exception handling routine with a single instruction, the instruction code length can be relatively shortened (for example, two words can be shortened). It is possible to reduce the number of times instructions are read and to increase the speed.

For example, since a function frequently used in the C language or the like is a subroutine, a return instruction from the subroutine corresponding to this number is used. Since necessary data is allocated to the general-purpose register for each function, the previous contents of the general-purpose register are saved / restored. Therefore, the effect of shortening the instruction code length by such a return instruction also increases.

Further, since the number of general-purpose registers to be saved / restored differs for each function, a plurality of instructions having different numbers of registers are supported, or a return instruction without the restoration of general-purpose registers is also supported. This makes it easy to create programs and improves usability.

Even when the number of general-purpose registers of the CPU is large, the general-purpose register to be returned can be specified, so that the degree of freedom in the use of the general-purpose registers is hardly impaired. Further, there is no need to save / restore an undesired general-purpose register.

By using a fixed combination designating a plurality of general-purpose registers, the instruction code length can be shortened. Further, by fixing the number of execution states of each instruction,
The number of internal conditional branches is reduced (the decoder may be described according to the input opcode of the instruction decoder), the internal logic is simplified, and the logic scale can be reduced. It can be easily realized by wired logic or the like without using a microprogram. By using wired logic or the like regardless of the microprogram, it is possible to contribute to speeding up of a logic circuit. By providing the register decoder with an incrementer, an increase in logical scale can be minimized, and a continuous arbitrary combination can be designated.

A general-purpose register save instruction (STM), which enables the same designation, is executed at the beginning of a subroutine or an exception handling routine, and finally, the return instruction of the present invention is executed. Further usability can be improved. By clearing the general-purpose register after saving when executing the general-purpose register save instruction, the instruction code length can be further reduced, and the number of execution states can be reduced.

In addition, by performing data read / write continuously, it is easy to effectively use them even when a burst operation to a memory or the like is required or when the bus width is expanded.

At the source program level or the object program level, by including the existing CPU instruction set and adding the above instructions, software resources can be effectively used, and the software development efficiency of the user can be improved. Can be improved. It is possible to enjoy both the advantage of maintaining compatibility at the source program level or the object program level and the advantage of adding the transfer instruction.

The invention made by the present inventors is not limited to the embodiments, but can be variously modified without departing from the gist of the invention.

The instruction code is an example, and various changes can be made. It goes without saying that the present invention can be applied to a case where a new instruction set is developed in addition to an existing instruction set.

The structure of the stack in exception processing is CC
Although R and PC are combined to form 32 bits,
It can be divided into 6 bits and 32 bits, and other control registers can be added. The PC may also be 32-bit.

The configuration and number of general-purpose registers and the number of general-purpose registers to be restored by a return instruction can be arbitrarily changed. The number of general-purpose registers to be restored may be one.
The order in which they are stored in the stack can be arbitrarily changed. When restoring a general-purpose register, it is more convenient to read continuously from the PC (and CCR).

The incrementer (RINC) may perform the addition / subtraction with the output of the instruction decoder in addition to the increment / decrement. In the case of the return instruction of the present invention, 1/2/3 may be sequentially subtracted from the register designation field of the instruction code. The register specification field included in the instruction code does not necessarily need to correspond to the general-purpose register specified first. It suffices if a desired general-purpose register can be specified in combination with the addition / subtraction.

When the stack pointer ER7 is specified as the general register to be returned, writing to ER7 may be prohibited. This is because saving / restoring the stack pointer is meaningless and a predetermined point operation may be performed.

At the time of execution of the general-purpose register save instruction, both the instruction to clear the general-purpose register after the save and the instruction to hold the general-purpose register may be provided. This may be specified by a predetermined bit of the first word of the instruction code, a control signal (MOD) may be generated, and the operation of the second word may be changed.

The content of the clear of the general-purpose register is not limited to 0, but may be another value. A means for designating the content to be cleared may be provided separately.

The basic unit of an instruction is not limited to 16 bits. The return instruction of the present invention can be applied to an 8-bit unit or a 32-bit unit.

For simplicity, the bus width is set to 32 bits.
Instruction read is in 16-bit units, but instruction read is 3 bits.
The speed can be increased in units of 2 bits. Such an example is described in Japanese Patent Application No. 11-167812.
Alternatively, the read / write of a long word may be executed by two read / write operations in word units with a bus width of 16 bits. Such an example is disclosed in Japanese Patent Application No.
-320518.

The other functional blocks of the microcomputer are not restricted at all.

In the above description, the case where the invention made by the present inventor is mainly applied to a microcomputer which is the background of the application has been described. However, the present invention is not limited to this, and it is applicable to other data processing devices. The present invention can be applied to at least a data processing device having a plurality of register means.

[0179]

The effects obtained by typical ones of the inventions disclosed in the subject will be briefly described as follows.

In a return instruction from a subroutine or from exception processing, the instruction code includes information for specifying a plurality of general-purpose registers, and when the instruction code is executed,
By restoring the designated general-purpose register in addition to restoring the program counter, usability is improved, and the program capacity and the number of execution states can be reduced.

Furthermore, the instruction code length can be shortened by making the combination of designated general registers continuous, and the internal conditional branch can be made by fixing the number of execution states of each instruction. It can reduce the number, simplify the internal logic, and reduce the logic scale. Even when a 16-bit variable length instruction code system is adopted, the overall program efficiency can be improved by effectively using instruction codes while simplifying instruction prefetching and instruction decoding.

[0187] A general-purpose register save instruction enabling the same designation is executed at the head of a subroutine or an exception handling routine, and finally, the return instruction of the present invention is executed, thereby further improving usability. Can be improved.

By continuously performing the return of the general-purpose register and the return of the program counter and the like, the internal operation can be facilitated and the speed can be increased.

By supporting a plurality of return instructions having different numbers of registers, continuous general-purpose registers can be specified, and further, the creation of a program can be facilitated and the usability can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram of a microcomputer to which the present invention is applied.

FIG. 2 is a diagram showing a configuration example of a general-purpose register and a control register built in a CPU.

FIG. 3 illustrates a configuration example of a CPU.

FIG. 4 is a detailed block diagram of a part of a register selector RDEC.

FIG. 5 is an instruction format diagram of a first return instruction (RTS / n) and a second return instruction (RTE / n) including the return of a plurality of general-purpose registers.

FIG. 6 is a diagram illustrating a configuration example of a stack of a first return instruction (RTS / n) and a second return instruction (RTE / n) including the return of a plurality of general-purpose registers.

FIG. 7 is a diagram illustrating an operation flow of a first return instruction (RTS / n);

FIG. 8 is a diagram illustrating execution timing of a first return instruction (RTS / n).

FIG. 9 is a diagram showing an operation flow of a second return instruction (RTE / n).

FIG. 10 is a diagram illustrating execution timing of a second return instruction (RTE / n).

FIG. 11 is a diagram showing an operation flow of a save instruction (STM) for a plurality of general-purpose registers.

FIG. 12 is a diagram of execution timing of a save instruction (STM) for a plurality of general-purpose registers.

FIG. 13 is a schematic diagram of a development environment of a CPU of the present invention.

Claims (5)

[Claims] 1. A data processing device for sequentially executing a predetermined instruction, comprising a plurality of register means, and an instruction read operation (PC return) based on the contents read from a stack.
And a return instruction (RTS / RTS) for writing another content read from the stack into at least one of the register means in accordance with the information specified in the instruction code.
(2, RTE / 2) instruction processing means. 2. The data processing device according to claim 1, wherein:
A register designating means and an arithmetic operation means (RINC),
The return instruction performs an operation of writing another plurality of contents read from the stack to the information specified in the instruction code and the plurality of contents specified by the arithmetic operation means in the register means. Characteristic data processing device. 3. A data processing apparatus according to claim 1, further comprising instruction execution means for a plurality of return instructions having different numbers of register means for writing. 4. A data processing apparatus according to claim 1, further comprising an instruction execution unit for another return instruction for performing an instruction read operation (PC return) based on the contents read from the stack. Data processing device. 5. A data processing apparatus according to claim 2, wherein said instruction specified in said instruction code and a plurality of register means specified by said arithmetic operation means write to said stack. A data processing system comprising (STM) instruction execution means.