JPH08328867A - Program confirmation method for digital signal processor and digital signal processor system - Google Patents

Abstract

PURPOSE: To prevent the defective operation of a DSP(digital signal processor) by confirming whether the downloaded processing program is correct or not. CONSTITUTION: A program containing a test mode is downloaded into an instruction storage part 103 which stores a processing program group of a DSP 102. Then a test mode is actuated before the processing program of a system including the DSP 102 is carried out, so that it is possible to confirm whether the processing program of the DSP 102 is downloaded in a normal way. Furthermore, the system processing program is not immediately started when the power supply of the system including the DSP 102 is started or reset. Thus the harmful effect due to an abnormal operation of the DSP 102 can be prevented to the peripheral circuits. Then a CPU 101 can judge the DSP 102 by writing the normal status into a readable register when the DSP 102 is normally operating.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and system for confirming whether a processing program of a digital signal processor is correctly set from the outside, and particularly a processing program downloaded from the outside is a digital signal. The present invention relates to a program checking method and its system for checking whether the instruction RAM connected to the outside of the processor or the instruction RAM inside the digital signal processor is correctly set.

[0002]

2. Description of the Related Art Conventionally, a digital signal processor (hereinafter referred to as a DSP) is one of devices used for adaptive processing for storing signal values and changing processing characteristics according to circumstances. . The DSP can change the processing contents by program control without changing the peripheral circuits.

Therefore, in many cases, not only the ROM but also the RAM is used as a memory for storing the processing instructions of the DSP, and a processing program is executed from the outside connected to the DSP, for example, by a central control unit (hereinafter referred to as CPU). Is downloaded to the instruction RAM, and the DSP processes according to the downloaded processing program. That is,
The DSP fetches the downloaded processing program one instruction at a time, decodes the instruction, and executes processing according to the decoded result.

In a system using such a DSP, when the power is turned on or the system is reset, a processing program to be executed by the DSP is downloaded to the instruction RAM, and a start signal for starting the operation is output to the DSP after the download is completed. The DSP executes the instruction downloaded to the instruction RAM as soon as the activation signal is input.

[0005]

However, in the conventional processing system using the DSP, the CPU or the like immediately activates the processing to the DSP after the completion of downloading the program of the DSP, so that the downloaded processing program is executed by the DSP. There is a problem that it is not possible to confirm whether or not it conforms to the command form of. Therefore, when an instruction that is not in the instruction form of the DSP is downloaded to the instruction RAM, the DSP cannot execute the instruction, which causes a problem that the entire device does not operate normally.
Further, if some bits indicating a processing instruction are not written correctly due to a problem such as the download timing of the CPU, the DSP executes the written wrong instruction, so that the processing is not performed correctly. Or, there is a problem of causing a failure in the processing system.

The present invention eliminates the above-mentioned conventional drawbacks and confirms whether or not a downloaded processing program is correct, thereby preventing a defective operation of a DSP and a program confirmation method for a digital signal processor. Provide the system.

[0007]

In order to solve this problem, a program confirmation method for a digital signal processor according to the present invention is based on a processing program downloaded from a central control unit for controlling the entire system.
What is claimed is: 1. A program confirmation method for confirming whether or not the processing program of a digital signal processor which processes data in response to a command from the central control unit is normally loaded. After downloading the test program together with, the test command is issued, the digital signal processor executes the test program based on the test command, and the central control unit, based on a response from the digital signal processor, It is characterized by confirming whether or not the processing program is normally loaded.

Here, the confirmation is performed based on the presence / absence of a response from the digital signal processor. When the response is not received for a predetermined time, it is determined that the processing program is not normally loaded. The confirmation is performed based on the content of the response from the digital signal processor, and in the case of an unexpected response or a response indicating an error, it is determined that the processing program is not normally loaded. Also, the test program is
It includes a series of unconditional branches distributed and inserted in the processing program, and whether or not the series of unconditional branches is normally executed by the digital signal processor.
It is considered whether or not the processing program is normally loaded. In the confirmation, if there is a response from the digital signal processor or if there is an unexpected response, it is determined that the processing program is not normally loaded. Further, the test program includes an algorithm for confirming a bit error of the processing program, and the confirmation of the bit error by the digital signal processor is regarded as whether or not the processing program is normally loaded. The algorithm is a checksum, and a bit error is confirmed by comparing the checksum calculated in advance by the central controller with the checksum calculated by the digital signal processor according to the algorithm. In the confirmation, if there is a response from the digital signal processor or a response indicating an error, it is determined that the processing program is not normally loaded.

Further, a program confirmation method for a digital signal processor according to the present invention includes a central control unit for controlling the entire system, a digital signal processor for processing data, and an instruction for storing a processing program group of the digital signal processor. A storage unit, a data storage unit for storing data to be processed and data after processing, a first register for storing data for designating processing contents of the digital signal processor, and a status of the digital signal processor. A method for confirming a program of a digital signal processor in a system including a second register, wherein the central controller writes a processing program group of the digital signal processor in the instruction storage unit,
Before starting the processing of the data, the central control unit sets the data for instructing the operation of the first program of the processing program group in the first register; A step of activating, a step of executing processing by the signal processor, a step of reading data of the second register by an output signal from the digital signal processor, and a step of normalizing the first program by the digital signal processor. And the step of activating the processing program other than the first program to the digital signal processor when the read data indicates that the processing has been executed.

Here, the execution step includes a step of executing initialization, a step of executing a plurality of unconditional branch instructions,
A step of setting data indicating a normal end in the second register when the execution of the first program ends normally; and an step of outputting an interrupt to the central controller after the setting of the second register ends The branch destination after the execution of the unconditional branch instruction is the next unconditional branch instruction in the first program or the instruction for performing the data setting process to the second register.

Further, a program confirmation method for a digital signal processor of the present invention is a central control unit for controlling the entire system, a digital signal processor for processing data, and an instruction for storing a processing program group of the digital signal processor. A storage unit, a data storage unit for storing data to be processed and data after processing, a first register for storing data for designating processing contents of the digital signal processor, and a status of the digital signal processor. A program confirmation method for a digital signal processor in a system comprising a second register for storing data representing all program groups except the first program data from the processing program group written by the central controller. Three A step of writing a processing program group of the digital signal processor in the instruction storage unit by the central control unit by providing a register, and the central control unit first program of the processing program group before starting processing of data. Setting the data for instructing the operation of the first register in the first register, and the data representing the entire program group excluding the first program data from the processing program group written by the central controller is set to the third register. Setting in a register, activating the process in the digital signal processor, executing the process in the signal processor, and reading data in the second register by an output signal from the digital signal processor. By the digital signal processor If the first program is indicated by the read data that was successful, the second to the digital signal processor 1
And a step of activating the processing program excluding the above program.

Here, the execution step includes a step of executing initial setting, a step of reading data written in the third register, and a processing program for sequentially processing all program groups except the first program. And a step of repeating the execution step until the reading of all the program groups except the first program is completed, and a group of all programs except the first program based on the data read by the step. The step of obtaining data representing the configuration of the program, the step of comparing the data representing the configuration of all program groups except the first program determined in the step with the data written in the third register, and the comparison. If they match in the process, data indicating that the execution of the first program is normally completed is set in the second register. A step of, consists of a step of outputting an interrupt to the central controller after setting the end of the second register, in the step of the comparison, the first
If the data representing the configuration of all programs except the above program does not match the data written in the third register, the data indicating that the processing program has not been written correctly is set in the second register. To do.

Further, the digital signal processor system of the present invention is based on a processing program downloaded from a central control unit for controlling the entire system.
A digital signal processor system having a digital signal processor for processing data in response to an instruction from the central control unit, wherein the central control unit comprises load means for downloading a test program together with the processing program, and a test instruction. And a confirmation means for confirming whether or not the processing program is normally loaded, based on a response from the digital signal processor, wherein the digital signal processor is based on the test instruction. It is characterized by comprising an executing means for executing the test program.

Here, the confirmation means, when there is no response from the digital signal processor for a predetermined time,
It is determined that the processing program is not normally loaded. The confirmation means determines that the processing program is not normally loaded when the response from the digital signal processor is an unexpected response or a response indicating an error. Further, the test program includes a series of unconditional branches distributed and inserted in the processing program, and the confirming unit does not normally execute the series of unconditional branches by the digital signal processor. Is determined from the presence or absence of a response from the digital signal processor or an unexpected response, and it is considered that the processing program has not been normally loaded. Further, the test program includes an algorithm for confirming a bit error of the processing program, and the confirming means confirms the confirmation of the bit error by the digital signal processor, indicating presence or absence of a response from the digital signal processor, or an error. Judging from the response, it is considered that the processing program was not loaded normally. Further, the algorithm is a checksum, and further comprises a holding means for holding a checksum calculated in advance by the central control unit, the confirmation means, the checksum and the digital signal previously calculated in the central control unit. The bit error is confirmed by comparison with the checksum calculated according to the algorithm by the processor.

[0015]

Operation: A command for performing a test for confirming the processing program downloaded to the instruction storage unit is put in the processing program, and the processing that the central control unit or the like downloads when the power of the apparatus is turned on or reset. By activating the processing for checking the program, it is possible to check whether the processing program downloaded to the instruction storage unit is correct or not. By adding a simple procedure, the digital signal processor will fail. Prevent movement.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS This embodiment will be described below in detail with reference to the accompanying drawings. First Embodiment <Structural Example of Processing System Including DSP> FIG. 1 is a diagram showing the structure of a processing system including a DSP according to a first embodiment for implementing the present invention.

(Example of DSP system) In FIG. 1, 104a
Is a storage unit a for storing processing data to be processed, 1
Reference numeral 02 denotes a DSP that executes processing according to the processing program stored in the instruction storage unit 103, and reference numeral 104b denotes a storage unit b that stores processed data output from the DSP 102.

(Example of CPU system) On the other hand, 101 is a CPU for controlling the entire apparatus, which is a group of processing programs stored in a system program 109a stored in a ROM 109 and an auxiliary storage device 111 such as a hard disk or a floppy disk. 109b and 109c are downloaded to the RAM 110 to perform various control processes. 109 is
A ROM for storing a system program 109a for controlling the CPU 101 and DSP processing program groups 109b, 109c, 110 is a RAM for working the CPU 101 or for downloading and executing the program from the auxiliary storage device 111, and 111 is an auxiliary storage for the CPU 101. Device, eg hard disk, floppy disk, MO
And CD-ROM. Reference numeral 112 is a bus for exchanging signals with the peripheral portion of the CPU 101, and 113 is the CPU 10.
1 is a peripheral device interface circuit for interfacing between 1 and external communication means. Reference numeral 114 is a watchdog timer, which is initialized by a signal 116 when the DSP 102 is started by a signal 107.
102 goes out of control and interrupt signal 10 from DSP 102
If 8 does not occur within a predetermined time, the watchdog timer 114 generates an interrupt signal 115 and C
It is for sending to the PU 101 and causing the CPU 101 to perform appropriate error processing. The watchdog timer 114 may be inside the CPU 101.

(Example of connection between DSP and CPU) 103 is D
An instruction storage unit configured by a RAM that stores a processing program group of the SP 102, 105 a command register that stores a command for instructing a processing program that the DSP 102 executes, 106 a status register that stores the status of the DSP 102, 107 CPU 101 is D
Interrupt signal for activating SP102, 108
Is an interrupt signal output from the DSP 102 to the CPU 101.

<Operation Example of Processing System Including DSP> FIG. 2 is a flowchart showing the processing steps of the DSP 102 in the first embodiment. When the power is turned on or the system is reset, the CPU 101 uses the DSP 1 to which the present invention is applied.
02 processing program group, ROM109 or RAM
110 or the auxiliary storage device 111 to the instruction storage unit 10
Download to 3. The CPU 101 is the instruction storage unit 10
When the download to 3 is completed, command register 1
A command for setting a mode (hereinafter, referred to as a test mode) for confirming whether the download to the instruction storage unit 103 is correctly performed is set in 05. After setting the command in the command register 105, the CPU 101
By outputting the activation signal 107 to the DSP 102, the DS
Activate P102.

When the CPU 101 is activated, FIG.
The step S101 shown in is satisfied, and the DSP 102 proceeds to the next step S102. In step S102, the command set in the command register 105 is decoded. That is, the command register 10 by the CPU 101
The command set to 5 is read, and it is determined whether the processing operation which is activated is in the test mode or another processing. When the command set in the command register 105 indicates the test mode, the process proceeds to step 103, and the DSP 102 starts the test mode processing. If the command read in step S102 is not in the test mode, the process proceeds to step S104, and the process corresponding to the command set in the command register is executed.

(Configuration example of test mode program) FIG. 3
Shows an example of the configuration of the test mode processing program. The test mode program 30 is made up of instructions and processes as indicated by reference numerals 301 to 309 in FIG. That is, the configuration of the test mode program of this embodiment is the same as that of the test mode initial process 301 and the above step S1.
Normal system programs 31 to 3n executed in 04
A plurality of unconditional branch instructions 302 to 307 inserted between
And a data setting process 308 for the status register,
It is composed of an interrupt signal output process 309 to the CPU 101. When the unconditional branch instructions 302 to 307 are executed, the program is configured to branch to the next unconditional branch instruction. Here, the system programs 31-
3n may be, for example, a program unit or a subroutine unit, or may be forcedly inserted in the middle of a system program by giving priority to the capacity between unconditional branch instructions. Furthermore, in order to increase the reliability of the test, an appropriate number calculated from the capacity of the system program may be randomly inserted.

When a test mode command is set in the command register 105, the DSP 102 first executes the test mode initial processing 301. The initial processing 301 is, for example, an initial set such as a register, but it will not be described in detail here. DSP102
Executes the instructions stored in the instruction storage unit 103 in sequence, so when the series of initial processing 301 in the test mode is completed, the unconditional branch instruction 302 is executed next. If the unconditional branch instruction 302 is downloaded correctly,
The next instruction executed by the DSP 102 is the unconditional branch instruction 30.
It is the instruction of the branch destination of 2, that is, the unconditional branch instruction 303.

As described above, a plurality of unconditional branch instructions are inserted in the entire processing program, and each unconditional branch instruction is executed one after another during the test mode execution. If the entire processing program is correctly downloaded, the nth unconditional branch instruction 307 is executed, the execution judgment of the final instruction in step S105 is satisfied, and the process proceeds to step S106.

In step S106, the branch destination instruction of the DSP 102, that is, the status register 106 shown in FIG.
The normal operation status setting process 308 is performed. That is, the status indicating that the downloaded program is correctly downloaded to the instruction storage unit 103 is set in the status register 106. In the next step S107, the DSP 102 sets the status in the status register 107, outputs the interrupt signal 108 to the CPU 101, and ends the test mode processing.

Since the test mode according to the present embodiment mainly moves between unconditional branch instructions, if even one erroneous instruction is downloaded among the instructions in the test mode, D
The SP 102 will execute an erroneous instruction, that is, execute a processing program other than the other test mode processing or run away. Therefore, the DSP 102 does not set the status in the status register 107.

Therefore, the CPU 101 can confirm that the processing program other than the test mode is being executed by searching the contents of the status register 106. In the event of a further runaway, the watchdog timer 1 shown in FIG.
14 is initialized, the time from that time is monitored, and an interrupt signal 115 is generated when a time-out occurs.
By performing error processing by 101, the instruction storage unit 103
It is possible to perform reliable confirmation and error handling of whether the download to the server was successful. In other words, if the interrupt is not output from the DSP 102 even after the lapse of a predetermined time, it is possible to know that the instruction download to the instruction storage unit 103 has not been normally performed.

Actually, it cannot be said that there is an error in the entire system program just because all the unconditional branch instructions have been executed normally, but the unconditional branch instructions are properly processed at appropriate intervals. It is clear that the reliability of the test can be increased by inserting only the number. Second Embodiment <Configuration Example of Processing System Including DSP> FIG. 4 is a diagram showing a configuration of a processing system including a DSP according to a second embodiment for implementing the present invention. In FIG. 4, elements having the same functions as those of the configuration of FIG. 1 are designated by the same reference numerals as those of FIG.

In FIG. 4, a block denoted by reference numeral 401 is a checksum as data of a program group obtained by subtracting the program data for executing the test mode from the processing program group downloaded by the CPU 101 to the instruction storage unit 103. A checksum data register (CSR) for storing. <Operation Example of Processing System Including DSP> FIG. 5 is a flowchart showing the processing steps of the DSP 103 in the second embodiment.

The CPU 101 stores in the instruction storage unit 103 the DSP 102 when the system power is turned on or reset.
Download the processing programs of. Example 1
As described above, the processing program includes the DSP1
A test mode program for confirming whether the processing program group No. 02 is correctly downloaded to the instruction storage unit 103 and a processing program for the entire system are included.

The CPU 101, like the first embodiment,
A command instructing execution of the test mode is set in the command register 105, and the checksum of the remaining processing program group except the processing program portion of the test mode is taken from the processing program group to be downloaded, and the checksum data is set in the CSR 401. To do. CPU 101
When the setting in each register is completed, the DSP 102 activates the DSP 102 by the activation signal 107.

When the DSP 102 is activated by the CPU 101, step S201 shown in FIG. 5 is satisfied, and the process proceeds to the next step S202. In step S202, the command written in the command register 105 is decoded. When the command written in the command register 105 indicates the test mode, the process proceeds to step S203,
The DSP 102 executes the test mode. Step S
If the read command indicates something other than the test mode in 202, the process proceeds to step S204, and the DSP 10
2 executes a processing program according to the command set in the command register.

(Configuration example of test mode program) FIG. 6
FIG. 3 is a diagram showing an example of a processing program group downloaded to the instruction storage unit 103 by the CPU 101. In the case of the second embodiment, the test mode processing program 60 and the system programs 61 to 6n are downloaded to different areas in the instruction storage unit 103.

Upon activation of the test mode execution, the DSP 102 proceeds to step S203, as shown in FIG.
First, the initial process 601 in the test mode is performed. When the initial processing 601 in the test mode is completed, the DSP
102 starts the test mode process 602. That is, D
The SP 102 reads the data written in the CSR 401 by the CPU 101.

Next, the DSP 102 sequentially reads, as data, a program group from the processing program group downloaded to the instruction storage unit 103 by the CPU 101, excluding the program portion for performing the test mode processing, and based on the read data. Checksum data is calculated. In other words, the code indicating the instruction is taken into the DSP 102 as the processing data and the processing for obtaining the checksum is executed. The DSP 102 obtains the checksum data of the system program by reading all the system programs shown in FIG. 6 as data.

In step S205 of FIG. 5, the DSP 10
2 compares the calculated checksum data of the system program with the data of the CSR 401 read in advance. If the data written in the CSR 401 and the checksum data obtained in the test mode match, it is determined to be normal and the process proceeds to step S206. In step S206, the DSP 102 sets a status indicating normal operation in the status register 106, assuming that the processing program group has been correctly downloaded to the instruction storage unit 103 by the CPU 101. Then in step S208
Then, the interrupt signal 108 is output to the CPU 101, and the process ends.

In step S205, if the data of the CSR 401 and the checksum data obtained by executing the test mode in step S203 do not match, the process proceeds to step S207 and the status register 10
Set the status indicating abnormal operation to 6 and step S2
At 08, the interrupt signal 108 is output to the CPU 101, and the process ends. In this example, the checksum data coincidence is determined. However, if data is added to the processing program so that the checksum becomes a predetermined value, for example, “0”, the checksum data register is not needed and the checksum data register is not required. The abnormality can be directly determined from the calculation result of.

Normally, when the CPU 101 recognizes that the interrupt signal 108 is output from the DSP 102 after activating the test mode in the DSP 102, it reads the status of the status register 106.
The CPU 101 uses the read status register 106.
If the status indicates that the operation is normal, the instruction storage unit 10
It is determined that the processing program group has been correctly downloaded to No. 3, but if the read status indicates an abnormal operation or an undefined one, the download to the instruction storage unit 103 is correctly performed. It is judged that it was not lost, and the download is performed again.

Also, as in the first embodiment, the time elapsed after the DSP 102 is activated via the signal line 107 is monitored by a timer or the like, and the DSP 102 is activated even if a predetermined time has elapsed after the activation. If the interrupt signal 108 from the DSP 102 is not output, that is, the CPU 101 activates the DSP 10 via the signal line 107 and simultaneously initializes the watchdog timer 114 via the signal line 116. If it does not occur within the specified time, watchdog timer 1
An interrupt signal 115 is generated from 14 to notify the CPU 101 of error processing. At this time, the CPU 101 determines that the operation is abnormal and downloads again. In this embodiment, the first and second embodiments have been described independently, but by combining them, the reliability of confirmation can be further increased. Further, the present invention may be applied to a system including a plurality of devices or an apparatus including one device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0040]

As described above, according to the present invention,
(EN) A method and system for confirming a program of a digital signal processor which prevents a malfunction of a DSP by confirming whether or not a downloaded processing program is correct.

That is, by downloading the program including the test mode to the instruction storage unit for storing the processing program group of the DSP and operating the test mode before executing the processing program of the system in which the DSP is incorporated, the DSP is operated. You can check whether the processing program of is downloaded normally. Also, DSP
Since the processing program of the system is not started immediately when the power of the system incorporating the above is turned on or reset, it is possible to prevent the peripheral circuits from being adversely affected by the abnormal operation of the DSP.

When the DSP operates normally, the CPU can determine the operating state of the DSP by writing a normal operation status in a register readable by the CPU. Furthermore, if the program is not downloaded correctly, the program with a configuration that causes the DSP to run out is set to the test mode, and the elapsed time after the DSP is activated is monitored by a timer or the like, so that the predetermined time has passed. If there is no interrupt from the DSP, it can be determined that the DSP is operating abnormally.

Furthermore, by reading the program data of the system as processing data into the DSP, obtaining the checksum, and comparing it with the checksum data written in advance by the CPU, the processing program downloaded to the instruction memory can be read as data. There is an effect that it is possible to completely confirm whether it is correct on the above.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a configuration example of a processing system including a DSP according to a first exemplary embodiment.

FIG. 2 is a flowchart illustrating processing of a DSP according to the first exemplary embodiment.

FIG. 3 is a diagram showing a processing program in a test mode according to the first embodiment.

FIG. 4 is a diagram illustrating a configuration example of a processing system including a DSP according to a second embodiment.

FIG. 5 is a flowchart showing processing of a DSP in the second embodiment.

FIG. 6 is a diagram illustrating a processing program in a test mode according to the second embodiment.

[Explanation of symbols]

 101 CPU 102 DSP 103 Command Storage Unit 104a Process Data to be Processed 104b Process Data Processed by DSP 105 Command Register 106 Status Register 107 Activation Signal 108 Interrupt Signal 109 Interrupt Signal 109a System Program 109b Processing Program Group 109c Processing Program Group 110 RAM 111 auxiliary storage device 112 bus 113 peripheral interface circuit 114 watchdog timer 115 interrupt signal 116 initialization signal 401 checksum register (CSR)

Claims (18)

[Claims] 1. Based on a processing program downloaded from a central control unit for controlling the entire system,
A program confirmation method for confirming whether or not the processing program of a digital signal processor, which processes data in response to a command from the central control device, is normally loaded, wherein the processing program is executed from the central control device. After downloading the test program together with, issue a test command, the digital signal processor executes the test program based on the test command, the central controller, based on the response from the digital signal processor, A program confirmation method characterized by confirming whether or not a processing program has been normally loaded. 2. The confirmation is performed based on the presence / absence of a response from the digital signal processor, and when the response is not received for a predetermined time, it is determined that the processing program is not normally loaded. The program confirmation method according to claim 1. 3. The confirmation is performed based on the content of the response from the digital signal processor, and in the case of an unexpected response or a response indicating an error,
3. The program checking method according to claim 1, wherein it is determined that the processing program is not normally loaded. 4. The test program includes a series of unconditional branches inserted dispersedly in the processing program, and whether or not the series of unconditional branches is normally executed by the digital signal processor. 2. The program checking method according to claim 1, wherein it is considered whether or not the processing program is normally loaded. 5. The confirmation according to claim 4, wherein the presence or absence of a response from the digital signal processor or an unexpected response determines that the processing program is not normally loaded. How to check the program. 6. The test program includes an algorithm for checking a bit error of the processing program,
5. The program confirmation method according to claim 1, wherein the confirmation of the bit error by the digital signal processor is regarded as whether or not the processing program is normally loaded. 7. The algorithm is a checksum, and by comparing a checksum calculated in advance by the central controller with a checksum calculated by the digital signal processor according to the algorithm,
7. The program checking method according to claim 6, wherein a bit error is checked. 8. The confirmation is characterized by determining that the processing program is not normally loaded in the case of a response indicating the presence or absence of a response from the digital signal processor or a response indicating an error. Program confirmation method. 9. A central control unit for controlling the entire system, a digital signal processor for processing data, an instruction storage unit for storing a processing program group of the digital signal processor, and data to be processed and processed data. A digital signal in a system including a data storage unit for storing the data, a first register for storing data for designating the processing content of the digital signal processor, and a second register for storing the status of the digital signal processor. A method for checking a program of a processor, wherein the central control unit writes the processing program group of the digital signal processor in the instruction storage unit, and the central control unit sets the processing program group before starting processing of data. The first pro of A step of setting data for instructing the operation of the RAM in the first register; a step of activating the digital signal processor for the processing; a step of executing the processing by the signal processor; Reading the data of the second register according to the output signal of the digital signal processor, and if the read data indicates that the first program is normally executed by the digital signal processor, the first signal is transmitted to the digital signal processor. And a step of activating a processing program excluding the above program, the method for checking a program of a digital signal processor. 10. The execution step includes a step of executing initialization, a step of executing a plurality of unconditional branch instructions, and a step of executing a second register operation when the execution of the first program ends normally. It comprises a step of setting data indicating a normal end and a step of outputting an interrupt to the central controller after the setting of the second register is completed, and the branch destination after the execution of the unconditional branch instruction is the first 10. The program verification method for a digital signal processor according to claim 9, wherein the program is a next unconditional branch instruction in a program or an instruction for performing data setting processing to the second register. 11. A central control unit for controlling the entire system, a digital signal processor for processing data, an instruction storage unit for storing a processing program group of the digital signal processor, data to be processed and processed data. A digital signal in a system including a data storage unit for storing the data, a first register for storing data for designating the processing content of the digital signal processor, and a second register for storing the status of the digital signal processor. A method for checking a program of a processor, comprising a third register for storing data representing all program groups except the first program data from a processing program group written by the central controller, wherein the central controller is configured to store the data. Digital signal Writing the processing program group of the processor into the instruction storage unit, and before starting the processing of the data, the central control unit stores the data for instructing the operation of the first program of the processing program group by the first program. In the third register, and data in the third register, the data representing all program groups except the first program data written from the processing program group written by the central controller. Activating processing, performing processing by the signal processor, reading data in the second register by an output signal from the digital signal processor, the first program by the digital signal processor Was successfully executed. And a step of activating the processing program other than the first program to the digital signal processor, the program confirmation method of the digital signal processor. 12. The execution step comprises a step of performing initialization, a step of reading data written in the third register, and an entire program group except the first program as processing programs in order. The reading process,
Repeating the execution step until the reading of all program groups except the first program is completed, and data representing the configuration of all program groups except the first program based on the data read by the step And the data representing the configuration of all program groups except the first program determined by the step and the third step.
Comparing the data written in the register, and setting the data indicating that the execution of the first program has ended normally in the second register if the comparisons match. A step of outputting an interrupt to the central control unit after the setting of the second register is completed, and in the step of comparing, the data representing the configuration of all program groups except the first program and the third register 12. The program confirmation method for a digital signal processor according to claim 11, wherein when the data written in the data does not match, the data indicating that the processing program has not been written correctly is set in the second register. . 13. A digital signal processor system having a digital signal processor for processing data in response to a command from the central control unit based on a processing program downloaded from the central control unit for controlling the entire system. Then, the central control unit, based on a response from the digital signal processor, a load means for downloading the test program together with the processing program, a command means for issuing a test command, whether the processing program is normally loaded. A digital signal processor system, comprising: a confirmation unit that confirms whether or not the digital signal processor includes an execution unit that executes the test program based on the test command. 14. The digital signal processor according to claim 13, wherein the confirmation means determines that the processing program is not normally loaded when there is no response from the digital signal processor for a predetermined time. system. 15. The confirmation means determines that the processing program is not normally loaded when the response from the digital signal processor is an unexpected response or a response indicating an error. 13. The digital signal processor system according to 13 or 14. 16. The test program includes a series of unconditional branches distributedly inserted in the processing program, and the confirming unit normally executes the series of unconditional branches by the digital signal processor. 14. The digital signal processor system according to claim 13, wherein the absence is judged from the presence or absence of a response from the digital signal processor or an unexpected response, and it is considered that the processing program is not normally loaded. 17. The test program includes an algorithm for confirming a bit error of the processing program, wherein the confirming unit confirms the bit error by the digital signal processor, whether or not there is a response from the digital signal processor, or 14. The method according to claim 13, wherein the processing program is judged not to be loaded normally by judging from a response indicating an error.
6. A digital signal processor system according to item 6. 18. The algorithm is a checksum, and further comprises a holding unit for holding a checksum calculated in advance by the central control unit, and the confirmation unit is a checksum calculated in advance in the central control unit. 18. The digital signal processor system according to claim 17, wherein a bit error is confirmed by comparing with a checksum calculated according to the algorithm by the digital signal processor.