JPH08321783A - Viterbi decoder - Google Patents

Abstract

PURPOSE: To obtain the Viterbi decoder in which accuracy of error correction is enhanced. CONSTITUTION: An equalizer 1 applies waveform equalization to an input signal to convert the signal into a signal with a partial response characteristic. A level controller 2 eliminates level fluctuation of an output signal of the equalizer 1. A converter 3 digitizes an output signal of the level controller 2. A PR equalizer 41 applies waveform equalization to most significant bit data of an output signal of the converter 3 to convert the signal into a signal having a partial response characteristic. A delay device 42 matches a phase of the output signal of the converter 3 with a phase of an output signal of the PR equalizer 41. An adder 43 takes a difference between an output signal of the PR equalizer 41 and an output signal of the delay device 42. A filter 44 extracts a low frequency component of the output signal of the adder 43. Delay devices 45, 46 match a phase of the output signal of the converter 3 with a phase of an output signal of the filter 44. An adder 47 takes a difference between the output signal of the filter 44 and an output signal of the delay device 46. A Viterbi decoding circuit decodes an output signal of the adder 47.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Viterbi decoding device for waveform equalizing input data by a partial response method and detecting the most probable data sequence by utilizing the correlation between the data. The present invention relates to a Viterbi decoding device suitable for use in a magnetic recording / reproducing device, a magneto-optical recording / reproducing device, and the like.

[0002]

2. Description of the Related Art Recently, in a recording / reproducing apparatus such as a digital video tape recorder or an optical disk apparatus, a PRM combining a partial response method and a Viterbi decoding method
L (Partial Response Maximu
The signal processing technique called the m Likelihood method has attracted attention.

That is, the PRML system is a partial response (PR: Parti) method for equalizing the shape of a reproduced waveform.
The maximum likelihood (ML: Maximum Likelihood) is used for data detection by using an al response method.
d) The Viterbi decoding method which is a decoding method is used. By using such a PRML system, the recording density can be increased to about 1.2 to 1.5 times by the signal processing without largely changing the existing recording / reproducing system. Further, the PRML system has a feature that it is possible to equalize the waveform while maintaining a high S / N ratio of the data read from the recording medium, and to secure a data error rate that causes no practical problem. ing.

For example, when digital data is recorded on an optical disk by an optical disk recording / reproducing apparatus using the PRML system, the digital data recorded on the optical disk is reproduced with a frequency characteristic having a high frequency drop due to the characteristics of the head amplifier. To be done.

This reproduced data I (t) is supplied to a Viterbi decoding device as shown in FIG. That is, FIG.
As shown in, the reproduction data I (t) is supplied to the equalization circuit 201 having an arbitrary frequency characteristic, and the equalization circuit 201
Thus, the reproduced data I (t) is converted into output data r (t) having a constant response, that is, an impulse response.
Also, the output data r (t) obtained by the equalization circuit 201
Is an automatic gain control (AGC: Automatic Ga)
in Control) circuit 202. AG
The C circuit 202 outputs the output data r from the equalization circuit 201.
The level fluctuation of (t) is removed, and the output data r (t) from which the level fluctuation is removed is supplied to the analog / digital (A / D) converter 203. The A / D converter 203 converts the output data r (t) from the AGC circuit 202 into digital data r
^It is converted into ^d (t), and the digital data r ^d (t) is supplied to the Viterbi decoding circuit 204.

Here, there are several types of partial responses depending on what kind of intersymbol interference is applied. These methods can be classified by the impulse response of the output data r (t) obtained by the equalization circuit 201, and include PR (1,1) and PR (1,2,1). P
R (1,1) is a method for suppressing noise of high frequency components, and by using this method, the Viterbi decoding circuit 2
The configuration of 04 can be simplified. Also, PR
When (1, 2, 1) is used, the Viterbi decoding circuit 204
Although the configuration is complicated, it is a method that can further improve the S / N ratio. Thus, depending on which method you use,
It is determined which frequency component is emphasized.

Further, since the output data r (t) obtained by waveform equalization by the partial response method has a known impulse response, the original digital data I ( t) can be analogized.

Therefore, the Viterbi decoding circuit 204 detects the most probable data series by effectively utilizing the correlation between the data so that the influence of noise generated during recording and reproduction is minimized. That is, when there is intersymbol interference, the fact that only a limited pattern appears in the data sequence obtained by sampling the reproduction data is used to compare the pattern with the actual sampling result. Detect an error. Then, the pattern most similar to the sampling result is detected and the error is corrected. Further, the pattern that the reproduced data can take depends on not only the inter-code interference but also the recording code. In consideration of such restrictions, the Viterbi decoding circuit 204 improves the accuracy of error correction.

[0009]

By the way, the error correction capability of the Viterbi decoding circuit 204 effectively exerts the effect that the spectrum of noise contained in the digital data r ^d (t) supplied to the Viterbi decoding circuit 204 is effective. Has a characteristic of rising from a white level to a high frequency range. However, as shown in FIG. 10, the Viterbi decoding circuit 204
Directly from the A / D converter 203 to the digital data r ^d
(T) had been supplied. That is, the Viterbi decoding circuit 20
The digital data r ^d (t) supplied to No. 4 was data that was not subjected to noise suppression processing. For this reason,
If the digital data r ^d (t) contains a lot of low-frequency noise components, the error correction capability of the Viterbi decoding circuit 204 may be reduced, and erroneous correction may occur.

Therefore, the present invention has been made in view of the above-mentioned conventional circumstances, and has the following objects.

That is, it is an object of the present invention to provide a Viterbi decoding device with improved error correction accuracy.

[0012]

In order to solve the above-mentioned problems, a Viterbi decoding apparatus according to the present invention is a first waveform equalizing means for equalizing an input signal into a signal having a partial response characteristic. A level control means for removing a level fluctuation of the output signal of the first equalization means, and a conversion means for digitizing the output signal of the level control means.
A noise suppression unit that performs noise suppression processing on the output signal of the conversion unit and a Viterbi decoding circuit that decodes the output signal of the noise suppression unit are provided, and the noise suppression unit includes the Viterbi decoding from the output signal of the conversion unit. A sub-decoding unit capable of more accurately decoding noise in a band in which the circuit is likely to malfunction, and a second decoding unit for re-equalizing the output signal of the sub-decoding unit to a signal having a partial response characteristic. Waveform equalizing means; first delay means for matching the phase of the output signal of the converting means with the phase of the output signal of the second waveform equalizing means; and the output signal of the second waveform equalizing means and the above. First calculating means for obtaining a difference from the output signal of the first delay means, extracting means for extracting a low frequency component of the output signal of the first calculating means, and phase of the output signal of the converting means Second delay means for matching the phase of the output signal of the extracting means, and a difference between the output signal of the extracting means and the output signal of the second delay means, and the difference signal is supplied to the Viterbi decoding circuit. It is characterized by comprising two calculation means.

Further, the Viterbi decoding apparatus according to the present invention is characterized in that the sub-decoding means outputs the most significant bit data of the signal digitized by the converting means as a generation signal.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

A Viterbi decoding apparatus according to the present invention is, for example,
High-frequency signal obtained from a magneto-optical disk (hereinafter, reproduction R
It is called F signal. ) I _a (t) is waveform-equalized by a partial response (PR) method and is decoded by a Viterbi decoding method.
, An equalizer (EQ: Equalizer) 1 that equalizes the waveform of the input reproduction RF signal I _a (t),
Automatic gain control (AGC: Automatic Gain Cont) for eliminating level fluctuations of the output signal of the equalizer 1.
roll) circuit 2, an analog / digital (A / D) converter 3 for digitizing the output signal of the AGC circuit 2, and A / D
A noise suppression unit 4 that performs noise suppression processing on the output signal of the D converter 3 and a Viterbi decoding circuit 5 that decodes the output signal of the noise suppression unit 4 are provided.

The noise suppressing means 4 includes a PR equalizer 41 for waveform equalizing the most significant bit data of the output signal of the A / D converter 3 by a partial response method, and an output signal of the A / D converter 3. Delay circuit (DL) 42 for delaying the phase of
And an adder 43 that takes the difference between the output signal of the PR equalizer 41 and the output signal of the delay circuit 42, and a filter (LPF: L) that extracts the low-frequency noise component of the added output signal of the adder 43.
ow Pass Filter) 44 and a delay circuit (DL) 45 for delaying the phase of the output signal of the A / D converter 3.
A delay circuit (DL) 46 for delaying the phase of the output signal of the delay circuit 45, the output signal of the filter 44 and the delay circuit 4
6 and an adder 47 for calculating the difference from the output signal of No. 6.

The Viterbi decoding apparatus 100 shown in FIG. 1 above.
Is, for example, as shown in FIG.
Applied to the recording / reproducing apparatus of the Viterbi decoding device 10
The reproduction RF signal I _a (t) input to 0 is the data S read from the magneto-optical disk 102 by the reproduction head PD.
(T) is the signal amplified by the reproduction amplifier 103.

Here, on the magneto-optical disk 102, data S (t) to which data compression or error code is added is recorded. The data S (t) has been subjected to precoding processing for preventing the propagation of data errors before recording the data on the magneto-optical disk 102. That is, the data S (t) is pre-added with the inter-code interference, which is the reverse of what is given to the record-encoded data by the recording / reproducing system. As a result, the waveform of the reproduction RF signal I (t) has a one-to-one correspondence with the recording waveform.

The above-described data S (t) is recorded on the magneto-optical disk 102 by the recording head LD driven by the drive circuit 101, and the magneto-optical disk 102 is recorded.
The reproduced RF signal I _a (t) obtained from the above is supplied to the equalizer 1 of the Viterbi decoding device 100.

The equalizer 1 employs, for example, a transversal filter equalization method for waveform equalization using a transversal filter. This transversal filter is, as shown in FIG. 3, a FIR (Finite) digital filter.
It corresponds to an Impulse Response) filter, has delay circuits D _{−N + 1 to} D _N−1 having taps at each pulse transmission time interval T, and weighting factors cn (n = −N, ... ., -1, 0, 1, ..., N)
Gain adjusting circuits C _{-N to} C _N and a gain adjusting circuit C _-N
It is composed of a summing circuit P that adds outputs from -C _N. Further, the number of taps and the weighting coefficient cn of the taps in the transversal filter are designed so that the waveform of the output signal I _b (t) of the equalizer 1 becomes the waveform of PR (1,2,1). ing.

As shown in FIG. 4, the characteristics of PR (1,2,1) are as follows when the peak value of the output signal I _a (t) of the equalizer 1 is standardized by “2”. An amplitude of 1/2 (= 1) appears at the sampling timings before and after. Further, PR (1, 2, 1) has a delay element D for one sampling time as shown in FIG.
D) It can be said that it is a method of giving the characteristics of ² .

The tap weighting coefficient cn is, for example, as shown in FIG. 6, a difference X between the input waveform and the target waveform at each discrimination point.
It is adapted to be updated according to the algorithm of the least square error method (MSE method) so that the total sum of squares of ₁ , X ₂ , X ₃ , ... Is minimized. Further, when updating the tap weighting coefficient cn, the reproduction RF signal I _a (t) is PR
Equalize the waveform while automatically adjusting it so that it is close to the waveform of (1, 2, 1).

In this way, the target waveform PR
Since the equalized output signal I _b (t) obtained by waveform equalization close to (1, 2, 1) is not completely waveform equalized as shown in FIG. 7, an equalization error Δk occurs. ing. The equalized output signal I _b (t) in which such equalization error Δk occurs is A
It is supplied to the GC circuit 2.

The AGC circuit 2 eliminates the level fluctuation of the equalized output signal I _b (t) from the equalizer 1. That is, AGC
The circuit 2 controls the amplitude characteristic and DC component of the equalized output signal I _b (t) to an arbitrary reference level and supplies the same to the A / D converter 3.

The A / D converter 3 converts the signal I _C (t) from which the level fluctuation has been removed by the AGC circuit 2 into, for example, 8-bit digital data I _e (t), and the digital data I _e. (T) is supplied to each of the delay circuit 42 and the delay circuit 45, and the most significant bit (MSB) data I _{d of the} 8-bit digital data I _e (t) as shown in FIG.
(T) is supplied to the PR equalizer 41.

That is, in this embodiment, the most significant bit data I _d (t) is converted into 8-bit digital data I
_The sub-decoding result is different from that of the Viterbi decoding circuit 5 obtained from _e (t). Such a method of obtaining the sub-decoding result by using the most significant bit data I _d (t) is a compact disc (CD: Compact d).
isc) Generally used in players and the like, and is equivalent to a method of comparing reproduced RF signals at the center level.

Here, the sub-decoding result must have a noise band component different from the noise band component affected by the Viterbi decoding circuit 5. Therefore, since the Viterbi decoding circuit 5 has a feature that it is strongly susceptible to the low-frequency noise component, the most significant bit data I _d (t) that is strong against the low-frequency noise component is used as the sub-decoding result. Also, the most significant bit data I _d (t)
Is generally a 10 ^-2 byte error rate (BER: By
te Err Rate).

The PR equalizer 41 employs the transversal filter equalization method as in the above-described equalizer 1, and the most significant bit data I from the A / D converter 3 is applied.
Waveform equalization is performed on _d (t) so as to have a target PR (1, 2, 1) characteristic. The waveform equalization processing in the PR equalizer 4 is the same as the waveform equalization processing in the equalizer 1, and the details thereof will be omitted. That is, the PR equalizer 41
Converts the most significant bit data I _d (t) into ideal 8-bit digital data I _f (t) having the target PR (1, 2, 1) characteristic as shown in FIG. The digital data I _f (t) is supplied to the adder 43. here,
The digital data I _f (t) usually contains an error of about 10 ⁻² BER or less.

On the other hand, the delay circuit 42 is composed of a shift register and has the digital data I from the A / D converter 3.
_e (t) is delayed by a time equal to the delay amount of the PR equalizer 41, and the phase difference from the digital data _If (t) output from the PR equalizer 41 is set to "0". Then, the delay circuit 42 supplies the delayed digital data I _g (t) to the adder 43.

The adder 43 takes the difference between the digital data I _g (t) from the delay circuit 42 and the digital data I _f (t) from the PR equalizer 41. That is, the noise component I _h (t) of the signal I _C (t) supplied to the A / D converter 3 is obtained by subtracting the digital data I _g (t) from the digital data I _f (t). However, this noise component I)
Contains an error equivalent to 10 ^-2 BER. Here, the noise component I _h (t) is 10 ⁻² generated in the PR equalizer 41.
The error is less than BER, but this error is
Due to the characteristics of the most significant bit data I _d (t), it is assumed that a high frequency component is included in a large amount and a low frequency noise component is small. Such noise component I _h (t) is supplied to the filter 44.

The filter 44, the low-frequency noise components I _i (t) extracted from the noise component I _h from the adder 43 (t), and supplies the low-frequency noise components I _i (t) to the adder 47 .

On the other hand, the delay circuit 45 has the same delay amount as the delay circuit 42 described above, and delays the digital data I _e (t) from the A / D converter 3 by a time equal to the delay amount. , The delayed digital data I _e (t) is supplied to the delay circuit 46 at the next stage.

The delay circuit 46 is equal in time to the digital data I _e (t) from the delay circuit 45 at the preceding stage to coincide with the inter-axis axis of the low band noise component I _i (t) output from the filter 44. Delayed and delayed low-frequency noise component I
_i (t) is used as the low-frequency noise component I _j (t) in the adder 47.
Supply to.

The adder 47 takes the difference between the digital data I _e (t) from the delay circuit 46 and the low band noise component I _j (t) from the filter 44. That is, the digital data I
By subtracting the low-frequency noise component I _j (t) from _e (t), the Viterbi decoding circuit 5 generates data I _k (t) containing a large amount of high-frequency noise component that exerts a powerful effect, and the data I _k (t) is generated. _{The k} (t) is supplied to the Viterbi decoding circuit 5.

The Viterbi decoding circuit 5 detects the most probable data series on the basis of the data I _k (t) from the adder 47.

For example, the partial response characteristic is PR
The operation of the Viterbi decoding circuit 5 in the case of (1, 2, 1) will be described below.

As described above, PR (1,2,1) is affected by intersymbol interference over three sampling periods. Therefore, assuming that there is no noise source, the sampling value s (t) at a certain time is the data Sd (t) corresponding to a certain time and the data [Sd (t−2), Sd (at the past two sampling times. t-1)]. A combination of data at the past two sampling times is called a state. A timeless series of state transitions is called a retres diagram. FIG. 10 shows a PR (1,2,1) retreat diagram. In this retres diagram, the numbers next to the arrow are data at the time of the end point of the arrow. Further, the ideal sampling value y (k) that does not include noise for each transition state (that is, arrow) from time k−1 to time k is determined by the partial response characteristic. FIG. 11 shows y (k) in PR (1,2,1)
Indicates the value of. When the actual sampling value at the transition from time k-1 to time k is s (k), the probability of assuming that the transition is a certain transition state on the retres diagram It is called the branch metric of the state (that is, arrow). As a specific evaluation value of the branch metric, for example, {y (k) -s (k)} ²
To use. In this case, the smaller the branch metric, the higher the degree of certainty. A certain data series is represented as one path on the retres line. The sum of the branch metrics on this path is called the path metric of that path, and represents the certainty of the data series corresponding to that path. The Viterbi decoding circuit is a circuit that obtains a path having a minimum path metric and outputs a data series corresponding to this path.

A specific configuration of the Viterbi decoding circuit 5 is shown in the block diagram of FIG. That is, the Viterbi decoding circuit 5
Is a branch metric calculation circuit 51 and ACS (Ad
d, Compare, Select) circuit 52 and a path memory circuit 53.

The branch metric calculation circuit 51 calculates a branch metric corresponding to each state transition.

The ACS circuit 52 is a path metric memory for storing the path metric reaching each state at the time k−1, a circuit for adding a branch metric to the path metric at the time k−1 according to the Retres diagram, and at the time k. It is provided with a circuit for comparing the magnitudes of the combined path metrics and a circuit for selecting a path metric having a smaller value according to the comparison result. The selected value updates the path metric memory as a new path metric. The paths selected by the ACS circuit 52 in this way are only the number of states (4 in the case of PR (1,2,1)) at the current time, but these paths are called surviving paths. If you follow the surviving paths in the past, you will end up in one path at some point. Before this point, it is the part that has been determined as the path that minimizes the path metric.

The path memory circuit 53 is the ACS circuit 5 described above.
The survivor path is stored according to the result selected by 2, and the most probable data series corresponding to the determined path is output.

As described above, in the present embodiment, the data I in which the low frequency noise component is suppressed by the noise suppressing means 4 is used.
_{Since k} (t) is supplied to the Viterbi decoding circuit 5, the defect of the Viterbi decoding circuit 5 that is easily affected by the low-frequency noise component can be compensated for, and the error correction capability of the Viterbi decoder 5 efficiently exhibits its effect. can do.

The present invention can be applied not only to the Viterbi decoding device as described above, but also to a decoding device in which two decoding circuits having different effects depending on the noise band are combined. For example, a decoding circuit that is resistant to low band noise components may be used as the sub decoding circuit for obtaining the sub decoding result, and a decoding circuit that is resistant to high band noise components may be used instead of the Viterbi decoding circuit 5. In this way, since a decoding circuit effective for each noise band can be selected and used, the carrier to noise ratio (C / N: Carrier to Noise ratio) can be selected.
Even when decoding a reproduced RF signal with bad io), the same decoded output as in the conventional case can be obtained. Therefore, information can be recorded on the magneto-optical disk or the like with higher density.

That is, for an input signal with a poor C / N, B
Since a decoded signal with a low ER can be obtained, it is effective for a recording / reproducing device with an increased recording density. Further, since the decoding efficiency of the Viterbi decoding circuit can be theoretically increased beyond the limit, it is possible to widen the application range of the Viterbi decoding device to which the PRML method in which the partial response method and the Viterbi decoding method are combined is applied.

In the above-described embodiment, the sub-decoding result has a noise band component different from the noise band affected by the Viterbi decoding circuit 5.
The present invention is not limited to this, as long as the Viterbi decoding circuit 5 has a strong component with respect to the noise band in which malfunction easily occurs.

[0046]

In the Viterbi decoding device according to the present invention, the first
The waveform equalizing means of (3) equalizes the input signal and converts it into a signal having a partial response characteristic. The level control means removes the level fluctuation of the output signal of the first equalization means. The conversion means digitizes the output signal of the level control means. The sub-decoding means generates a noise signal in a band in which the Viterbi decoding circuit easily malfunctions from the output signal of the converting means. The second waveform equalizing means re-equalizes the output signal of the sub-decoding means and converts it into a signal having a partial response characteristic. The first delay means is
The phase of the output signal of the converting means is matched with the phase of the output signal of the second waveform equalizing means. The first calculation means calculates the difference between the output signal of the second waveform equalization means and the output signal of the first delay means. The extraction means extracts the low frequency component of the output signal of the first calculation means. The second delay means matches the phase of the output signal of the converting means with the phase of the output signal of the extracting means. The second calculation means calculates the difference between the output signal of the extraction means and the output signal of the second delay means. The Viterbi decoding circuit decodes the output signal of the second arithmetic means. Since the Viterbi decoding circuit is supplied with the signal in which the low frequency noise component is suppressed, the effect of the error correction capability of the Viterbi decoding circuit can be efficiently exhibited. Therefore, the accuracy of error correction can be improved.

In the Viterbi decoding device according to the present invention,
The sub-decoding means outputs the most significant bit data of the signal digitized by the converting means as a generation signal. Since the most significant bit data is data that is less likely to be affected by low-frequency noise components, a signal having a noise band different from the noise band of the output signal of the Viterbi decoding circuit is generated from the output signal of the conversion means. You can

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a Viterbi decoding device according to the present invention.

FIG. 2 is a block diagram showing a configuration of a recording / reproducing system of a magneto-optical disk to which the Viterbi decoding device is applied.

FIG. 3 is a block diagram showing a configuration of a transversal filter.

FIG. 4 is a waveform diagram for explaining characteristics of an equalizing circuit in PR (1,2,1).

FIG. 5 is a circuit diagram for explaining characteristics of an equalizing circuit in PR (1, 2, 1).

FIG. 6 is a waveform diagram for explaining the least square error method.

FIG. 7 is a waveform diagram showing a signal in which an equalization error has occurred.

FIG. 8 is a waveform chart showing most significant bit data.

FIG. 9 is a waveform diagram showing a signal having a target waveform characteristic.

FIG. 10 is a retres diagram of PR (1,2,1).

FIG. 11 is a diagram showing values of y (k) in PR (1,2,1).

FIG. 12 is a block diagram showing a specific configuration example of a Viterbi decoding circuit.

FIG. 13 is a block diagram showing a configuration of a conventional Viterbi decoding device.

[Explanation of symbols]

 1 Equalizer 2 AGC circuit 3 A / D converter 4 Noise suppression means 5 Viterbi decoding circuit 41 PR equalizer 42, 45, 46 Delay circuit 43, 47 Adder 44 Filter 100 Viterbi decoding device

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H04L 25/08 9199-5K H04L 25/08 B

Claims (2)

[Claims] 1. A first waveform equalization means for equalizing an input signal into a signal having a partial response characteristic, and a level control means for removing a level fluctuation of an output signal of the first equalization means. A conversion means for digitizing the output signal of the level control means, a noise suppression means for performing noise suppression processing on the output signal of the conversion means, and a Viterbi decoding circuit for decoding the output signal of the noise suppression means, The noise suppressing means is a sub-decoding means capable of more accurately decoding the output signal of the converting means with respect to noise in a band in which the Viterbi decoding circuit is likely to malfunction, and a waveform of the output signal of the sub-decoding means. Second waveform equalizing means for re-equalizing and converting to a signal having a partial response characteristic, and the phase of the output signal of the converting means for the second waveform equalizing means. First delaying means for adjusting the phase of the output signal of the stage, first computing means for taking a difference between the output signal of the second waveform equalizing means and the output signal of the first delaying means, Extracting means for extracting a low-frequency component of the output signal of the first calculating means; and second delay means for matching the phase of the output signal of the converting means with the phase of the output signal of the extracting means.
A Viterbi decoding device comprising: a second arithmetic means for calculating a difference between an output signal of the extracting means and an output signal of the second delay means and supplying the difference signal to the Viterbi decoding circuit. 2. The Viterbi decoding apparatus according to claim 1, wherein the sub-decoding means outputs the most significant bit data of the signal digitized by the converting means as a generation signal.