JP2001344903A - Digital information reproducing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital information reproducing device capable of performing precise filter parameter learning while suppressing the increase of power consumption. SOLUTION: A maximum likelihood deciding part 507 outputs the second discrimination result d2, which has small delay though a discrimination error ratio is high as the result of comparing it with a discrimination result d1 in addition to the result d1 sent to a decoder 508. An error signal generation part 510 generates an error signal e4 from the result d2 and the output of a digital equalizer 506. A filter parameter learning part 511 learns the filter parameter of the equalizer 506 from the signal e4.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital information reproducing apparatus for reading digital data from a recording medium, and more particularly to a digital information reproducing apparatus provided with a maximum likelihood estimator using a Viterbi decoder.

[0002]

2. Description of the Related Art In recent years, digital information reproducing devices such as magnetic disk devices, magnetic tape devices, optical disk devices, and magneto-optical disk devices have realized partial response (PR: Pa).
(rtialResponse) method is widely used. This is a recording medium for recording digital information (magnetic disk, magnetic tape, optical disk, magneto-optical disk, etc.)
As the recording density of the digital data increases, the performance of the conventional method of recording digital information makes it difficult to write a waveform for recording one bit of digital information without the influence (waveform interference) of recording adjacent bits. It depends.

The partial response method is to prevent signal performance from being degraded due to the equalization decoding process by positively producing known waveform interference in the waveform equalization processing unit. By combining such a partial response method with an ML (Maximum Likelihood) method that is a maximum likelihood estimation method, PRML that enables highly accurate signal processing
(Partial Response Maximum Likelihood) method is also in practical use.

[0004] In the PRML system, many systems are produced from the form of the given waveform interference. In particular, in magnetic disk drives, PR (1,1, -1, -1) (EPRML: Extended PRML), P
A class 4 PRML system such as R (1,2,0, -2, -1) (EEPRML: Extended EPRML) is used. For a signal processing method of the PRML system in a magnetic disk, for example, see the document: IEEE Transactions on Magnetics, Sep. 199.
9, Vol. 35, Num. 5, pp. 4378-4386, “Rate 16/17 Maximu
m Transition Run (3; 11) Code on an EEPRML Channel
with an Error-Correcting Postprocessor ".

On the other hand, in an optical disk device, PR (1,1), PR (1,1)
A method such as (1,2,2,1) is used. Regarding a PRML-based signal processing method in an optical disk device, see, for example, JP-A-9-17130 and JP-A-10-11.
No. 2030.

[0006] These PRML-based signal processing methods are based on PR
Compared to a method that does not use the ML signal processing method, that is, a method that performs a decoding operation without giving waveform interference, high-precision signal processing is possible, and the recording performance of an apparatus equipped with the signal processing unit is improved. Can be improved.

In such a digital information reproducing apparatus using the PR system, a signal reproduced from a recording medium is used to remove waveform interference, limit a signal band, and produce desired waveform interference. Filter means are required.

FIG. 10 is a diagram showing a configuration of a signal processing unit 100 in a conventional magnetic disk drive.

As shown in FIG. 1, digital information written on a recording medium is read from a head 101 and amplified by an amplifier 102. The amplified signal is adjusted by a variable gain amplifier (VGA) 103 to have an appropriate amplitude, and sent to an analog filter (AF) 104. The AF 104 includes a downstream A / D converter (ADC) 1
05 removes high frequency components of a signal that becomes noise when being sampled. Note that the AF 104 may perform waveform equalization so that desired waveform interference can be easily generated by an equalizer at a subsequent stage.

The analog signal from which the high frequency component has been removed is
The signal is converted into a digital signal by the ADC 105. This digital signal is subjected to waveform equalization in an n-tap transversal digital equalizer (DEQ) 106. The waveform-equalized signal has known waveform interference, and the maximum likelihood estimating unit 107 performs maximum likelihood decoding.
The decoded value is subjected to a decoding process by the decoder 108 to become user data, and becomes an output of the signal processing unit 100. The output of the signal processing unit 100 is transmitted to a host such as a computer outside the magnetic disk device via a hard disk controller (HDC) and an interface (not shown).

The output signal of the DEQ 106 is input to a decision unit 109. The decision unit 109 makes a temporary decision for producing an error signal, and outputs a decision result. The error signal generation unit 110 generates an error signal e1 using the determination result of the determiner 109 and the output signal of the DEQ 106.

[0012] The filter parameter learning unit 111 includes an error signal e1 obtained from the error signal generation unit 110 and DEQ1.
The parameter of the DEQ 106 is changed using information such as the input of 06.

FIG. 11 is a diagram showing a configuration of a signal processing unit 200 in a conventional optical disk device.

As shown in FIG. 1, digital information written on a recording medium is transmitted to an optical pickup (optical head) 2.
01 and amplified by the preamplifier 202. The amplified signal is supplied to a variable gain amplifier (VGA) 20.
The signal is adjusted to have an appropriate amplitude by 3 and sent to an analog filter (AF) 204. The AF 204 removes high-frequency components that become noise when being sampled by an A / D converter (ADC) 205 at the subsequent stage. In addition,
The AF 204 may perform waveform equalization so that desired waveform interference is easily generated by an equalizer at a subsequent stage.

The analog signal from which the high frequency component has been removed is
The signal is converted into a digital signal by the ADC 205. This digital signal is subjected to waveform equalization by a digital equalizer (DEQ) 206. It should be noted that the DEQ 206 may not be needed in a device in which the waveform equalization is sufficiently performed by the AF 204.

A known waveform interference is generated in the signal subjected to the waveform equalization, and the maximum likelihood estimation unit 207 performs maximum likelihood decoding. The decoded value is subjected to a decoding process by the decoder 208 to become user data, and becomes a user data.
Output. The output of the signal processing unit 200 is transmitted to a host such as a computer outside the optical disk device via an optical disk controller (ODC) and an interface (not shown).

The output signal of the DEQ 206 is
09, the judgment unit 209 makes a temporary judgment for generating an error signal, and outputs a judgment result.
Error signal generation section 210 generates error signal e2 using the determination result of determiner 209 and the output signal of DEQ 206.

The filter parameter learning section 211 has the error signal e2 obtained from the error signal generation section 210 and the DEQ2
The parameter of the DEQ 206 is changed using information such as the input of 06.

[0019]

When signal processing such as PRML is performed, the signal-to-noise ratio of the signal input to the signal processing unit is lower than when no such signal processing is performed. The error rate of the determination result in 209 becomes relatively high. When the error rate of the output of the maximum likelihood estimating unit is constant, the increase in the decision error rate is caused by the fact that the PR method used is E
The more complicated the waveform interference given to PRML and EEPRML becomes, the more remarkable it becomes.

When the quality of the input signals of the decision units 109 and 209 is sufficiently high, even if the error of the error signal is temporarily deteriorated due to an error in the judgment result, the error signal at the time when the error does not occur thereafter is used. Since the progress of filter learning in an erroneous direction is limited, the signal error rate at the output of the signal processing unit is unlikely to deteriorate.

However, when the quality of the input signal of the decision units 109 and 209 is significantly deteriorated due to deterioration of the performance of the signal recorded on the medium, increase of noise in the signal processing unit, and setting error of the parameter in the signal processing unit. The signal error at the output of the signal processing unit until the learning result returns to a point near the optimal setting until the quality of the temporary error signal causes the filter parameters to learn at a point away from the optimal setting. The rate is increased, and the performance of the entire apparatus is degraded.

Further, the quality deterioration of the temporary error signal as described above causes the filter parameters to be learned at a point away from the optimum setting, thereby causing the quality deterioration of the input signals of the decision units 109 and 209, and This leads to a false decision error, which leads to further deterioration of the quality of the error signal. When such a phenomenon occurs, the error rate of the signal at the output of the signal processing unit increases, and the performance of the entire device further deteriorates.

FIG. 12 is a diagram showing the distribution of the equalized signal at the time of the decision unit 109 in the magnetic disk using the PR (1,0, -1) ML method. In the example shown in the figure, the equalized signal is {1,
0, -1}, and equalization is performed, but in the hatched portion, in a simple determination such as signal level discrimination,
Make a decision error. This decision error rate is at least several times greater than the decision error rate of the ML section, and the stability of the learning of the filter parameters decreases.

In order to solve such a problem, a method of updating filter parameters using a signal after maximum likelihood decoding has been considered.

FIG. 13 is a diagram showing a configuration of a signal processing unit 400 in a magnetic disk device adopting a method using a signal after maximum likelihood decoding for updating a filter parameter. In the figure, components denoted by the same reference numerals as those described above have similar features.

As shown in FIG. 1, the digital information written on the medium includes a head 101, an amplifier 102, a VGA 1
03, the AF 104, the ADC 105, the DEQ 106, and the maximum likelihood estimating unit 407 sequentially process and decode. The determination result output from the maximum likelihood estimator 407 has a lower determination error rate and higher quality than the determination result of the determiner 109 in FIG.

The delay unit 412 generates a DEQ output signal corresponding to the determination result of the maximum likelihood estimating unit 407.
The output of the EQ 106 is delayed by an appropriate number of clocks. The error signal generation unit 410 generates an error signal e3 using the determination result of the maximum likelihood estimation unit 407 and the output signal of the delay unit 412.

The filter parameter learning section 411 includes the error signal e3 obtained from the error signal generation section 410 and the signal DEQ1.
The parameter of the DEQ 106 is changed using information such as the input of 06.

In the signal processing section 400 shown in FIG. 13, the possibility that the filter parameter is learned to be improperly set due to a determination error is reduced. Accordingly, performance degradation due to an increase in the decision error rate of the entire apparatus, such as the induction of continuous decision errors, is unlikely to occur.

However, there is a large delay from when the equalized output is input to the maximum likelihood estimating section 407 to when the estimation result is output. For example, the ACS (Add-Co
A delay of several tens of clocks is expected in a circuit such as a mpare-select circuit and a path memory. In this case, the delay unit 412 needs to have a delay circuit having a size of DEQ output bit width × number of delay stages. When the filter parameter learning unit 411 needs to input the DEQ 106 at the time of learning the filter parameter, the filter parameter learning unit also needs to include a delay circuit having a size of DEQ input bit width × number of delay stages. is there. With these circuits,
The circuit size increases, and the power consumption of the entire device increases.

An object of the present invention is to provide a digital information reproducing apparatus capable of performing highly accurate filter parameter learning while suppressing an increase in power consumption.

[0032]

A digital information reproducing apparatus according to the present invention comprises an analog filter for limiting a band of an analog reproduced signal reproduced from a recording medium, and an A filter for converting an output signal of the analog filter into a digital signal. A / D converter, a digital equalizer for equalizing the output of the A / D converter to provide waveform interference for realizing a partial response method, and a maximum likelihood estimation from the signal equalized by the digital equalizer. A maximum likelihood estimator to perform;
A decoder for decoding user data recorded on a recording medium from an output of the maximum likelihood estimating unit; an error signal generating unit for generating an error signal from an output of the digital equalizer; and a digital equalizer for generating an error signal from an output of the error signal generating unit. And a filter parameter learning unit that learns filter parameters of the following. The maximum likelihood estimation unit outputs a second determination result separately from the determination result sent to the decoder, and the error signal generation unit And generating an error signal from the result of the determination and the output of the digital equalizer.

In this case, the maximum likelihood estimating unit includes a metric operation unit for generating metric and path selection information, a path memory for holding a path selection result output from the metric operation unit, The second step is performed using the contents of the memory in the previous stage and the metric.
May be provided.

Further, the maximum likelihood estimating unit includes first and second metric calculation units for generating metric and path selection information, and a path selection result output from the first and second metric calculation units. First and second path memories to be held, wherein the first metric operation unit and the first path memory output a determination result of maximum likelihood estimation, and the second metric operation unit and the second path memory The second path memory may output the second determination result, and the length of the second path memory may be shorter than the length of the first path memory.

Further, in the above case, the digital information reproducing apparatus may include a terminal for outputting error signal information outside the apparatus. The error signal information corresponds to, for example, an error signal output from the error signal generation unit and information obtained by integrating the error signal. The filter parameter learning unit may include a register capable of performing filter parameter adjustment.

In the digital information reproducing apparatus, the user data may be recorded on the recording medium.

[0037]

Embodiments of the present invention will be described below in detail with reference to the drawings. Note that components having the same reference numerals as those already described are assumed to perform the same operation, and the description of the operation will be omitted.

<< First Embodiment >> FIG. 1 is a block diagram showing a configuration of a signal processing section of a digital information reproducing apparatus according to the present invention. In the following, a case will be described in which the present digital information reproducing apparatus employs the PR (1, 0, -1) ML system, but the same applies to other PRML systems.

As shown in the figure, the signal processing section 500
Amplifier 502, VGA 503, AF 504, AD
It includes a C505, a DEQ 506, a maximum likelihood estimating unit 507, a decoder 508, an error signal generating unit 510, a filter parameter learning unit 511, and delay units 512 and 513.

The digital information written on the recording medium is
It is read from a head, a pickup, etc., and thereafter, the amplifier 502, the VGA 503, the AF 504, the
The processing is sequentially performed by the DEQ 506, and the maximum likelihood decoding is performed by the maximum likelihood estimating unit 507 in the same manner as in the method described above.

The decision result d1 by the maximum likelihood estimating unit 507 is
The decoding process is performed by the decoder 508 and the signal processing unit 5
00 is output. The maximum likelihood estimating unit 507 determines the judgment result d1
And a second determination result d2 is generated. The second decision result d2 has a property that the decision error rate is higher than the decision result d1, but the clock delay with respect to the input of the maximum likelihood estimator 507 is small. A method for generating the second determination result d2 will be described later.

The delay unit 512 delays the output signal of the DEQ 506 by the clock delay time in the maximum likelihood estimating unit 507 so as to correspond to the second determination result d2. Error signal generation section 510 outputs DE delayed by delay unit 512.
An error signal e4 is generated using the output of Q506 and the second determination result d2.

The delay unit 513 converts the input signal of the DEQ 506 into the “maximum likelihood estimator 50” so as to correspond to the error signal e4.
7, the clock delay time + the processing time of the error signal generator 510 ".

The filter parameter learning unit 511 changes the parameters of the DEQ 506 using the input of the DEQ 506 delayed by the delay unit 513 and the error signal e4.

Next, the configuration of the error signal generator 510 will be described. FIG. 2 is a block diagram illustrating a configuration of the error signal generation unit 510.

As shown in FIG.
Includes a target amplitude generator 601 and a subtractor 602.

There are cases where the signal level of the second determination result d2 input to error signal generating section 510 is different from the signal level of the output of delay element 512, in which case it is necessary to adjust the signal level to the same level. The output of the maximum likelihood estimating unit 507 is a binary signal representing a write current in order to reduce the number of bit widths of the path memory in the maximum likelihood estimating unit. Therefore, the second determination result d2 must be consistent with the PR (1,0, -1) equalization result. Therefore, the target amplitude generation unit 601 performs an operation of convolving a known waveform equalization suitable for the used partial response method. in this case,
The interference convolved by the target amplitude generation unit 601 is (1-D)
(1 + D) (1 + D) is sufficient. The output of the target amplitude generator 601 is subtracted by the subtractor 602 from the output of the delay unit 512 to become an error signal e4.

Next, the configuration of the filter parameter learning section 511 will be described. FIG. 3 is a block diagram illustrating a configuration of the filter parameter learning unit 511.

As shown in the figure, the filter parameter learning section 511 comprises (n-1) delay units 701_1 to 701
1_ (n−1) and n multipliers 702_1 to 702_
n, n integrators 703_1 to 703_n, n determiners 704_1 to 704_n, a register 705,
And a multiplexer 706.

The output of the delay unit 513 input to the filter parameter learning unit 511 is output from the delay units 701_1 to 701
_ (N-1), and the multipliers 702_1-7
02_n is multiplied by the error signal e4. The multiplication results are integrated by integrators 703_1 to 703_n, respectively. The integration period of each integrator is set in register 7
05. The set value of the register 705 is provided, for example, from the outside of the filter parameter learning unit 511.

Each of the integrators 703_1 to 703_n
Are subjected to level determination by the determiners 704_1 to 704_n. The result of the determination by the determiner 704 is transmitted through a multiplexer (MUX) 706 to the DEQ 50.
Sent to 6. The n determination results bundled by the MUX 706 are used to update each filter parameter of the n-tap transversal filter in the DEQ 506.

The criterion of the decision unit 704 is such that when the integration result exceeds a certain threshold value by an absolute value, the coefficient of the DEQ 506 is set so as to slightly change in the direction in which the integration result exceeds the threshold value. I just need. Note that the threshold value of the determiner may be changed by a set value of the register 705. Also, in order to adjust learning more accurately,
What is necessary is just to make it the input / output of the determiner become a step function as shown in FIG.

Next, the configuration of the maximum likelihood estimating section 507 for generating the second judgment value d2 will be described.

FIG. 5 is a block diagram showing a configuration of maximum likelihood estimating section 507.

As shown in the figure, the maximum likelihood estimator 507
Metric calculation unit 801, path memory 802, ML
Selectors 803 and 804 are provided.

The metric calculation unit 801 includes the maximum likelihood estimation unit 5
The Euclidean distance between the signal value input to 07 and the target signal value corresponding to each branch of the trellis transition is calculated at each time.
Then, the metric calculation unit 801 calculates the path metric value of the most probable path among the paths that reach the current state at each time, selects the state one time before the surviving path, and returns the estimation result according to the selection to the path. Memory 80
2 is stored.

The path memory 802 has the same number of shift registers as the number of states of the PRML system used. Each shift register holds a predetermined number of estimation results while shifting each time. The estimation result output from the metrics calculation unit 801 is stored in the forefront stage of the shift register, and accordingly, the estimation result held internally is shifted by one time. However, at the time of the shift, the estimation result held in the shift register corresponding to the state one time before the selected surviving path is copied. As a result, if the number of surviving paths gradually decreases due to the selection of paths involved in the estimation, the number of copies increases, and the estimation results remaining in the final stage of the plurality of shift registers in the path memory are almost the same.

The ML selector 803 includes a path memory 802
Is calculated using the contents of the last stage of the above and the path metric value of the most probable path output from the metric operation unit 801, and is used as the output (judgment value d 1) of the maximum likelihood estimation unit 507. When the path memory length of the path memory 802 is sufficiently long, the ML selector 803 is not required.

The ML selector 804 is an ML selector 80
3 is a block that performs the same operation as that of the path memory 80.
2, not the final stage, but the decoding estimated using the contents of the intermediate stage of the path memory 802 (ie, the intermediate stage of the shift register) and the path metric value of the most probable path output from the metric operation unit 801. Calculate the value,
It is output as the second determination value d2. Second determination value d2
Is more likely to cause a decision error than the decision value d1, but the clock delay with respect to the input of the maximum likelihood estimator 507 is small. Also, the decision units 109 and 2 which have not performed the maximum likelihood decision
The probability of making a decision error is lower than that of the output of the step S09. As for a specific position of the intermediate stage of the path memory, an appropriate position is selected according to a required error rate and other mounting conditions.

In the digital information reproducing apparatus configured as described above, as compared with the digital information reproducing apparatus shown in FIGS. 10 and 11, the filter parameter learning unit does not operate even under the condition that the SN ratio of the reproduced signal is low. The likelihood of being learned properly is reduced.

Therefore, appropriate parameters are set during adaptive learning, and decoding can be performed at a good error rate. That is, it is possible to reduce the error rate of the reproduced signal, increase the reliability of the device, and further increase the recording density. Alternatively, it is possible to reduce the permissible specification of the performance of components other than the signal processing unit such as the medium, the head, the pickup, and the motor while securing the same data error rate as the conventional one.

Further, in the digital information reproducing apparatus configured as described above, the delay circuit amount of the delay device for delaying the output of the digital equalizer and the like is smaller than that of the digital information reproducing apparatus shown in FIG. You can do it. This makes it possible to reduce the power consumption of the digital information reproducing apparatus without deteriorating the decoding error rate.

<< Second Embodiment >> Next, another configuration method of the maximum likelihood estimating unit 507 will be described.

FIG. 6 is a block diagram showing another configuration of the maximum likelihood estimating unit.

As shown in the figure, the maximum likelihood estimator 507a
Is a waveform interference generation unit 901 and a metric calculation unit 90
2, 905, path memories 903 and 906, and ML selectors 904 and 907. Maximum likelihood estimator 507a
Differs from the maximum likelihood estimating unit 507 shown in FIG. 5 in that two types of partial responses are used.

The waveform interference generation section 901 includes the maximum likelihood estimation section 50
Waveform interference having a longer response than the waveform interference given to the input signal 7a is given to the input signal. For example, when the input of the maximum likelihood estimating unit 507a is given an interference of PR (1,0, -1) ML, the maximum likelihood estimation of the subsequent stage uses EPR (1,1, -1, -1) ML. When used, the waveform interference of (1 + D) which is insufficient so that the waveform interference of the input signal matches the design value of the maximum likelihood estimator is given.

The signal subjected to the waveform interference by the waveform interference generator 901 is input to the metric calculator 902. The metric calculator 902 calculates the Euclidean distance between the input signal value and the target signal value corresponding to each branch of the trellis transition every time. Then, the metric operation unit 9
In step 02, the path metric value of the most probable path among the paths reaching the current state at each time is calculated, the state one time before the surviving path is selected, and the estimation result according to the selection is stored in the path memory 903. .

The path memory 903 includes a shift register for holding the estimation result output from the metric operation unit 902, similarly to the above-described path memory 802, and performs the same shift operation as the above-described path memory 802.

The ML selector 904 includes a path memory 903
Is calculated using the contents of the last stage of the above and the path metric value of the most probable path output from the metric calculation unit 902, and is used as the output (judgment value d1) of the maximum likelihood estimation unit 507a. If the path memory length of the path memory 903 is sufficient, the ML selector 904 is not required.

The metric calculator 905, the path memory 90
6 and the second maximum likelihood estimator by the ML selector 907 are as follows:
The decoding operation is performed using a simpler partial response having a smaller number of states as compared with the maximum likelihood estimating unit including the metric operation unit 902, the path memory 903, and the ML selector 904.

The metric calculator 905 calculates the Euclidean distance between the input signal value and the target signal value corresponding to each branch of the trellis transition at each time. Then, the metric calculation unit 905 calculates a path metric value of the most probable path among paths reaching the current state at each time, selects a state one time before the surviving path, and outputs an estimation result according to the selection to the path. The data is stored in the memory 906.

The path memory 906 has a shift register for holding the estimation result output from the metric operation unit 905, similarly to the above-described path memory 802, and performs the same shift operation as the above-described path memory 802. Note that the length of the path memory 906 (the number of stages of the shift register) is shorter than the path memory 903.

The ML selector 907 includes a path memory 906
Of the last stage and the path metric value of the most probable path output from the metric calculation unit 905, to calculate an estimated decoded value, and output the calculated decoded value as a second determination value d2.

In this case, the second judgment value d2 is also equal to the judgment value d.
Compared with 1, the probability of making a decision error is high, but the delay time during processing in the maximum likelihood estimator is short. Also, the second determination value d2 is determined by the determiners 109 and 2 that have not performed the maximum likelihood determination.
Compared with the output of 09, the probability of making a decision error is low. That is, the same effects as those of the first embodiment can be obtained.

<< Third Embodiment >> FIG. 7 is a block diagram showing another configuration example of the signal processing unit in the digital information reproducing apparatus according to the present invention.

As shown in FIG.
Is a monitor terminal 100 for monitoring the quality of the error signal e4 from outside the device to the signal processing unit 500 shown in FIG.
1 is added.

Further, there is provided an adjusting mechanism for changing the set value of the register in the filter parameter learning unit 511 and the parameter of the DEQ 506 in accordance with the quality of the error signal e4 output from the monitor terminal 1001. That is, the filter parameter and the set value of the register in the filter parameter learning unit 511 can be changed by the adjustment signal given from outside the apparatus.

The signal processing unit 100 configured as described above
The digital information reproducing apparatus having 0 has the same effects as the digital information reproducing apparatus described above, and the signal processing unit 10
It is possible to easily perform an initial setting operation for matching the characteristics of each block of the digital information reproducing apparatus other than the signal processing section 1000 with the blocks of the digital information reproducing apparatus. Further, it becomes easy to reset when the property of the equalizer needs to be changed due to a change in the property of the medium.

In the example shown in FIG. 7, the error signal e4
Is output directly to the outside, but an integrator may be provided in the preceding stage of the monitor terminal 1001 to output the result of integrating the error signal e4.

Next, the configuration of a magnetic disk drive using the above-described signal processing unit will be described.

FIG. 8 is a diagram showing the configuration of a magnetic disk drive according to the present invention. As shown in the figure, the magnetic disk drive 1100 includes a magnetic disk 1101 on which data is written, a spindle 1102 for rotating the magnetic disk 1101, a magnetic head 1103 for reading and writing data from the magnetic disk 1101. ,
Arm 1104 for supporting magnetic head 1103, and voice coil motor 1 for moving magnetic head 1103
105 and a spindle motor 1106 for rotating the spindle 1102.

Further, as other control units, an interface (I / F) 1109 for connecting to the information processing device (host) 1108 and a hard disk controller (HDC) for controlling data transfer and format, etc. 1110 and a microcomputer (CPU) 11
11, a signal processing unit 1107 for processing signals from the magnetic head 1103, a spindle control circuit (SMC) 1112 for controlling the spindle motor 1106, and a voice coil motor control circuit (VCMC) for controlling the voice coil motor 1105. 1113.

Here, the signal processing section 1107 has the same configuration as any of the above-described embodiments. Therefore, the error rate of a signal with poor performance, such as the SN ratio, read from the magnetic disk 1101 can be made lower than before, and a magnetic disk device with a reduced error rate of the decoding result can be realized.

When the signal processing unit 1107 is mounted on a magnetic disk drive, an operation of setting an appropriate value to a register provided in a filter parameter learning unit according to the quality of a medium, a head, a motor, and the like is performed. May be necessary.
This operation is performed when setting in the magnetic disk device at the time of product shipment, and the register contents are set according to the error rate or the quality of the equalization error of the decoding result output from the signal processing unit 1107.

Next, the configuration of an optical disk device using the above-described signal processing unit will be described.

FIG. 9 is a diagram showing a configuration of an optical disk device according to the present invention.

As shown in FIG.
00 is an optical disk 1201 on which data is written.
And a spindle 120 for rotating the optical disc 1201
2, an optical pickup 1203 for reading and writing data from the optical disk 1201, an actuator 1204 for performing focusing control and tracking control of the optical pickup, and a spindle motor 1205 for rotating a spindle 1202.

Further, as other control units, an interface (I / F) 1208 for connecting to the information processing device (host) 1207 and an optical disk controller (ODC) for controlling data transfer and format, etc. 1209 and a microcomputer (CPU) 1210
A signal processing unit 1206 for processing a signal from the optical pickup 1203, a spindle control circuit (SMC) 1211 for controlling the spindle motor 1205,
An actuator controller (AC) 1212 for controlling the actuator 1204 is provided.

Here, the signal processing section 1206 has the same configuration as any of the above-described embodiments. Therefore, even for a signal with poor performance such as a CN ratio (carrier / noise ratio) read from the optical disk 1201, an optical disk device with a reduced error rate of the decoding result can be realized.

When the signal processing unit 1206 is mounted on an optical disk device, an operation of setting an appropriate value in a register provided in a filter parameter learning unit according to the quality of a medium, an optical pickup, a motor, and the like is performed. May be required. This operation is performed when setting in the optical disk device at the time of product shipment, and the register contents are set according to the error rate or the quality of the equalization error of the decoding result output from the signal processing unit 1206.

[0091]

As described above in detail, according to the present invention, since filter parameter learning can be performed with high accuracy while suppressing an increase in power consumption, the performance such as the SN ratio read from the recording medium can be improved. For signals with poor signal quality, lower the error rate than before, or guarantee the same error rate,
The permissible specifications of the performance of components other than the signal processing unit such as the medium, the head, the pickup, and the motor can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a signal processing unit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of an error signal generation unit according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a filter parameter learning unit according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an example of a criterion of a determinator in a filter parameter learning unit.

FIG. 5 is a block diagram illustrating a configuration of a maximum likelihood estimating unit according to the first embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a maximum likelihood estimating unit according to a second embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a signal processing unit according to a third embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a magnetic disk drive according to the present invention.

FIG. 9 is a block diagram showing a configuration of an optical disk device according to the present invention.

FIG. 10 is a block diagram showing a configuration of a signal reproducing system of a conventional magnetic disk device.

FIG. 11 is a block diagram showing a configuration of a signal reproducing system of a conventional optical disc device.

FIG. 12 is a diagram illustrating a distribution of the amplitude of a digital equalizer output.

FIG. 13 is a block diagram showing a configuration of a signal reproducing system of a magnetic disk device using a signal after maximum likelihood decoding for updating a filter parameter.

[Explanation of symbols]

100, 200, 400, 500, 1000 Signal processing unit 101 Head 102, 202, 502 Amplifier 103, 203, 503 Variable gain amplifier 104, 204, 504 Analog filter 105, 205, 505 AD converter 106, 206, 506 Digital equalizer 107, 207, 407, 507, 507a Maximum likelihood estimator 108, 208, 508 Decoder 109, 209 Judge 110, 210, 410, 510 Error signal generator 111, 211, 411, 511 Filter parameter learning unit 201 Pickup 412, 512, 513 Delay unit 601 Target amplitude generator 602 Subtractor 701_1 to 701_ (n-1) Delay unit 702_1 to 702_n Multiplier 703_1 to 703_n Integrator 704_1 to 704_n Judge 705 Gist 706 Multiplexer 801, 902, 905 Metric calculation unit 802, 903, 906 Path memory 803, 804, 904, 907 ML selector 901 Waveform interference generation unit 1001 Monitor terminal 1100 Magnetic disk device 1101 Magnetic disk 1102, 1202 Spindle 1103 Magnetic head 1104 Arm 1105 Voice coil motor 1106, 1205 Spindle motor 1107, 1206 Signal processing circuit 1108, 1207 Host 1109, 1208 Interface 1110 Hard disk controller 1111, 1210 Microcomputer 1112, 1211 Spindle control circuit 1113, 1212 Voice coil motor control circuit 1200 Optical disk device 1201 Optical disk 1203 Optical pickup 1 04 actuator 1209 optical disk controller

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Takushi Nishitani 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside of Hitachi, Ltd.System Development Laboratory Co., Ltd. No. 1 Within Hitachi, Ltd. Semiconductor Group (72) Inventor Nobuaki Nakai 5--20-1, Kamimizu Honmachi, Kodaira-shi, Tokyo In-house Hitachi, Ltd. Semiconductor Group (72) Inventor Hirofumi Ide On Kodaira, Tokyo 5-20-1, Mizumoto-cho Hitachi Semiconductor Co., Ltd. (72) Inventor Yoshiteru Ishida 2880 Kozu, Odawara-shi, Kanagawa Prefecture F-term in the Hitachi, Ltd. Storage Systems Division 5D044 BC01 CC04 FG02 FG05 FG16 GL02 GL32

Claims (5)

[Claims] 1. An analog filter for limiting a band of an analog reproduction signal reproduced from a recording medium, an A / D converter for converting an output signal of the analog filter into a digital signal, and an output of the A / D converter. A digital equalizer that provides waveform interference for realizing a partial response method, a maximum likelihood estimating unit that performs maximum likelihood estimation from a signal whose waveform is equalized by the digital equalizer, and an output of the maximum likelihood estimating unit. A decoder for decoding user data recorded on a recording medium from an error signal generator for generating an error signal from an output of the digital equalizer; and a filter for learning a filter parameter of the digital equalizer from an output of the error signal generator. A parameter learning unit, wherein the maximum likelihood estimating unit is a determination result sent to the decoder. A digital information reproducing apparatus which outputs a second determination result separately, and wherein the error signal generator generates an error signal from the second determination result and an output of a digital equalizer. 2. The maximum likelihood estimating unit includes: a metric operation unit that generates metric and path selection information; a path memory that holds a path selection result output from the metric operation unit; and a last stage of the path memory. 2. The digital information reproducing apparatus according to claim 1, further comprising: an ML selector that obtains the second determination result using contents of a memory in a previous stage and the metric. 3. 3. The maximum likelihood estimator includes: first and second metric calculators for generating metric and path selection information; and a path selection result output from the first and second metric calculators. The first metric calculation unit and the first path memory output a determination result of maximum likelihood estimation; the second metric calculation unit and the second path memory 2. The digital information according to claim 1, wherein a second path memory outputs the second determination result, and a length of the second path memory is shorter than a length of the first path memory. 3. Playback device. 4. The digital information reproducing apparatus according to claim 1, further comprising a terminal for outputting error signal information outside the digital information reproducing apparatus. 5. The digital information reproducing apparatus according to claim 1, wherein the filter parameter learning unit includes a register capable of adjusting a filter parameter.