JPH0832028B2 - High efficiency encoder - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a high-efficiency coding apparatus for compressing the average number of bits per pixel of image data such as digital television signals.

[Outline of Invention]

According to the present invention, in a high-efficiency encoding device applied when transmitting image data such as a digital television signal, one screen is divided into a large number of two-dimensional or three-dimensional blocks, and pixels in each block are divided. Pixel data in a block can be encoded with a compressed bit length by encoding with a variable bit length adapted to the dynamic range narrowed by the correlation, and the number of bits reduced compared to the number of bits of the original data Transmission data can be formed. Further, when the bit length is set according to the dynamic range, the bit length is set non-linearly so that the maximum distortion changes according to the dynamic range without keeping the maximum distortion constant. According to the present invention, the compression rate can be increased without degrading the quality of the restored image on the receiving side.

[Conventional technology]

As a method for encoding a television signal, there are known several methods for reducing the average number of bits per pixel or the sampling frequency for the purpose of narrowing the transmission band.

As an encoding method for lowering the sampling frequency, image data is thinned by 1/2 by sub-sampling, and the sub-sampling point and the position of the sub-sampling point used at the time of interpolation are indicated (that is, either upper or lower or left or right of the interpolation point). A flag which indicates whether to use the data of the sub-sampling point) has been proposed.

DPCM (differential PCM) is known as one of encoding methods for reducing the average number of bits per pixel. DPCM focuses on the fact that the correlation between pixels of a television signal is high and the difference between adjacent pixels is small, and the difference signal is quantized and transmitted.

As another encoding method for reducing the average number of bits per pixel, the screen of one field is subdivided into minute blocks, and an average value and standard deviation for each block and 1-bit encoding for each pixel are encoded. Some transmit code.

An encoding method that attempts to reduce the sampling frequency by using subsampling has a sampling frequency of 1/2
Therefore, there is a fear that a folding distortion may occur.

DPCM had a problem that an error was propagated to subsequent decoding.

The method of encoding in block units has a drawback that block distortion occurs at boundaries between blocks.

In order to solve the above-mentioned problems, the applicant of the present application defines the maximum and minimum values of a plurality of pixels contained in a two-dimensional block as described in Japanese Patent Application No. 59-266407. We have proposed a high-efficiency coding apparatus that obtains a dynamic range according to this dynamic range and performs coding with a variable bit length adapted to this dynamic range.

FIG. 11 is used for explaining the previously proposed variable bit length coding adapted to the dynamic range. The dynamic range is calculated for each two-dimensional block including (4 lines × 4 pixels = 16 pixels). In addition, the minimum level (minimum value) in the block is removed from the input pixel data of one sample of 8 bits. The pixel data from which this minimum value has been removed is quantized. This quantization is a process of converting the pixel data from which the minimum value has been removed into a representative level. The allowable maximum value of the quantization distortion (referred to as maximum distortion) that occurs during this quantization is set to a predetermined value, for example 4.

FIG. 11A shows the case where the dynamic range DR (the difference between the maximum value MAX and the minimum value MIN) is 8. In the case of (DR = 8), the central level 4 is the representative level L0, and the maximum distortion E = 4. That is, when (0 ≦ DR ≦ 8), the center level of the dynamic range is set as the representative level,
There is no need to transmit quantized data. Therefore, the required bit length Nb is 0. On the receiving side, decoding is performed with the representative level L0 as the restoration value from the minimum value MIN of the block and the dynamic range DR.

FIG. 11B shows the case of (DR = 17), the representative level is set to (L0 = 4) (L1 = 13), and the maximum distortion E is 4. Since there are two representative levels L0 and L1, (Nb = 1)
Becomes In the case of (9 ≦ DR ≦ 17), it is (Nb = 1). The maximum distortion E becomes smaller as the dynamic range DR is narrower.

FIG. 11C shows the case of (DR = 35), and the representative levels are determined to be (L0 = 4) (L1 = 13) (L2 = 22) (L3 = 31), respectively, and (E = 4) is there. Since there are four representative levels L0 to L3, (Nb = 2). In the case of (18 ≦ DR ≦ 35), (Nb = 2) is set.

In the case of (36 ≦ DR ≦ 71), eight representative levels (L0-
L7) is used. FIG. 11D shows the case of (DR = 71), and the representative level is (L0 = 4) (L1 = 13) (L2 = 22) (L3
= 31) (L4 = 40) (L5 = 49) (L6 = 58) (L7 = 67). (Nb = 3) in order to distinguish the eight representative levels L0 to L7.

In the case of (72 ≤ DR ≤ 143), 16 representative levels (L0
~ L15) is used. FIG. 11E shows the case of (DR = 143), and the representative level is (L8 = 76) (L9 = 85) (L10 = 9).
4) (L11 = 103) (L12 = 112) (L13 = 121) (L14 = 13
0) (L15 = 139) (L0 to L7 are the same as the above values). In order to distinguish 16 representative levels (L0 to L15), it is set to (Nb = 4).

In the case of (144 ≦ DR ≦ 287), 32 representative levels (L0
~ L31) is used. FIG. 11F shows the case of (DR = 287), and the representative level is (L16 = 148) (L17 = 157) (L18
= 166) (L19 = 175) (L27 = 247) (L28 = 25)
6) (L29 = 265) (L30 = 274) (L31 = 283) (L0 ~ L15
Is the same as the value above). In order to distinguish the 32 representative levels (L0 to L31), it is set to (Nb = 5). Actually, since the input pixel data is quantized by 8 bits, the maximum value of the dynamic range DR is 255, and it is not quantized to the representative level (L28 to L31).

Since the television signals in one block have a three-dimensional correlation in the horizontal and vertical two-dimensional directions and in the time direction, in the steady part, the variation range of the level of the pixel data included in the same block. Is small. Therefore,
Even if the dynamic range of the data DTI after removing the minimum level MIN shared by the pixel data in the block is quantized with a quantization bit number smaller than the original quantization bit number, quantization distortion hardly occurs. By reducing the number of quantization bits, the data transmission bandwidth can be made narrower than the original transmission bandwidth.

[Problems to be solved by the invention]

In the above-mentioned encoding device adapted to the dynamic range in which the bit length is variable, the maximum allowable distortion E is set to 4, for example. If the value of this maximum strain E is made larger,
The bit length Nb becomes smaller and the compression rate can be increased. However, when the maximum distortion E is increased, block distortion occurs.

Therefore, an object of the present invention is to provide a high-efficiency coding apparatus capable of increasing the compression rate without causing deterioration of a restored image such as block distortion.

In the present invention, when the bit length Nb is determined, the maximum distortion is changed with a non-linear characteristic that matches the human visual characteristics with respect to the dynamic range DR without changing the maximum distortion, and the bit length Nb is Made smaller. Generally, when there is a sharp change in the brightness level within a block, that is, when the dynamic range DR is large, a small change in the brightness level is difficult to notice. Therefore, in the present invention, the value of the maximum distortion E is relatively increased and the bit length Nb is decreased in a block having a large dynamic range DR.

[Means for solving problems]

The present invention is a means for obtaining the maximum value of a plurality of pixel data, the minimum value of a plurality of pixel data, and the dynamic range for each block included in a block composed of regions belonging to the same field or a plurality of consecutive fields of a digital image signal. A means for forming modified input data modified so as to have a relative level relationship based on a value defining a dynamic range, and a dynamic range defined by the number of quantization bits of a digital image signal. The value is divided into multiple ranges in the level direction, different numbers of bits are assigned to each range, and the larger the dynamic range, the more bits are allocated and the quantization is performed so that the maximum distortion becomes larger. , The code of the number of bits corresponding to the range to which the value of the modified input data belongs And a means for transmitting at least two of the dynamic range information, maximum value, and minimum value for each block as an additional code together with the encoded code signal. It is an encoding device.

[Action]

The variable bit length encoding adapted to the dynamic range DR can increase the compression rate. In particular, in the present invention, when the dynamic range DR is large, block distortion does not occur even if the maximum distortion is large, so the bit length is shortened. Therefore, without causing block distortion,
The compression rate can be made higher.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This invention is made in the following order of items.

a. Configuration of transmitting side b. Configuration of receiving side c. Block and blocking circuit d. Dynamic range detection circuit e. Quantization circuit f. Modified example a. Configuration of transmitting side FIG. 1 shows the transmitting side of the present invention. The configuration of (recording side) is shown as a whole. A digital television signal in which, for example, one sample is quantized into 8 bits is input to an input terminal indicated by 1. This digital television signal is supplied to the blocking circuit 2.

The blocking circuit 2 converts the input digital television signal into a continuous signal for each two-dimensional block which is a unit of coding. In this embodiment, one block has a size of (4 lines × 4 pixels = 16 pixels).
The output signal of the blocking circuit 2 is supplied to the dynamic range detection circuit 3 and the subtraction circuit 4. The dynamic range detection circuit 3 detects the dynamic range DR and the minimum value MIN for each block. The pixel data PD from the blocking circuit 2 is supplied to the subtraction circuit 4, and the subtraction circuit 4 forms pixel data PDI from which the minimum value MIN is removed.

Further, the detected dynamic range DR is supplied to the bit length determination circuit 6. The bit length determination circuit 6 determines the number of quantization bits (bit length N
b) is determined. In this case, the bit length Nb is set in consideration of human visual characteristics. That is, when the dynamic range DR is large, the maximum distortion E is increased. As an example, the bit length determination circuit 6 determines the bit length Nb according to the dynamic range DR as follows.

The determined bit length Nb is supplied to the quantization circuit 5. The quantization circuit 5 is supplied with the pixel data PDI from which the minimum value has been removed from the subtraction circuit 4. In the quantizing circuit 5, the pixel data PDI is calculated by the bit length Nb for each block.
Is quantized.

The coded code DT from the quantization circuit 5 is supplied to the framing circuit 7. The dynamic range DR (8 bits) and the minimum value MIN (8 bits) are supplied to the framing circuit 7 as additional codes for each block. The framing circuit 7 performs error correction coding processing on the coded code DT and the above-mentioned additional code, and also adds a synchronization signal. Transmission data is obtained at the output terminal 8 of the framing circuit 7, and this transmission data is sent to a transmission line such as a digital line.

As described above, the encoded code DT has a variable number of bits for each block, but the bit length of the pixel data of the block is uniquely determined from the dynamic range DR in the additional code. Therefore, there is an advantage that it is not necessary to insert a redundant code indicating a data delimiter in the transmission data, although the variable length code is adopted.

b. Configuration on the receiving side FIG. 2 shows the configuration on the receiving (or reproducing) side. The received data from the input terminal 11 is supplied by the frame decomposing circuit 12. Encoded code DT by the frame decomposition circuit 12
And the additional codes DR and MIN are separated, and error correction processing is performed. The encoded code DT is supplied to the decoding circuit 13, and the dynamic range DR is supplied to the bit length determination circuit 14.

In the bit length determination circuit 14, the bit length for each block is determined from the dynamic range DR as in the transmitting side. The bit length is supplied to the decoding circuit 13. Decoding circuit 13
Performs processing opposite to that of the quantization circuit 5 on the transmission side. That is, the data after the removal of the 8-bit minimum level is decoded into a representative level, this data and the 8-bit minimum value MIN are added by the addition circuit 15, and the original pixel data is decoded. The output data of the adder circuit 15 is supplied to the block decomposition circuit 16. The block decomposing circuit 16 is a circuit for converting the decoded data in the order of blocks into the same order as the scanning of the television signal, contrary to the blocking circuit 2 on the transmission side. The decoded television signal is obtained at the output terminal of the block decomposition circuit 16.

c. Block and Blocking Circuit A block, which is a unit of coding, will be described with reference to FIG. In this example, by dividing the screen of one field, a large number of two-dimensional blocks (4 lines × 4 pixels) shown in FIG. 3 are formed. In FIG. 3, a solid line indicates an odd field line, and a broken line indicates
The lines of even fields are shown. Unlike this example, the present invention can be applied to, for example, a three-dimensional block including four two-dimensional regions belonging to each frame of four frames.

The blocking circuit 2 will be described with reference to FIGS. 4, 5 and 6. For the sake of simplicity of explanation, it is assumed that the screen of one field has a configuration of (4 lines × 8 pixels) as shown in FIG. 5, and this screen is divided into two vertically and horizontally as shown by the broken line. Divided into 4 parts, (2 lines x 2
A case where eight blocks of (pixels) are formed will be described.

In FIG. 4, as shown in FIG. 6A, input data A consisting of 4 lines (Th _{0 to} Th ₃ ) is applied to the input terminal indicated by 21.
And a sampling clock B (FIG. 6B) synchronized with the input data A is supplied to the input terminal indicated by 22. The numbers (1 to 8) indicate the sample data of the line Th ₀ , the numbers (11 to 18) indicate the sample data of the line Th ₁ , and the numbers (21 to 28) indicate the sample data of the line Th ₂ . , And the numbers (31-38) are the line Th ₃
The sample data of each is shown. The input data A is supplied to the delay circuit 23 having a delay amount of Th and the delay circuit 24 having a delay amount of 2Ts (Ts: sampling period). Further, the sampling clock B is supplied to the 1/2 frequency dividing circuit 27.

The output signal C of the delay circuit 24 (FIG. 6C) is a switch circuit.
The delay circuit 23 is supplied to one of the input terminals of 25 and 26, respectively.
Output signal D (FIG. 6D) is supplied to the other input terminals of the switch circuits 25 and 26, respectively. The switch circuit 25 is 1 /
Controlled by the output signal E of the divide-by-2 circuit 27 (Fig. 6E), the switch circuit 26 outputs the pulse signal E as an inverter.
It is controlled by the pulse signal inverted by 28. The switch circuits 25 and 26 alternately select the input signal (C or D) every 2Ts. The output signal F from the switch circuit 25 is shown in FIG. 6F, and the output signal G from the switch circuit 26 is shown in FIG. 6G.

The output signal F of the switch circuit 25 is the first signal of the switch circuit 29.
Input terminal and a delay circuit 30 having a delay amount of 4 Ts. The output signal G of the switch circuit 26 is supplied to the delay circuit 31 having a delay amount of 2Ts. The output signal H of the delay circuit 30 (FIG. 6H) is supplied to the third input terminal of the switch circuit 29. The output signal I (FIG. 6I) of the delay circuit 31 is supplied to the second input terminal of the switch circuit 29 and the delay circuit 32 having a delay amount of 4Ts. The output signal J (FIG. 6J) of the delay circuit 32 is supplied to the fourth input terminal of the switch circuit 29.

The output signal of the 1/2 divider circuit 27 is supplied to the 1/2 divider circuit 33, and the output signal K (K in FIG. 6) is formed. The switch circuit 29 is controlled by the signal K, and the first and second switching is performed every 4Ts.
The second, third and fourth input terminals are sequentially selected. Therefore,
Signal L output from switch circuit 29 to output terminal 34
Is as shown in FIG. 6L. That is, the order of each field of data is the order of each block (for example, 1 → 2 → 11).
→ Converted to 12). Of course, the actual number of pixels in one field is much larger than the example shown in FIG. 5,
By the same scan conversion as described above, conversion is performed in the order of each block shown in FIG.

d. Dynamic Range Detection Circuit FIG. 7 shows an example of the configuration of the dynamic range detection circuit 3. As described above, the block circuit 2 sequentially supplies the input terminal indicated by 41 with image data of an area in which encoding is required for each block. The pixel data from the input terminal 41 is supplied to the selection circuit 42 and the selection circuit 43. One of the selection circuits 42 selects and outputs the one having a larger level between the pixel data of the input digital television signal and the output data of the latch 44. The other selection circuit 43 selects and outputs the smaller one of the pixel data of the input digital television signal and the output data of the latch 45.

The output data of the selection circuit 42 is supplied to the subtraction circuit 46 and is also captured by the latch 44. The output data of the selection circuit 43 is supplied to the subtraction circuit 46 and the latch 48, and at the same time, latched.
Captured by 45. A latch pulse is supplied from the control unit 49 to the latches 44 and 45. Timing signals such as a sampling clock and a synchronizing signal that are synchronized with the input digital television signal are supplied to the control unit 49 from the terminal 50. The control unit 49 supplies a latch pulse to the latches 44 and 45 and the latches 47 and 48 at a predetermined timing.

At the beginning of each block, the contents of latches 44 and 45 are initialized. All of the data of "0" is initialized to the latch 44, and all of the data of "1" is initialized to the latch 45. The maximum level is stored in the latch 44 among the pixel data of the same block that are sequentially supplied. In addition, the minimum level is stored in the latch 45 among the pixel data of the same block that is sequentially supplied.

When the detection of the maximum level and the minimum level is completed for one block, the maximum level of the block occurs at the output of the selection circuit 42. On the other hand, the minimum level of the block occurs at the output of the selection circuit 43. Latches 44 and 45 are reinitialized when the detection for one block is complete.

The output of the subtraction circuit 46 is the maximum level from the selection circuit 42.
The dynamic range DR of each block is obtained by subtracting MAX and the minimum level MIN from the selection circuit 43. These dynamic range DR and minimum level MIN are latched in the latches 47 and 48 by the latch pulse from the control block 49, respectively. The dynamic range DR of each block can be obtained at the output terminal 51 of the latch 47, and the output terminal 52 of the latch 48 can be obtained.
The minimum value MIN of each block is obtained.

e. Quantization Circuit An example of the quantization circuit 5 will be described with reference to FIG. In FIG. 8, the bit length Nb (2 bits) obtained by the bit length determination circuit 6 from the dynamic range DR is supplied to the input terminal indicated by 56, and the minimum value MIN is removed at the input terminal indicated by 57. Pixel data PDI is supplied. These data Nb and PDI are input to the address of the ROM 55 storing the data conversion table for quantization. ROM
A coded code DT of 3 bits is obtained from 55. In this encoded code DT, all the 3 bits are invalid in the case of (Nb = 0), and the least significant bit among the 3 bits is valid in the case of (Nb = 1), In the case of Nb = 2), the least significant bit among the 3 bits and its upper 2 bits are valid, and in the case of (Nb = 3), all 3 bits are valid.

In this embodiment, the value of the representative level used as the restoration value is a fixed value according to the bit length Nb. When the dynamic range DR is (0 ≦ DR ≦ 10) and (Nb = 0), it is not necessary to transmit the encoded code, and as shown in FIG. 9A, the central value (5 ) Is the representative level L0. The maximum strain is (E0 = 5).

In the case of (11 ≦ DR ≦ 25) and (Nb = 1), the ROM 55 performs 1-bit quantization with the maximum distortion (E1 = 6). As shown in FIG. 9B, the pixel data PDI is (0 to 1
If it is within the range of 2), "0" is output as the encoded code DT, and if the pixel data PDI is within the range of (13 to 25), "1" is output as the encoded code DT. It In this case, the representative level used as the restoration value on the receiving side is
(L0 = 6) (L1 = 19).

In the case of (26 ≦ DR ≦ 99) and (Nb = 2), the ROM 55 performs 2-bit quantization of (E2 = 12). As shown in FIG. 9C, the pixel data PDI is (0 to 24), (25 to 4).
(00), (01), (10) and (11) are output as the coded code DT depending on which of 9), (50 to 74) and (75 to 99) it is. . In this case, the representative level used as the restoration value on the receiving side is (L0 = 12) (L1 = 35)
(L2 = 62) (L3 = 87).

In the case of (100 ≦ DR ≦ 255) and (Nb = 3), ROM55
2 bit quantization of (E3 = 16) is performed by. Ninth
As shown in FIG. D, the pixel data PDI is (0 to 32), (33
~ 65), (66 ~ 98), (99 ~ 131), (132 ~ 164), (1
65 to 197), (198 to 230), and (231 to 263), depending on whether the range is (000), (001), (010), (0
11), (100), (101), (110) and (111) are output as the encoded code DT. In this case, the representative level used as the restoration value on the receiving side is (L0 = 16) (L1 = 49)
(L2 = 82) (L3 = 115) (L4 = 148) (L5 = 181) (L6 = 2
14) (L7 = 247).

As described above, when the representative level used as the restoration value on the receiving side is set to the predetermined value corresponding to the dynamic range, it is not always necessary to send the dynamic range DR (8 bits) as the additional code, and the minimum value ( 8 bits) and bit length Nb may be sent.

On the other hand, unlike this one embodiment, each dynamic range
Quantization may be performed by adapting to DR and determining the division range each time. In this case, the dynamic range DR is supplied to the ROM as an address signal instead of the bit length Nb. The data conversion table for quantization stored in ROM matches the visual characteristics and the maximum distortion changes. In this method, the additional code is any two of the minimum value (8 bits), the dynamic range DR (8 bits), and the maximum value (8 bits). The latter method reduces the data compression rate, but the restoration distortion is significantly improved compared to the above method.

On the receiving side, a representative level determined by the bit length Nb and the encoded code DT is obtained as a restoration value, and the minimum value MIN is added to this restoration value to obtain pixel data.

f. Modified example For example (Nb = 2), as shown in FIG. 10, the representative level L0 is equal to the minimum value MIN, and the representative level L3 is M.
You may make it quantize so that it may be equal to AX.

Alternatively, one block of data may be taken out at the same time by a circuit combining a frame memory, a line delay circuit, and a sample delay circuit.

〔The invention's effect〕

According to the present invention, the amount of data to be transmitted can be sufficiently reduced compared to the original data, and the transmission band can be narrowed. Further, the present invention has an advantage that the original pixel data can be almost completely restored from the received data in the stationary part where the change width of the brightness level is small, and the image quality is hardly deteriorated. Further, according to the present invention, since the dynamic range is determined corresponding to each block, the response at the transitional part such as the edge where the change width is large becomes good.

According to the present invention, since the delimiter code is variable-length coding, the compression rate can be increased. In particular, according to the present invention, since the variable length coding is performed by the non-linear characteristic matching the visual characteristic, even if the number of bits of the coding code of each pixel is reduced, the deterioration of the quality of the received image due to the block distortion or the like is prevented. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a receiving side, and FIG. 3 is a schematic diagram used for explaining a block which is a unit of encoding processing. 5, FIG. 5 and FIG. 6 are examples of the structure of the block circuit, schematic diagrams and timing charts for explaining the same, FIG. 7 is a block diagram of an example of the dynamic range detection circuit, and FIG. A block diagram of an example of a circuit, FIGS. 9 and 10 are schematic diagrams used to explain an example of quantization and another example, respectively.
FIG. 11 is a schematic diagram used for explaining the previously proposed high efficiency coding. Description of main symbols in the drawings 1: Input terminal of digital television signal, 2: Blocking circuit, 3: Dynamic range detection circuit, 5: Quantization circuit, 6: Bit length determination circuit, 7: Framed circuit.

Claims (1)

[Claims] 1. A maximum value of a plurality of pixel data, a minimum value of the plurality of pixel data, and a dynamic range for each block included in a block composed of regions belonging to the same field or a plurality of consecutive fields of a digital image signal. Determining means, means for forming modified input data modified so as to have a relative level relationship based on a value defining the dynamic range, and the above defined by the number of quantization bits of the digital image signal. The possible value of the dynamic range is divided into a plurality of ranges in the level direction, different numbers of bits are assigned to the above ranges, and the larger the dynamic range, the larger the number of assigned bits and the larger the maximum distortion. Quantization is performed so that the value of the modified input data belongs to The quantizing means for generating a coded code signal having the number of bits corresponding to the circle, and the coded code signal using at least two of the information of the dynamic range for each block, the maximum value and the minimum value as an additional code. A high-efficiency coding device comprising: