JPH08305431A - Memory access system - Google Patents

Abstract

PURPOSE: To accelerate read access from a master unit to the memory of a slave unit. CONSTITUTION: A read request is inputted to a read request transmitting means 1a. The read request transmitting means 1a discriminates whether the address of that read request is continued to the address of the last read request or not. When the address is not continued, that read request is transmitted to a slave unit 2 but when the address is continued, an address match signal is outputted to a read data control means 1b. A memory access control means 2a transmits the first data of the address shown by the read request and the second data of the next address to a master unit 1. The read data control means 1b transfers the first data as read data and stores the second data in a buffer 1ba. When the read request is further outputted to the continued address in such a state and the address match signal is inputted to the read data control means 1b, the second data in the buffer 1ba are transferred.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access system for a system in which a master unit and a slave unit are connected via a transmission line, and more particularly to a system memory in which the master unit can directly access the memory in the slave unit. Regarding access method.

[0002]

2. Description of the Related Art A numerical control system is provided with a numerical control unit (CNC) and a man-machine controller (MMC) which interactively inputs and outputs data and processes the data. The MMC is provided with various devices such as an input device using a keyboard and a mouse and a display device using a CRT or a liquid crystal display.

In many cases, the CNC and MMC are provided in one housing and are connected to each other by a parallel bus. However, if the MMC can be installed in a place apart from the CNC, the MMC can be installed in a place where an operator can easily work, thereby improving work efficiency. Therefore, M
There was a demand to connect the MC and CNC with a long transmission line. Moreover, it has been desired that one memory can be directly accessed to the other memory through a long transmission line.

Therefore, conventionally, the MMC is a master unit,
By using the CNC as a slave unit and connecting them to each other through a high-speed transmission line, the MMC can directly access the common RAM in the CNC. In this case, the CPU on the MMC side outputs a memory access request in the same manner as accessing the memory inside the MMC.
This memory access request is transferred to the CNC by serial communication. When the CNC side receives the memory access request from the MMC side, it performs DMA (direct memory access) to the common RAM. If the access request is a read request, the corresponding data is transmitted to the MMC. As an example of this, the present applicant has filed Japanese Patent Application No. 6-86331.
No. has been filed.

In this way, the MMC is the C in the CNC.
It is possible to directly access the memory in the CNC without going through the processing of the PU.

[0006]

By the way, in the above memory access method, when writing to the RAM on the slave unit side, the data to be written to the register provided on the serial bus controller on the master unit side. The write cycle on the master unit side is ended when is stored. As a result, the write cycle is performed at the same high speed as the access to the memory connected to the local bus, and the CPU on the master unit side can immediately perform the next processing.

However, in the case of the read cycle, the CPU on the master unit side waits until the read request output from the master unit side reaches the slave unit side and the target data arrives from the slave unit side. During this time, the CPU on the master unit side cannot perform other processing. Therefore, there is a problem that the overall data processing speed becomes slow.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a memory access system capable of performing a high-speed read access from a master unit to a memory of a slave unit.

[0009]

According to the present invention, in order to solve the above problems, in a memory access system of a system in which a master unit and a slave unit are connected via a transmission line, the master unit and the slave unit are provided in the master unit. Read request transmitting means for transmitting a read request to an arbitrary address of the memory in the slave unit via the transmission line; and a read request transmission unit provided in the slave unit, which receives the read request And a memory access control means for transmitting second data at an address next to the address to the master unit.

Further, in a memory access system of a system in which a master unit and a slave unit are connected via a transmission line, the master unit and the slave unit are provided in the master unit,
It is determined whether or not a read request to any address of the memory in the slave unit requests continuous data with previously accessed data, and if continuous data is requested, an address match signal is output, When requesting non-continuous data, the read request transmission means for transmitting the read request via the transmission line, and the slave unit provided in the slave unit, and when the read request is received, the requested address Memory access control means for transmitting first data and second data at an address next to the address via the transmission line, and read the first data received in the master unit. Transfer the request to the device that has output the request, store the second data in a buffer, and store the address match signal. When the output is a memory access method; and a read data control means for transferring said second data in the buffer to the device which has output the read request is provided.

[0011]

The read request sending means provided in the master unit sends a read request to an arbitrary address of the memory in the slave unit via the transmission line. Upon receiving the read request, the memory access control means provided in the slave unit transmits the first data at the requested address and the second data at the next address to the master unit.

Further, the read request transmission means provided in the master unit determines whether or not a read request to an arbitrary address of the memory in the slave unit requests data continuous with the data accessed last time,
An address match signal is output when continuous data is requested, and a read request is transmitted through the transmission line when continuous data is requested. Upon receiving the read request, the memory access control means provided in the slave unit transmits the first data at the requested address and the second data at the next address via the transmission line. The read data control means provided in the master unit transfers the received first data to the device which has output the read request, stores the second data in the buffer, and outputs the address match signal. The second data in the buffer is transferred to the device that has output the read request.

[0013]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of the present invention. The master unit 1 and the slave unit 2 are connected to each other via a transmission line 3 for serial transmission.

The read request for the memory 2b in the slave unit 2 output in the master unit 1 is input to the read request transmitting means 1a. When receiving the read request, the read request transmission unit 1a determines whether the address of the read request is continuous with the address of the previous read request. If it is not a continuous address, the read request is transmitted to the slave unit 2, and if it is a continuous address, an address match signal is output to the read data control means 1b.

The read request transmitted from the read request transmission means 1a is input to the memory access control means 2a in the slave unit 2 via the transmission line 3. The memory access control means 2a stores the first data at the address indicated by the read request and the second data at the next address in the memory 2b.
And the data of the above are transmitted to the master unit 1. For example, if the read request is for the address of "ADD # 01", the data "DATA" of the addresses "ADD # 01" and "ADD # 02"
Send "1" and "DATA2".

The data transferred from the slave unit 2 is input to the read data control means 1b. The read data control means 1b transfers the first data as read data to the device that has output the read request, and stores the second data in the buffer 1ba. For example, "DATA1" and "DATA
When "2" is received, "DATA1" is transferred to the device that outputs the read request, and "DATA2" is transferred to buffer 1ba.
To be stored.

In this state, when a read request for further consecutive addresses is output and an address match signal is input to the read data control means 1b, the device that issued the read request for the second data in the buffer 1ba. Forward to. Hereinafter, such data transfer at the time of reading will be referred to as read burst transfer.

In this way, when read requests for consecutive addresses are output, the data stored in the buffer can be transferred. As a result, the read cycle can be completed in a short time.

FIG. 2 is a block diagram showing the configuration of a numerical control system for carrying out the present invention. The figure is roughly divided,
It is divided into an MMC (Man Machine Controller) 20 and a CNC (Numerical Control Unit) 30. In this example, MMC
20 is a master unit and the CNC 30 is a slave unit. In the CNC 30, the CPU 31 controls various devices via the local bus 35, and the MMC 20
The CPU 24 controls various devices via the local bus 29. The MMC 20 and the CNC 30 are connected by a transmission line 40, and data is transmitted and received through this transmission line 40. In addition, local bus 3 in CNC30
Reference numeral 5 denotes a multi-master bus, and devices other than the CPU 31 can also be bus masters.

In the CNC 30, the CPU 31 controls the CNC
Control 30 as a whole. The common RAM 32 stores various data or input / output signals, and is used by the CNC 30 and the MMC.
It can be shared with 20. A CMOS memory is used as the non-volatile memory 33, which is backed up by a battery and stores parameters, pitch error correction amounts, tool error correction amounts, and the like that should be retained even after the power is turned off.

The axis control circuit 36 receives the axis movement command from the CPU 31, and outputs the axis command to the servo amplifier 37. The servo amplifier 37 receives the movement command and drives the servo motor of the machine tool 10. A PMC (Programmable Machine Controller) 38 receives a T function signal (tool selection command) and the like when executing an NC program. Then, these signals are processed by the sequence program, and the signals are output as the operation command, and the machine tool 10
Control. Further, it receives a status signal from the machine tool 10, performs a sequence process, and transfers a necessary input signal to the CPU 31.

Further, the serial bus controller 34 connected to the local bus 35 transmits / receives data to / from the MMC 20. From MMC20 to common RAM3
When there is a request for access to 2, the serial bus controller 34 performs DMA (Direct Memory Access) to access the data in the common RAM 32. If the access request is a read request (read request),
The data and the data of the next address are transferred to the MMC 20. When the access request is a write request (write request), the transferred data is written in the common RAM 32. The serial bus controller 34 also converts a parallel signal used for data transfer of the local bus 35 into a serial signal to convert the MMC 20 into a serial signal.
And outputs the input serial signal to a parallel signal and receives the parallel signal.

In the MMC 20, the CPU 24 executes a program for interactive processing, and in the interactive input screen displayed, settable works, data, etc. are displayed in a menu format on the display device 22 via the graphic control circuit 22a. indicate. In addition, a machining program is created from the data thus input, and the starting trajectory of the entire tool is displayed as a background animation. The RAM 25 stores various data for dialogue and the like. A memory using CMOS is used as the non-volatile memory 26, which is backed up by a battery, and stores application programs, machining programs, and the like that should be retained even after the power is turned off. The VRAM (video RAM) 27 is a RAM that can be accessed at high speed, and contains graphic data for animation display when a cutting simulation of the machine tool 10 is performed based on a machining program stored as an NC statement in the non-volatile memory 26. Is stored. The graphic control circuit 22a is V
The graphic data stored in the RAM 27 is converted into a display signal and output to the display device 22.

Furthermore, when exchanging data, FDD
A floppy disk is inserted into the FDD 21 connected via the interface 21a, software is loaded from the floppy disk, and various data is transferred to the floppy disk.
Write to disc.

Further, the graphic control circuit 22a is CP
The digital signal output from U24 or the like is converted into a display signal and given to the display device 22. C on the display device 22
An RT or liquid crystal display device is used. keyboard·
The interface 23a includes a keyboard 23 and a CPU 24.
Control data transfer to and from. The keyboard 23 is composed of symbolic keys, numerical keys, etc., and necessary graphic data and NC data are input using these keys.

The serial bus controller 28 is an MMC
When there is an access request from the device in 20 to the common RAM 32 in the CNC 30, the access request input as a parallel signal is converted into a serial signal and output to the CNC 30. Also, the serial signal input from the CNC 30 is
Convert to parallel signal and receive.

The transmission line 40 between the serial bus controller 28 on the MMC 20 side and the serial bus controller 34 on the CNC 30 side can be 20 m to 50 m long. And high-speed data transfer (about 25M
bps) is possible.

M in the above numerical control system
A packet switching method is used for data transfer between the MC 20 and the CNC 30. In the packet switching method, the data to be transferred is divided into blocks of arbitrary length. A packet is one in which various control information is added to the divided blocks. The packet switching method used in the access request from the MMC 20 to the CNC 30 will be described below.

FIG. 3 is a diagram showing an example of the format of a packet. The read request packet 51 is a packet output when the device on the MMC side accesses the data in the common RAM in the CNC. Read request packet 5
The first 4 bits of 1 are the command 51a and indicate that this packet is a read request packet. Next 23
A bit is an address that requires a read. The last 8 bits are a CRC (Cyclic Redundancy Check) check code.

The read data packet 52 is a packet output by the CNC when sending back data in response to a read request from the MMC. The first 4 bits of the read data packet 52 are the command 52a, which indicates that this packet is a read data packet. The next 16 bits are the data 52b of the read-requested address. The last 8 bits are CRC (Cyclic Redundancy Chec)
This is the check code 52c of k).

The command 52a of the read data packet 52 includes the first read data packet and the second read data packet.
Read data packet. When the read burst transfer is not performed, the first read data packet is transferred. On the other hand, when performing read burst transfer, first data requested by a read request is transferred as a second read data packet, and second data at the next address is transferred as a first read data packet. To be done.

The write data packet 53 is from MMC to C
This is a packet output when writing data to the common RAM in the NC. The first 4 bits of the write data packet 53 is a command 53a, which indicates that this packet is a write data packet. The next 23 bits are an address 53b for requesting a write. Next 1
Six bits are data 53c to be written in the memory in response to the write request. The last 8 bits are CRC (Cyclic Red)
undancy Check) check code 53d.

Next, a read cycle performed using the above packet in the numerical control system shown in FIG. 2 will be described. First, when reading from the CPU 24 on the MMC 20 side to the common RAM 32 on the CNC 30 side,
The serial bus controller 28 connected to the local bus 29 of the MMC 20 uses the common RAM 3 in the CNC 30.
Detect read cycle for 2. The serial bus controller 28 transfers this read request as a read request packet to the CNC 30 side.

Upon receiving the read request packet, the serial bus controller 34 on the side of the CNC 30 receives the common RAM.
A read cycle is generated for the requested address on 32 and the address next to that address. Then, the first data and the second data read in the read cycle are respectively used as a second read data packet,
It is transferred to the MMC 20 side as a first read data packet.

Upon receiving the second read data packet, the serial bus controller 28 on the MMC 20 side transfers the first data to the device which has output the read request, and recognizes that the read burst transfer will be performed.
Then, the second data of the first read data packet sent next is stored in the read burst buffer. In this state, if the further output read request to the common RAM 32 of the CNC 30 is a read request for consecutive addresses, the second data in the read burst buffer is transferred to the device that has output the read request.

The serial bus controller 28 will be described in more detail below. FIG. 4 is a block diagram showing the internal configuration of the serial bus controller on the MMC side. The serial bus controller is connected to the local bus 29. An access request to the common RAM of the CNC is input via the local bus 29. This access request is sent to the transmission control unit 28c and also input to the address latch circuit 28a and the comparison unit 28b. The address latch circuit 28a is further connected to the comparison unit 28b. The output signal of the comparison unit 28b is an address match signal and is input to the transmission control unit 28c and the data output control unit 28j. The output signal of the transmission control unit 28c is converted into a serial signal by the parallel-serial conversion circuit 28d, driven by the driver 28e, and output to the CNC.

On the other hand, the input signal from the CNC is received by the receiver 28f, converted into a parallel signal by the serial / parallel conversion circuit 28g, and then received data switching unit 2
Input to 8h. One output from the reception data switching unit 28h is output to the local bus 29, and the other output is input to the read burst buffer 28i. The output end of the read burst buffer 28i is the data output control unit 2
It is output via 8j.

In the serial bus controller 28 having such a configuration, when an access request to the common RAM in the CNC is input via the local bus 29, if the access request is a read request, the data is the address latch circuit. 28a. Comparison unit 28b
Is the difference between the address requested by the read request and the address latched in the address latch circuit 28a. If the difference is "1", it is determined that the read request is for continuous data, and the address is read. Output a match signal.

If the input access request is a write request, the transmission controller 28c outputs the write request as a write data packet. On the other hand, if the input access request is a read request, the comparison unit 28b
Does not output the address match signal, it outputs the read request as a read data packet, and if the comparison unit 28b outputs the address match signal, it does not output the data. The packet transmitted from the transmission control unit 28c is converted into a serial signal by the parallel-serial conversion circuit 28d, then driven by the driver 28e and transferred to the CNC.

The packet sent from the CNC via the transmission line is input to the serial / parallel conversion circuit 28g via the receiver 28f. The serial / parallel conversion circuit 28g converts a packet transferred as a serial signal into a parallel signal. Received data switching unit 28h
Determines the type of the packet according to the head command of the packet converted into the parallel signal. If the first packet sent is the first read data packet, the data of that packet is output as read data. When the second read data packet and the first read data packet are continuously transferred, the data of the second read data packet is output as the read data and then the data of the first read data packet is output. Are stored in the read burst buffer 28i. In this state, when read requests for further consecutive addresses are output, the comparison unit 28b outputs an address match signal. The data output control unit 28j, to which the address match signal is input, transfers the data in the read burst buffer 28i to the device that has output the read request.

In this way, the common RAM in the CNC is
When a read request for consecutive addresses is output, the read cycle can be completed in a short time by transferring the data stored in the read burst buffer 28i. Therefore, the latency of the MMC CPU is reduced and the data processing capability of the entire system is improved.

In the above example, the common RAM in the CNC is described as being connected to the local bus of the CNC, but a common RAM directly connected to the serial bus controller of the CNC is provided. In some cases. In this case, whether or not to perform the read burst transfer can be switched according to the read request from the MMC. That is, in the case of a read request to the common RAM connected via the local bus, read burst transfer is not performed and only the data of the requested address is accessed. Then, in the case of a read request to the common RAM directly connected to the serial bus controller, read burst transfer is performed.

As described above, the read burst transfer is performed by the common RA directly connected to the serial bus controller.
By limiting the access to M, the local bus of the CNC is not occupied more than necessary when accessing the common RAM connected via the local bus. As a result, it is possible to prevent the read burst transfer from adversely affecting the data processing speed of the CNC.

[0044]

As described above, according to the present invention, when a read request for the memory in the slave unit is output from the master unit, the slave unit sends to the master unit the first data of the requested address and the first data. Since the second data of the next address is transferred, when the master unit outputs read requests to consecutive addresses, the second data received in advance is sent to the device that issued the read request. It can be transferred and the read cycle can be completed in a short time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of the present invention.

FIG. 2 is a block diagram showing a configuration of a numerical control system for carrying out the present invention.

FIG. 3 is a diagram showing an example of a packet format.

FIG. 4 is a block diagram showing an internal configuration of a serial bus controller on the MMC side.

[Explanation of symbols]

 1 Master Unit 1a Read Request Transmission Means 1b Read Data Control Means 1ba Buffer 2 Slave Unit 2a Memory Access Control Means 2b Memory 3 Transmission Line

Claims (5)

[Claims] 1. In a memory access system of a system in which a master unit and a slave unit are connected via a transmission line, a read request for an arbitrary address of a memory provided in the master unit is provided. Read request transmission means for transmitting via a transmission line; and a first data of the requested address, which is provided in the slave unit and receives the read request.
And a memory access control means for transmitting second data at an address next to the address to the master unit. 2. In a memory access method of a system in which a master unit and a slave unit are connected via a transmission line, a read request to an arbitrary address of a memory provided in the master unit and lastly made to the slave unit It is determined whether the requested data is continuous data with the accessed data. When the continuous data is requested, an address match signal is output, and when the non-continuous data is requested, the read request is issued. Read request transmitting means for transmitting via the transmission line; and a first data of the requested address, which is provided in the slave unit and receives the read request.
And memory access control means for transmitting the second data of the address next to the address via the transmission line, and the first access means provided in the master unit and received.
Data of the above is transferred to the device which outputs the read request, the second data is stored in the buffer, and when the address match signal is output, the second data in the buffer is read. A memory access method comprising: a read data control unit that transfers the request to a device that outputs the request. 3. The read data control means determines the type of data by decoding the headers of the first data and the second data transferred as a packet. 2. The memory access method described in 2. 4. The memory access method according to claim 2, wherein the master unit is a man-machine controller. 5. The memory access method according to claim 2, wherein the slave unit is a numerical controller.