JPH08255142A - Parallel processor device - Google Patents

Abstract

PURPOSE: To provide a parallel processor device which can properly process a video signal, etc., in real time and properly perform other processing without exerting any influence on the real-time processing of the video signal. CONSTITUTION: The parallel processor device 10 transmits data by plural unit processors 11a-11n through a common transmission line 13 in synchronism with a synchronizing signal inputted from a synchronizing signal transmission line 15. Then a processing regarding the data transmitted through the common transmission line 13 is performed within a cycle of the synchronizing signal in synchronism with the synchronizing signal. In the cycle, an individual transmission line 14 connecting the processors 11a-11n in a ring is monitored in a free period wherein the processing regarding the data transmitted through the common transmission line 13 ends, and the transmission and reception of data transmitted by the individual transmission line 14 and a processing based upon the data are performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a parallel processor device suitable for real-time processing of video signals, for example.

[0002]

2. Description of the Related Art Digitization of video signals and audio signals (hereinafter, both are collectively referred to as AV data) has led to digitization in broadcasting stations, and various devices such as recording devices, editing devices and reproducing devices in stations have The computer performs predetermined processing and is controlled by the computer. Further, with the progress of image compression technology and data recording technology, processing / accumulation of AV data has become easy, and devices that perform larger scale and advanced processing have appeared.

For example, AV data input from a plurality of input systems is stored, or A stored in advance is stored.
An AV server device is also being realized in which V data is used to appropriately output images to a plurality of channels while appropriately performing editing or the like in response to requests that occur successively. As a processing unit that actually performs image processing and the like in such an AV processing unit, and a control unit that controls those processing units, parallel processors each having a plurality of processors due to their processing amount and parallelism. It is often a configuration. For example, one processor performs predetermined image processing for each predetermined area on the screen, or one processor is assigned for each output channel to perform predetermined control.

[0004]

An ordinary parallel processor is sufficient for editing in cases where real-time processing is not required, but real-time control such as a switcher for actually sending data is performed. When attempting to control a necessary video signal processing device by a plurality of processors, it is necessary that the processors be perfectly synchronized. That is, it is necessary to control each video processing device in, for example, a field unit and further arrange the progress status of the processing in a pixel unit in consideration of the communication delay between the processors. Therefore, it is difficult to realize such a video signal processing device in an ordinary parallel processor having a plurality of processors and simply having a mutual communication function.

Further, in the video signal processing device as described above, it is necessary to perform processing other than real time processing of the video signal. For example, it is processing such as status sense, self-diagnosis, or parameter setting. However, if a plurality of parallel processors are perfectly synchronized and real-time processing of a video signal is performed at a field cycle of 1/60 seconds, for example, there is a problem that other processing as described above cannot be performed. In particular, data transmission becomes a bottleneck, and such other processing cannot be instructed. If such transmission is forcibly performed, it may affect the real-time processing of the video signal as described above.

Therefore, an object of the present invention is to perform parallel processing in which real-time processing of a video signal or the like can be appropriately performed, and other processing can be appropriately performed without affecting the real-time processing of the video signal. To provide a processor device.

[0007]

In order to solve the above-mentioned problems, first, a common synchronization signal is input to a plurality of processors so that data transmission via a bus and processing in each processor are completed between the plurality of processors. It was done in synchronization with. In addition, data transmission means between each processor is provided separately from the data transmission means via the bus used for real-time processing of video signals, and processing data and control data that do not require real-time processing are transmitted by this transmission path. By doing so, it is possible to avoid that data transmission becomes an obstacle and efficient processing cannot be performed.

Therefore, the parallel processor device of the present invention includes a plurality of unit processors, a synchronization signal transmission line for inputting a common synchronization signal as an external interrupt signal to the plurality of unit processors, and each of the plurality of unit processors. At least one communication bus that is connected and performs data transmission between the plurality of unit processors based on a synchronization signal input through the synchronization signal transmission path and the plurality of unit processors are directly connected in order. However, it has a ring-shaped communication path for transmitting data between the plurality of unit processors independently of the transmission of data via the communication bus, and in the plurality of unit processors, the communication bus is provided. The processing related to the data transmitted via the ring communication path is executed with priority over the processing related to the data transmitted via the ring communication path. That.

[0009]

According to the parallel processor device of the present invention, data is transmitted / received via the communication bus in each of the plurality of unit processors in synchronization with the synchronization signal input from the synchronization signal transmission line. Furthermore, each unit processor performs a predetermined process in the cycle of the synchronization signal so that data can be transmitted and received in synchronization with the synchronization signal. Also,
During the idle period of the periodic processing relating to the data transmitted / received via the communication bus, the ring communication path is monitored, and transmission / reception of data transmitted by the ring communication path and processing based on the data are performed. To do.

[0010]

EXAMPLES The parallel processor system of the first embodiment of the first embodiment the present invention with reference to FIGS. 1 and 2 will be described. FIG. 1 is a block diagram showing the configuration of a parallel processor device according to the first embodiment of the present invention.
The parallel processor device 10 includes processors 11a to 11
n, communication bus 13, ring-shaped transmission lines 14a to 14n,
Also, it has a synchronization signal transmission line 15.

First, the configuration of the parallel processor device 10 will be described. The parallel processor device 10 has a configuration in which n processors 11a to 11n are connected as illustrated. An identification number of the processor i (i = a to n) (hereinafter referred to as a processor ID) is assigned to each processor i (i = a to n). Each of the processors 11a to 11n is a general-purpose processor that incorporates an arithmetic circuit, a memory, an I / O unit, and the like. In the memory, the processor ID, a program for performing a predetermined process, and parameters required for executing the program are recorded in advance.

The I / O unit of each processor 11i (i = a to n) has at least three I / O ports, one of which is connected to the communication bus 13 (hereinafter referred to as bus 13). , The remaining two I / O ports are directly connected to the I / O ports of different processors by dedicated transmission lines.
The bus 13 is a common transmission line having a predetermined bit width, and is provided from the outside of the parallel processor device 10 to the processor 11
Data transmission to a to 11n and processor 11
Data is mutually transferred between a to 11n. Processor 1
A dedicated transmission line for directly connecting 1a to 11n sequentially connects n processors 11a to 11n, and constitutes a ring-shaped transmission line 14 as a whole.

Further, each processor 11i (i = a to n)
One of the interrupt inputs of is connected to the synchronization signal transmission line 15. Therefore, by applying a predetermined signal to the synchronization signal transmission line 15, the processors 11a to 11a
All n are interrupted at the same time, and data transfer and processing can be synchronized.

As described above, in the parallel processor device 10, the n processors 11a to 11n are connected to the bus 13
And the ring-shaped transmission line 14 are coupled, and the data can be transmitted between the processors via either the bus 13 or the ring-shaped transmission line 14.

The operation of such a parallel processor device 10 will be described. In each of the n processors 11a to 11n, a processing program previously recorded in the memory of the processor 11a to 11n is started based on the synchronization signal input from the synchronization signal transmission line 15, and the processing based on the program is started. To do. Each processor 11a-1
When the processing is started at 1n, first, n processors 1
Any of 1a to 11n dominates the bus, and the data packet is transmitted to the bus 1 at a predetermined timing synchronized with the synchronization signal.
Send to 3.

Each processor receiving the data packet reads out data for the own processor from the data packet based on the processor ID, and performs a predetermined process on the data or according to the data. Further, the processor which controls the bus 13 next and which sends out the data specified by the data of the data packet sends out the data packet of a predetermined format to the bus 13 at the timing of the next synchronization signal. After that, this process is repeated for each cycle.

Here, the format of the data packet transmitted via the bus 13 will be described with reference to FIG. FIG. 2 is a diagram showing a format of data transmitted by the bus 13. The data packet is the ID of the processor that controls the bus 13 in the next cycle, that is, the ID of the processor that sends the data packet in the next cycle.
And the transmission data for each processor is recorded.
The transmission data to each processor is composed of a map portion in which each processor ID and the address of the actual data are recorded in a pair, and a data block portion in which the actual data is recorded.

When a data packet of such a format is transmitted, each processor searches its own processor ID from the map section, reads the data address recorded in the word next to the processor ID, and based on that address. Read the data for the local processor in the data block. Also, each processor reads the ID of the processor that sends the data packet in the next cycle recorded in the first word of the data packet, and if it is its own processor ID, assembles the data packet for sending as appropriate, Data is sent to the bus 13 at the next cycle.

Further, each of the processors 11a to 11n transmits / receives data via the ring-shaped transmission line 14 during periodic transmission / reception of data via the bus 13 and processing based on the transmitted / received data, and Perform processing based on the data. That is, each processor 11a-1
1n is an I / I connected to the ring-shaped transmission line 14 when the arithmetic circuit becomes idle after the periodical processing is completed.
Check the O port to see if there is input data.

If the data has been transmitted, the destination processor ID of the data is checked. As a result of the check, if the data is data for the own processor, the data is stored in the memory and a predetermined process is performed according to the data. When it is necessary to send the processing result, the sending data is assembled and the ring-shaped transmission line 1
4 If the data transmitted via the ring-shaped transmission line 14 is not data for the own processor, the data is transferred to the ring-shaped transmission line 14 from another I / O port different from the received I / O port. Is output as is.

The transmission / reception of the data transmitted by the ring-shaped transmission line 14 and the processing based on the data are
As described above, all the processes are performed during the idle period in which the transmission / reception and the processing of the data for each cycle based on the synchronization signal of the synchronization signal transmission line 15 are completed. If there is no free period or if there is no sufficient period, the processing relating to the data transmitted by the ring-shaped transmission line 14 is performed little by little over a long period until a free period occurs. Therefore, by performing these processes, the periodical process is not put in a waiting state.

As described above, in the parallel processor device 10 of the first embodiment, any one of the n processors 11a to 11n is provided for each cycle on the basis of the synchronization signal input via the synchronization signal transmission line 15. Sends data as appropriate,
The other processors receive the data and execute a predetermined process according to the data for the own processor in the data. Therefore, each processor can transmit and process data in perfect synchronization.
Even if it is necessary to parallelize the processing progress statuses, it is possible to perform appropriate processing.

Further, since the processor that sequentially controls the bus is determined according to the processor ID recorded in the data to be transmitted, overhead time such as bus arbitration is not required, and high-speed processing is possible.

Data that does not need to be executed in real time at high speed in synchronization with each processor is transmitted to each processor via the ring-shaped transmission path 14, and each processor appropriately processes the data between the synchronization processing. Therefore, the processing can be appropriately performed without interfering with the synchronization processing. Further, it is not necessary to separately provide a processor for such processing that does not need to be executed in real time.

[0025] As a second embodiment of the second embodiment the present invention when applied to the parallel processor system to the image processing apparatus will be described with reference to FIGS. 3 and 4 for the present invention. FIG. 3 is a block diagram showing the configuration of an AV server device to which the parallel processor device of the present invention is applied. This AV server device is an AV data supply device that records various AV data composed of video signals and audio signals in a large-capacity data recording device, outputs the AV data appropriately in response to a request, and edits or broadcasts. .

First, the configuration and operation of the AV server device 90 will be described. The AV server device 90 includes a video signal encoding device 91, a circuit switching device 92, a data storage device 93, a video signal decoding device 94, a synchronous system control execution device 20,
It also has a control command transmission device 96. The various material AV data obtained by interviews and the like are recorded in the video signal encoding device 9
It is highly efficient coded by 1 and is stored in the desired data storage device 93 via the circuit switching device 92.

The data storage device 93 is composed of a randomly accessible recording medium such as an MO disk, and can immediately reproduce and output the recorded AV data. Then, a predetermined AV data supply request signal is sent from the application system 97 such as an editing device to the LA.
When input to the control command transmission device 96 via N, each unit is controlled by the synchronous system control execution device 20,
Data is output. That is, the data storage device 9
The requested AV data recorded in No. 3 is reproduced and input to the video signal decoding device 94 via the circuit switching device 92. Then, it is decoded by the video signal decoding device 94 and output to the editing device.

As described above, in the AV server device 90, the plurality of video signal encoding devices 91, the circuit switching device 92, the data storage device 93, and the video signal decoding device 94 are completely synchronized, that is, the field. It is necessary to synchronize and operate in units or frames.
The AV server device 90 is a synchronization system control execution device 20 that performs control by completely synchronizing the respective video devices.
The parallel processor device of the present invention is applied to.

The configuration of the synchronous system control execution device 20 will be described with reference to FIG. FIG. 4 is a block diagram showing the configuration of the synchronous system control execution device 20.
This synchronous system control execution device 20 has basically the same configuration as the parallel processor device 10 of the first embodiment, except that one processor among a plurality of processors manages the other processors and operates as a host device. I used it only for the interface.

The synchronous system control execution device 20 has a structure in which one event management processor 21 and n video equipment control processors 22a to 22n are connected as shown in the figure. The event management processor 21 and the video equipment control processors 22a to 22n are provided with identification numbers of the processors (hereinafter referred to as processor IDs). Further, these processors are general-purpose processors each including an arithmetic circuit, a memory, an I / O unit, and the like, like the processors of the parallel processor device 10 of the first embodiment. Programs and parameters are recorded.

The I / O unit of these processors has a plurality of I / O units.
/ O port, one of which is connected to the bus 23 and two
Each of them is directly connected to the I / O port of another processor by a ring-shaped transmission line 24. The I / O unit of the video equipment control processor 22 has a plurality of I / O ports connected to the various video equipments described above. The video equipment control processor 22 controls each video equipment by this connection line.
The I / O unit of the event management processor 21 is connected to the control command transmission device 96, which is a higher-level device, by a dedicated transmission line. The event management processor 21 obtains the control information of each video device from the control command transmission device 96 through this connection line.

The configurations of the bus 23 and the ring-shaped transmission line 24 are the same as those of the bus 13 and the ring-shaped transmission line 14 of the parallel processor device 10. Synchronous system control execution device 20
The field sync signal of the video signal is input to the synchronization signal transmission path 25 of FIG. Each processor of the synchronous system control execution device 20 sequentially performs each processing in the field cycle in synchronization with this synchronization signal.

Next, the synchronous system control execution device 20
The operation of will be described. Event management processor 21
Synchronizes with a synchronization signal input as an external interrupt via the synchronization signal transmission line 25 to transmit a data packet,
N video equipment control processors 22a via the bus 13
Broadcast to ~ 22n. The structure of this data packet is the same as that of the first embodiment shown in FIG. The data packet transmitted by broadcasting is stored in the local memory in each of the video equipment control processors 22a to 22n.

Each video equipment control processor 22a-22n
Then, the data packet in its own local memory is read and the next sender processor ID stored in the first word is checked. If this processor ID is the ID of its own processor, the video device control processor 2
2i (i = a to n) becomes the data transmission processor in the next cycle. At this time, the first word in the data packet created by the video equipment control processor 22i,
That is, the next sender processor ID sets the processor ID of the event management processor 21.

As a result, the event management processor 21
From one of the video device control processors 22a to 22n,
Data is alternately transmitted from i to the event management processor 21 and the other video equipment control processor 22 via the bus 23 in units of field intervals. Therefore, at the time when the period of n frames has passed, all the event management processors 21 and the video equipment control processors 22.
The mutual data transmission is completed.

Further, the diagnostic program and the processing that operates asynchronously with the video signal without any trouble are sequentially transmitted between the video equipment control processors 22 via the ring-shaped transmission path 24. This processing is the same as in the first embodiment.

As described above, in the AV server device 90 of the second embodiment, since the parallel processor device of the present invention is used as the synchronous system control execution device 20, the event management processor is used in the first field of each frame of the video signal. 21 to n video equipment control processors 22a to 22n
Data can be transmitted to the event management processor 21 from the arbitrary video equipment control processor 22i in the second field. Therefore, it is possible to align the operation of all video equipment on a frame-by-frame basis, and it is possible to realize an advanced AV server device capable of performing highly accurate video editing in real time.

The parallel processor device of the present invention is not limited to the first and second embodiments, and various modifications can be made. For example, each processor constituting the parallel processor device may be a general-purpose processor as in this embodiment, a dedicated processor for a special purpose, or a mixture thereof. Also, each unit processor is
The present invention is not limited to the processor formed by one chip, but may be a chip set formed by a plurality of chips or an arithmetic processing unit having a structure such as a processor board formed on a substrate. Further, the architecture of the communication bus (bus) is not limited at all, and any type of bus may be used. The format of the data packet is not limited to the example shown in FIG. 2, and any format may be used.

Further, details of various processes not explicitly shown in the present embodiment may be arbitrary methods which are usually performed. For example, the end of data for each processor may be obtained from the data start address for the next processor in the map section, or an EOD (end of data) code may be added to the data block, and the end of data may be detected by detecting this code. May be detected.

Further, the case where the parallel processor of the present invention is applied to the AV processor has been described as the second embodiment, but the use of the parallel processor is not limited to the AV processor. It can be effectively applied to a general-purpose computer device and various dedicated control devices.

[0041]

When the parallel processor device of the present invention is used, the processes in the plurality of processors are performed in perfect synchronization, so that the progress status of the processes in the respective processors can be aligned and the parallel processes can be performed. . Therefore, it is possible to provide a parallel processor device suitable for use in a device that requires strict real-time control, such as a switcher for actually transmitting data in a broadcasting station or the like.

Further, since data can be transmitted between the processors independently of the data transmission relating to the real-time processing, data relating to processing which does not require real-time processing such as status sensing, self-diagnosis, or parameter setting. Can be transmitted by this transmission path. Therefore, these processes can be performed at any time in the gap of the real-time processing, and it is possible to prevent the data transmission from becoming an obstacle and preventing efficient processing.

That is, according to the present invention, real-time processing of a video signal or the like can be appropriately performed, and further,
It is possible to provide a parallel processor device capable of appropriately performing other processing without affecting the real-time processing of the video signal.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a parallel processor device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing an example of a data format transmitted by a bus.

FIG. 3 is a block diagram showing a configuration of an AV server device to which a parallel processor device according to a second embodiment of the present invention is applied.

FIG. 4 is a block diagram showing a configuration of a parallel processor device according to a second embodiment of the present invention.

[Explanation of symbols]

10 ... Parallel processor device 11 ... Processor 13 ... Communication bus 14 ... Ring transmission line 15 ... Synchronous signal transmission line 20 ... Synchronous system control execution device 21 ... Event management processor 22 ... Video equipment control processor 23 ... Communication bus 24 ... Ring-shaped transmission line 25 ... Synchronous signal transmission line 90 ... AV server device 91 ... Video signal coding device 92 ... Circuit switching device 93 ... Data storage device 94 ... Video signal decoding device 96 ... Control command transmission device 97 ... Application system

Claims (1)

[Claims] 1. A plurality of unit processors, a synchronization signal transmission line for inputting a common synchronization signal as an external interrupt signal to the plurality of unit processors, and a synchronization signal transmission line connected to each of the plurality of unit processors. At least one communication bus for transmitting data between the plurality of unit processors based on a synchronization signal input by, and each of the plurality of unit processors are directly connected in order,
There is a ring-shaped communication path for transmitting data between the plurality of unit processors independently of transmission of data via the communication bus, and in the plurality of unit processors, via the communication bus. A parallel processor device that executes a process related to transmitted data with priority over a process related to data transmitted via the ring communication path.