JPH08249267A - Dma controller - Google Patents

Abstract

PURPOSE: To provide a DMA controller suitable for the cyclic highspeed transfer of medium data. CONSTITUTION: An address generation part 1 for successively generating addresses so as to control the execution of one-block transfer every time start signals 115 are asserted and asserting standby request signals 114 every time the execution of the one-block transfer ends, a timer part 2 for asserting repeat request signals 111 in a cycle longer than the time required for the execution of the one-block transfer and a control part 10 for activating the timing operation of the timer part 2 and asserting the start signals 115 to the address generation part 1 when the start request signals 112 are asserted are incorporated in this DMA controller 200. The control part 10 activates the timing operation of the timer part 2 and asserts the start signals 115 even when the timer part 2 asserts the repeat request signals 111 after the address generation part 1 asserts the standby request signals 114 and before stop request signals 113 are asserted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA controller that handles media data in a computer system.

[0002]

2. Description of the Related Art In recent years, with the spread of computer systems, the need for multimedia processing such as handling media data such as voices and moving pictures has increased. Since such multimedia processing is simple data transfer repetitive processing and high speed is required, the program IO control method (P
Instead of the IO control method), the direct memory access control method (DMA control method) is adopted.

In a conventional computer system having a CPU, a main memory, an input device, an output device and a DMA controller, between the input device and the main memory, between the main memory and the output device, between different areas of the main memory, or When performing periodic high-speed transfer of media data between the input device and the output device, the interrupt processing program is started by the periodic interrupt from the timer to the CPU,
The operation of the DMA controller is controlled by the interrupt processing program. Specifically, in the first step, the CPU sets appropriate values for one block transfer in the transfer source address register, transfer destination address register, and transfer size register of the DMA controller. In the second step, the interrupt processing program is activated by the interrupt from the timer to the CPU. By executing this interrupt processing program, the CPU issues a request to start 1-block transfer to the DMA controller. In the third step, in response to this transfer start request, DM
The A controller controls the execution of one block transfer. 1
When the execution of the block transfer is completed, the DMA controller notifies the CPU to that effect. When continuing the transfer of the media data, the processing from the second step onward is repeated.

[0004]

In the conventional configuration as described above, the interrupt processing program is activated by a periodic interrupt to the CPU, and the DM is executed by the interrupt processing program.
Since the periodical transfer of the media data is realized by controlling the operation of the A controller, it has the following problems.

First, the CPU needs a periodic interrupt processing program for controlling the operation of the DMA controller. Therefore, the size of the program becomes large.

Secondly, since interrupts are periodically generated in the CPU and the interrupt processing program is executed each time, C
The burden on the PU increases.

Third, high real-time performance of the CPU is required, which increases the cost of the computer system. When handling media data, it is important to maintain the continuity of the data, and it is necessary to set the processing time from when an interrupt is generated in the CPU to when the DMA controller is activated to a fixed time or less. Therefore, software and hardware for realizing the high real-time performance of the CPU are required.

[0008] Fourth, when a plurality of media having different periods are handled at the same time, the higher real-time property is CP.
Required by U. In this case, simultaneous interrupts are generated in the CPU in a cycle of the least common multiple of the handling cycle of each medium, and it becomes necessary for the interrupt processing program to determine which medium corresponds to the transfer. Therefore, the load on the CPU is further increased.

In view of the above problems, an object of the present invention is to provide a DMA controller suitable for periodic high-speed transfer of media data.

[0010]

In order to achieve the above object, the present invention adopts a structure of a DMA controller having a timer unit for controlling restart of block transfer.

Specifically, the DMA controller of the present invention controls the execution of one block transfer each time the start signal is asserted, and asserts the wait request signal each time the execution of one block transfer ends. First means and the first
For asserting the repeat request signal in a cycle longer than the time required to execute one block transfer under the control of the means of
And a second request asserts a repeat request signal after the first request asserts a wait request signal and before the stop request signal is asserted. Adopts a configuration including a third means for activating the timing operation of the second means and asserting a start signal to the first means.

[0012]

According to the DMA controller of the present invention, the third means has three internal states of a transfer stop mode, a transfer execution mode and a standby mode. When the start request signal is asserted, the third means transits from the transfer stop mode to the transfer execution mode to activate the timing operation of the second means and assert the start signal to the first means. The first means receives the assertion of the start signal, controls the execution of the one block transfer, and asserts the wait request signal at the end of the one block transfer. At this time, the third means makes a transition from the transfer execution mode to the standby mode in response to the assertion of the standby request signal. The second means is adapted to assert the repeat request signal in a cycle longer than the time required to execute one block transfer under the control of the first means, and in the standby mode, the second request is issued before the stop request signal is asserted. When the repeat request signal is asserted from the means of, the third means:
A transition is made from the standby mode to the transfer execution mode to restart the timing operation of the second means and reassert the start signal to the first means so that the next block transfer will be executed. That is, the block transfer is automatically restarted without CPU intervention.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a schematic configuration of a computer system including a DMA controller according to an embodiment of the present invention. In FIG. 1, reference numeral 200 denotes a DM according to an embodiment of the present invention.
A controller, 201 is CPU, 202 is main memory, 2
Reference numeral 03 is an output device, 204 is an input device, and 3 is a system bus connecting these circuit blocks. The system bus 3 has an address bus and a data bus.

The DMA controller 200 has a first transfer mode for executing a DMA transfer between the input device 204 and the main memory 202, and the main memory 202 and the output device 20.
A second transfer mode for performing a DMA transfer to and from
It has a third transfer mode for executing a DMA transfer between different areas of the main memory 202 and a fourth transfer mode for executing a DMA transfer between the input device 204 and the output device 203. The transfer size is in units of 1 word (4 bytes). DMA controller 2
Reference numeral 00 denotes a programmable circuit block having a plurality of control registers built therein as described later, and an address for specifying the control register and data (control information) to be written in the control register specified by the address.
And PIO from the CPU 201 via the system bus 3.
Supplied by control method. The same PIO control method is adopted for the input device 204 and the output device 203.

The internal structure of the DMA controller 200 is shown in FIG. In FIG. 2, reference numeral 1 is an address generation unit for sequentially generating addresses so as to control execution of block transfer, 2 is a timer unit for controlling restart of block transfer, and 10 is a whole internal operation of the DMA controller 200. Is a data buffer for temporarily holding data, and 12 is a bus interface that functions as an interface with the system bus 3. Bus interface 12 and data buffer 1
An internal data bus 100 is provided between the address generator 1, the address generator 1, and the timer unit 2, and an internal address bus 101 is provided between the bus interface 12 and the address generator 1. The timer unit 2 stores a frequency division number register 50 for holding the set frequency division number data, a counter 51 for counting a clock, a count value of the counter 51 and data held by the frequency division number register 50. The internal data bus 100 is connected to the frequency division number register 50. 110 is a counter reset signal, 111 is a repeat request signal, 112 is a start request signal, 113 is a stop request signal, 114 is a standby request signal, and 115 is a start signal. Comparator 52 of timer unit 2
Asserts the repeat request signal 111 when the count value of the counter 51 and the data held in the frequency division number register 50 match.

The internal configuration of the address generator 1 is shown in FIG. In FIG. 3, 13 is a transfer size register for holding the set transfer size, 14 is a transfer destination address register for holding the set transfer destination address,
Reference numeral 15 is a transfer source address register for holding the set transfer source address. These registers 13, 1
The setting data of 4 and 15 are supplied through the internal data bus 100. Reference numeral 16 is a comparator for outputting the standby request signal 114. 20, 21, 2
Reference numeral 2 is a register for holding the values of the transfer size, the transfer destination address, and the transfer source address being updated.
Reference numerals 23, 24, 25 and 26 are multiplexers, 27 is a decrementer for subtracting 1 from the input value, and 28 and 29 are incrementers for adding 4 to the input value. The comparator 16 asserts the standby request signal 114 when the value of the transfer size being updated (output of the register 20) becomes 0. The multiplexer 26 switches between the value being updated of the transfer destination address (output of the register 21) and the value being updated of the transfer source address (output of the register 22) and outputs the value to the internal address bus 101.

FIG. 4 is a state transition diagram of the control unit 10 in FIG. The control unit 10 has three internal states T0, T1, T
I have 2. T0 indicates a transfer stop mode, T1 indicates a transfer execution mode, and T2 indicates a standby mode. When the start request signal 112 is asserted from the bus interface 12 according to the control information from the CPU 201 after the initialization of the various control registers, the internal state of the control unit 10 transits from T0 (initial state) to T1, and the control is performed. The counter reset signal 110 and the start signal 115 are asserted from the section 10. As a result, the timer unit 2 starts the time counting operation, and at the same time, the address generation unit 1 starts the transfer control of one block. When the address generation unit 1 asserts the standby request signal 114 with the completion of the transfer of one block, the internal state of the control unit 10 transits from T1 to T2. When the stop request signal 113 is asserted from the bus interface 12 in response to the control information from the CPU 201 in the internal state T2 of the standby mode, the internal state of the control unit 10 transits from T2 to T0, and the block transfer operation is completed. . On the other hand, the timer unit 2 is adapted to assert the repeat request signal 111 at a cycle longer than the time required to execute one block transfer under the control of the address generation unit 1, and repeats from the timer unit 2 in the internal state T2 in the standby mode. When the request signal 111 is asserted, the internal state of the control unit 10 becomes T
The transition from 2 to T1 occurs, and the control unit 10 asserts the counter reset signal 110 and the start signal 115. As a result, the timing operation of the timer unit 2 is restarted and at the same time,
The transfer control of the next block by the address generator 1 starts.

FIG. 5 shows the overall operation of the DMA controller 200, and S1 to S7 in the figure are the reference numerals assigned to the respective steps. Details of the block transfer step S4 in FIG. 5 are shown in FIG.

A case where sound is reproduced by the computer system shown in FIG. 1 will be specifically described with reference to FIGS. 5 and 6. The voice data is input from the input device 204,
It is assumed that the audio is reproduced by supplying the audio data to the output device 203. DMA controller 2
The fourth transfer mode is selected as the 00 transfer mode. Unique addresses are assigned to the transfer size register 13, the transfer destination address register 14, the transfer source address register 15, and the frequency division number register 50 of the DMA controller 200. Similarly, an address for transfer control is also assigned to the DMA controller 200, and the CPU 201 controls the operation of the DMA controller 200 by writing a value for a transfer start request or a value for a transfer stop request to this address. Further, an address and a control value are assigned to the start / stop of the audio data supply of the input device 204 and the start / stop of the audio reproduction of the output device 203, respectively.

In step S1 in FIG. 5, the transfer source address register 15, the transfer destination address register 14, the transfer size register 13 and the frequency division number register 50 of the DMA controller 200 are initialized. At this time, the internal state of the control unit 10 is the transfer stop mode T0. For example,
When initializing the transfer source address register 15,
U201 is the input device 2 according to the PIO control method.
Reference numeral 04 designates the start address of the block storing the audio data in the data bus of the system bus 3, and the address assigned to the transfer source address register 15 in the system bus 3.
To the address bus to generate a write transaction on the system bus 3. The bus interface 12 looks at the contents of the address bus of the system bus 3 and stores the value of the data bus of the system bus 3 in the transfer source address register 15. Transfer destination address register 1
4. Initialization of the transfer size register 13 and the frequency division number register 50 is also executed according to the same PIO control method. It should be noted that the frequency division register 50 includes the address generator 1
The value obtained by dividing the audio reproduction cycle longer than the time required to execute the one-block transfer under the control of 1) by the clock cycle of the counter 51 is set as the frequency division number data.

In step S2, the DMA controller 2
00 waits without doing anything until there is a transfer start request from the CPU 201. The CPU 201 requests the DMA controller 200 to start the transfer by writing the value for the transfer start request to the address assigned for the transfer control.
At the same time, by writing the value for the supply start request to the address assigned to the audio supply control of the input device 204, the input device 204 is started to supply the audio data, and the audio reproduction control of the output device 203 is performed. By writing the value for the reproduction start request to the address, the output device 203 is caused to start reproducing the sound. DMA
When the bus interface 12 of the controller 200 recognizes that it is a transfer start request, it asserts a start request signal 112 to the control unit 10. Start request signal 112
Is asserted, the control unit 10 changes the internal state from the transfer stop mode T0 to the transfer execution mode T1.

In step S3, the control unit 10 resets the counter 51 to 0 by asserting the counter reset signal 110.
Then, the timer unit 2 is reset and the timekeeping operation of the timer unit 2 is started. In the timer unit 2, the counter 51 is automatically incremented by the clock, and the comparator 52 compares the count value of the counter 51 with the data held in the frequency division number register 50.

In step S4, the control unit 10 causes the address generation unit 1 to start the transfer control of one block by asserting the start signal 115. As a result, under the control of the DMA controller 200, data transfer of the transfer size from the transfer source address to the transfer destination address is executed. The address generator 1 asserts the wait request signal 114 at the end of the one-block transfer, as described later. By asserting the standby request signal 114, the control unit 10 changes the internal state from the transfer execution mode T1 to the standby mode T2.

In step S5, the control unit 10 checks whether or not the stop request signal 113 from the bus interface 12 is asserted. When stopping the DMA transfer, the CPU 201 requests the DMA controller 200 to stop the transfer by writing the value for the transfer stop request to the address assigned for the transfer control. When the bus interface 12 recognizes that it is a transfer stop request, it asserts a stop request signal 113 to the control unit 10. When the stop request signal 113 is asserted, the control unit 10 changes the internal state from the standby mode T2 to the transfer stop mode T0 and proceeds to step S6. By asserting the counter reset signal 110, the control unit 10 causes the counter 51 of the timer unit 2 which is operating to count time. After resetting to 0, the transfer control is ended. in this case,
The operation of the DMA controller 200 ends.

When the stop request signal 113 is not asserted, the process proceeds from step S5 to step S7 in the standby mode T2, and the control section 10 checks whether or not the repeat request signal 111 is asserted from the timer section 2. Repeat request signal 11
When 1 is not asserted, the process returns to step S5 in the standby mode T2 and waits until the stop request signal 113 or the repeat request signal 111 is asserted. The comparator 52 of the timer unit 2 includes a count value of the counter 51 and a frequency division number register 5
When the held data of 0 matches, the repeat request signal 111 is asserted. When the repeat request signal 111 is asserted, the control unit 10 changes the internal state from the standby mode T2 to the transfer execution mode T1 and returns to step S3. Therefore,
The timer unit 2 is restarted and the transfer control of the next block is automatically started.

Next, the block transfer step S4 in FIG.
The internal operation of the address generator 1 (see FIG. 3) in
This will be described in detail with reference to FIG. S11 to S11 in FIG.
S15 is a code given to each step.

In step S11, in response to the assertion of the start signal 115 from the control unit 10, the multiplexer 2
Transfer size register 13, transfer destination address register 14, and transfer source address register 1 via 3, 24, and 25.
The stored data of No. 5 is stored in the registers 20, 21, 22 respectively.

In step S12, the comparator 16 compares the value held in the register 20 (value being updated in transfer size) with 0. When the value held in the register 20 becomes 0, the comparator 16 asserts the wait request signal 114. Then, the transfer control of one block is completed.

If the value held in the register 20 is not 0, the process proceeds from step S12 to step S13, and the bus interface 12 transfers the value held in the register 22 (the value during the updating of the transfer source address) to the address bus of the system bus 3. Output and initiate a read transaction. The read data is stored in the data buffer 11.

In step S14, the bus interface 12 outputs the value held in the register 21 (the value of the transfer destination address being updated) to the address bus of the system bus 3 and the data of the data buffer 11 to the data bus of the system bus 3. Then, a write transaction is initiated.

In step S15, the decrementer 27 and the multiplexer 23 are used to subtract 1 from the value held in the register 20. At the same time, the incrementer 28 and the multiplexer 24 are used to change the value held in the register 21 to 4
Then, 4 is added to the value held in the register 22 by using the incrementer 29 and the multiplexer 25. Then, the process returns to step S12.

By the operations of the above steps S11 to S15, 1 is changed from the input device 204 to the output device 203.
The DMA transfer of the voice data of the block is performed. When transferring the next block, the data held in the transfer size register 13, the transfer destination address register 14, and the transfer source address register 15 are stored again in the registers 20, 21, 22 in step S11. Data transfer of the same transfer size to the same transfer destination address is executed.

As described above, according to this embodiment, the CPU
Since the timer unit 2 incorporated in the DMA controller 200 automatically restarts the block transfer after the 201 gives the transfer start request to the DMA controller 200, the CPU 201 can load the media data without burdening the media data. High-speed transfer can be performed periodically. Moreover,
Since the restart of the block transfer is controlled at high speed by the special hardware of the timer unit 2 including the frequency division number register 50, the counter 51, and the comparator 52, the continuity of the media data can be easily performed at low cost. Can be kept at. Further, when simultaneously handling a plurality of media having different cycles, the DMA controllers according to the present embodiment are prepared by the number of media, and the frequency division number data according to the handling cycle of each media is divided by each DMA controller. It may be set in the number register. Thereby, it is possible to simultaneously execute the periodic high-speed transfer of each of the plurality of media data without imposing a burden on the CPU.

In the above specific example, the input device 20
4 relating to the DMA transfer between the B.4 and the output device 203
However, according to the DMA controller 200 of the present embodiment, the periodic high-speed transfer of the media data can be performed without burdening the CPU 201 in the first to third transfer modes. can do.

[0035]

As described above, according to the present invention, the structure of the DMA controller having the timer unit for controlling the restart of the block transfer is adopted, and the block transfer is automatically performed without the intervention of the CPU. Since it is restarted, it is not necessary to provide the CPU with a periodic interrupt processing program for controlling the operation of the DMA controller, and the program size is reduced. Further, since it is not necessary for the CPU to execute the periodic interrupt processing program, the load on the CPU is reduced. Also, special hardware for controlling the restart of block transfer is DMA
Since it is provided in the controller, the continuity of media data can be easily maintained at low cost. It is easy to handle the case where a plurality of media having different cycles are handled at the same time.

Therefore, according to the present invention, it is possible to provide a DMA controller suitable for periodic high-speed transfer of media data.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a computer system including a DMA controller according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an internal configuration of a DMA controller according to the embodiment of the present invention in FIG.

3 is a block diagram showing an internal configuration of an address generation unit in FIG.

FIG. 4 is a state transition diagram of a control unit in FIG.

5 is a flowchart showing the operation of the DMA controller of FIG.

FIG. 6 is a flowchart showing details of a block transfer step in FIG.

[Explanation of symbols]

 1 Address Generation Unit (First Means) 2 Timer Unit (Second Means) 3 System Bus 10 Control Unit (Third Means) 11 Data Buffer 12 Bus Interface 13 Transfer Size Register 14 Transfer Destination Address Register 15 Transfer Source Address Register 16 Comparator 20, 21, 22 Register 23, 24, 25, 26 Multiplexer 27 Decrementer 28, 29 Incrementer 50 Dividing number register 51 Counter 52 Comparator 100 Internal data bus 101 Internal address bus 110 Counter reset signal 111 Repeat request Signal 112 Start request signal 113 Stop request signal 114 Standby request signal 115 Start signal 200 DMA controller 201 CPU 202 Main memory 203 Output device 204 Input device

Claims (3)

[Claims] 1. A first means for controlling execution of one-block transfer each time a start signal is asserted, and asserting a wait request signal each time execution of one-block transfer is completed, and the first means. Second means for asserting the repeat request signal in a cycle longer than the time required to execute one block transfer under the control of the means of :, and when the start request signal is asserted or the first means transmits the wait request signal. If the second means asserts the repeat request signal after asserting and before the stop request signal is asserted, it activates the timing operation of the second means and the start signal to the first means. And a third means for asserting. 2. The DMA controller according to claim 1, wherein the first means is a transfer source address register for holding a set transfer source address, and a transfer for holding a set transfer destination address. A DMA controller comprising a destination address register and a transfer size register for holding a set transfer size. 3. The DMA controller according to claim 1, wherein the second means is a frequency division number register for holding set frequency division number data, a counter for counting a clock, and the counter. And a comparator for asserting the repetitive request signal when the count value of 1 is matched with the data held in the frequency division number register.