JPH08248939A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE: To perform the signal processing after sampling by the use of one kind of clock in the case where performing digital processing of plural video signals sampled by the number of samples different from each other. CONSTITUTION: The video signal from an input terminal 1 is digitally converted in an A/D conversion part 2 with the clock from a write clock generating part 7 to be written in a memory part 6 by the amount equivalent to 1H under the write control of a memory controller 6 and then this data are read out by the readout control from the memory controller 6 based on the clock generated in a read clock generating part 8 to be inputted to a picture processing part 4 and are subjected to a picture processing to be transmitted to a display part 5 to be displayed on a screen. Moreover, the on-screen signal synchronized with the read clock is generated in an on-screen signal generating part 9 to be inputted to the picture processing part 4 and then this signal is synthesized with the signal from the memory part 3. Further, the write clock generating part 7 generates clocks having frequencies corresponding to video signal sources and the read clock generating part 8 always generates one king of the clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing circuit, and more particularly to a digital signal processing circuit which processes a video signal sampled at different clocks with one kind of clock without losing effective pixels.

[0002]

2. Description of the Related Art When displaying a video signal sampled at different frequencies on a digital drive type display, a clock corresponding to each signal source is required for signal processing, and there is a problem that timing design is difficult. . Further, when the on-screen signals are combined and displayed, there is a problem that the size of the displayed character changes because the dot clock differs depending on the signal source.

[0003]

SUMMARY OF THE INVENTION In view of the above, the present invention takes one kind for reading and writing the video signal from each signal source at a clock corresponding to each signal source, and writing to the line memory or the like. Use the clock,
An effective pixel is ensured by varying the number of dots in the blanking period of the video signal according to the signal source.

[0004]

In order to solve the above-mentioned problems, the present invention processes a first clock generating unit for generating a clock corresponding to a video signal source and an effective pixel in a horizontal scanning period of the video signal. Second to generate the clock needed for
A / C for converting a video signal into a digital signal by using a clock from the clock generation unit and the clock from the first clock generation unit
A D conversion unit and a memory unit for recording data for the horizontal scanning period from the A / D conversion unit using the clock from the first clock generation unit and reading the data using the clock from the second clock generation unit. An image processing unit for processing the data read from the memory unit, and to provide a digital signal processing circuit for displaying based on the data from the image processing unit.

[0005]

With the above construction, in the digital signal processing circuit according to the present invention, write clocks respectively corresponding to a plurality of video signal sources are generated, and the video signals are converted into digital signals using the write clocks. , Record in line memory. The data in the line memory is read using a required read clock, and the on-screen signals generated in synchronization with the read clock are combined and output. The read clock is a clock having a frequency capable of processing at least effective pixels in any of the plurality of video signals, and the line memory data is the number of dots in the blanking period when the read side frequency and number are small. Is changed to read.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a digital signal processing circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of essential parts of an embodiment of a digital signal processing circuit according to the present invention. In the figure, 1 is a video signal input terminal, 2
Is an A / D conversion unit, and a video signal from the video signal input terminal 1 is input to the A / D conversion unit 2 and is sampled using a clock from a write clock generation unit 7 described later to be converted into a digital signal. A memory unit 3 is composed of a frame memory or a line memory capable of recording data for at least one horizontal scanning period, and records data from the A / D conversion unit 3 using a clock from the write clock generation unit 7. Then, the clock is read by the clock from the read clock generation unit 8 described later. An image processing unit 4 is a memory unit 3.
The read data is processed. A display unit 5 displays on the screen based on a signal from the image processing unit 4. A memory controller 6 controls writing and reading of data in the memory unit 3. The write clock generator 7 generates a plurality of types of clocks corresponding to a plurality of video signals. The read clock generation unit 8 generates one kind of clock capable of processing effective pixels in the horizontal scanning period of any input video signal. An on-screen signal generation unit 9 generates characters to be displayed on-screen in synchronization with the clock from the read clock generation unit 8 and inputs them to the image processing unit 4 to combine them with the signal from the memory unit 3. A control unit 10 controls each unit.

Next, the operation of the digital signal processing circuit according to the present invention will be described. The video signal from the video signal input terminal 1 is input to the A / D converter 2, and the write clock generator 7
It is sampled with the clock of and converted into a digital signal. If the video signal source is standard NTSC, the write clock generator 7 generates 12.588 based on the signal from the controller 10.
A clock of MHz is generated, and the A / D conversion unit 2 samples the video signal with this clock, converts it into a digital signal, and inputs it to the memory unit 3. In response to the write control signal from the memory controller 6, the memory unit 3 synchronizes the signal from the A / D conversion unit 2 with the clock from the write clock generation unit 7 and records one horizontal scanning period (1H) at a time. Then, by the read control signal from the memory controller 6,
Data is read out in synchronization with the 28.636 MHz clock from the read clock generator 8 and input to the image processor 4. On the other hand, the on-screen signal generation unit 9 generates an on-screen character or the like in synchronization with the clock from the read clock generation unit 8, inputs this signal to the image processing unit 4, and outputs the signal to the required position of the signal from the memory unit 3. To synthesize. Image processing unit 4
Signal is sent to the display unit 5 and displayed on the screen.

The input video signal is a standard NTSC signal having a horizontal frequency of 15.734 KHz, a VGA mode computer signal having a horizontal frequency of 31.469 KHz, or a signal having a horizontal frequency of 31.5 KHz down-converted from the MUSE signal and having an aspect ratio of 9: 9. When displaying non-interlaced on 16 wide screens, standard NTSC signal, VGA signal, and MUS
The E down-converted signal, as shown in FIG.
Horizontal frequencies are 15.734KHz, 31.469KHz and 31.5KH respectively
At z, the sample frequencies are 12.588MHz and 25.175MH, respectively.
z, 35.154MHz, and the number of samples for 1H is 80
0, 800, 1116, effective pixels are about 664, 640,
Since it is about 892 and the horizontal frequency on the read side is about 31.5KHz, the read clock is set to 28.6K as shown in Fig. 2B.
If set to 36MHz, the number of dots for 1H will be 910, and for standard NTSC signals and VGA signals, the number of lights will be 800.
Since the lead is 910, the video signal will not be lost. Also, in the case of the MUSE down-converted signal, since the write is 1116 and the read is 910, part of the video signal will be lost as it is, but the effective range of the image is about 80%, so the number of effective pixels is It is about 892, and the timing of reading by the memory controller 6 is set appropriately, and the video information is not lost by cutting off the part before and after the effective pixel and part of the blanking period.
Thus, only one 28.636 MHz read clock is required to support the above three types of video signal sources. Also,
The on-screen signal generator 9 is replaced by the read clock generator 8
By synchronizing the generated on-screen signal with any of the above video signals, the size of the displayed characters or the like is always the same by synchronizing with the above clock.

[0009]

As described above, according to the digital signal processing circuit of the present invention, the clock on the input side has the frequency corresponding to each video signal source.
The single clock for the digital signal processing system facilitates circuit design and at the same time reduces cost.
Since there is only one type of clock, the display size does not change depending on the signal source when displaying on-screen characters and the like.

[Brief description of drawings]

FIG. 1 is a block diagram of essential parts of an embodiment of a digital signal processing circuit according to the present invention.

FIG. 2 is a diagram for explaining the operation of the digital signal processing circuit according to the present invention, in which (a) is the number of samples of the input signal,
(B) shows the number of pixels to be processed.

[Explanation of symbols]

 2 A / D conversion section 3 Memory section 4 Image processing section 5 Display section 6 Memory controller 7 Write clock generation section 8 Read clock generation section 9 On-screen signal generation section 10 Control section

Claims (8)

[Claims] 1. A first clock generation unit that generates a clock corresponding to a video signal source, and a second clock generation unit that generates a clock necessary for processing effective pixels of the video signal.
An A / D conversion unit for converting a video signal into a digital signal using the clock from the first clock generation unit;
A memory unit that records data for the horizontal scanning period from the conversion unit using the clock from the first clock generation unit and reads it using the clock from the second clock generation unit; and data read from the memory unit. And a digital signal processing circuit for displaying based on data from the image processing unit. 2. The digital signal processing circuit according to claim 1, wherein the first clock generation unit is configured to generate a plurality of types of clocks corresponding to a plurality of video signal sources, respectively. 3. The digital signal processing according to claim 1 or 2, wherein the second clock generation unit generates one kind of clock capable of processing effective pixels of any of the plurality of video signals. circuit. 4. The digital signal according to claim 1, wherein the memory unit reads all effective pixels by varying the number of dots outside the effective pixel period when reading data. Processing circuit. 5. A memory controller for controlling the memory unit is provided, wherein writing of data from the A / D conversion unit to the memory unit is controlled using a clock from the first clock generation unit, and the second clock is used. The digital signal processing circuit according to claim 1, claim 2, claim 3, or claim 4, wherein reading of data from the memory section is controlled by using a clock from the generation section. 6. An on-screen signal generation unit that generates an on-screen character or the like using the clock from the second clock generation unit is provided, and the signal read from the memory unit by the image processing unit is an on-screen signal. The digital signal processing circuit according to claim 1, claim 2, claim 3, claim 4 or claim 5, wherein the signals from the generator are combined. 7. The memory unit comprises a frame memory for recording data from the A / D converter, claim 1, claim 2, claim 3, claim 4, claim 5, or claim 5. Item 6. A digital signal processing circuit according to item 6. 8. The line memory according to claim 1, wherein the memory unit is a line memory for recording data for one horizontal scanning period from the A / D conversion unit. 7. The digital signal processing circuit according to claim 5 or 6.