JPH08223600A - Recorder, reproducer and recording and reproducing device of television signal - Google Patents

Abstract

PURPOSE: To record an EDTV-2 signal in a digital VTR by setting the lower limit level of a luminance signal to the level which is lower than a pedestal level. CONSTITUTION: The composite video signal outputted from a tuner 700 is separated into a Y signal and color difference signals CB and CR in an EDTV-2 recording circuit 600 and the signals are supplied to each input terminal of a digital VTR recording circuit 800. Each slice circuit is installed in a luminance signal channel and each color difference signal channel, and low potential side clip voltage is set to -51 IRE or below which is the lower limit potential of an adaptive setup lowering signal. In the AD conversion characteristic of the luminance signal, the OIRE of a pedestal level is set to a quantization value '16' and the 100 IRE of a white peak is set to a quantization value '235' and a quantization value '0' is made to correspond to about -7 IRE Thus, the recording of the adaptive setup lowering signal in a VTR 800 is made possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for recording or reproducing a television signal, and more particularly to a device capable of providing a high quality image by separating and transmitting a high resolution component. Device for recording a recorded television signal on a recording medium, a reproducing device for reproducing the television signal from the recording medium, and a recording and reproducing device for recording and reproducing the television signal using the recording medium It relates to the device.

[0002]

2. Description of the Related Art A television capable of providing an image having a higher resolution and a wider image than a television signal of the system while maintaining the compatibility with the NTSC system which is the current standard system of television broadcasting. As a method, the second generation E
XTENDED DEFINITION TELEVI
sion (hereinafter referred to as EDTV-2) has been proposed, and its practical application is planned in the near future.

This EDTV-2 enables transmission of a video signal having a bandwidth of 0 to 6 MHz by using a format conforming to the NTSC system.
Aspect ratio 1 in a receiver equipped with
A wide image of 6: 9 can be expressed. Further, when the image is received by a normal NTSC receiver, an image having an aspect ratio of 16: 9 is displayed in the central portion (main image portion) of the screen, and a non-image portion where no image is displayed appears in the upper and lower portions thereof.

In the EDTV-2, in order to provide a wide image of high resolution as described above, in addition to a luminance signal and a chromaticity signal having the same band as the NTSC system, a horizontal resolution enhancing signal and a vertical resolution enhancing signal are provided. A signal and an identification control signal including control information and identification information related to the EDTV signal are transmitted as an auxiliary signal. The outline of the formats of these auxiliary signals will be described below.

1) Horizontal resolution enhancement signal In the EDTV-2, a progressive scanning television camera having 525 scanning lines and an output signal bandwidth of 6 MHz is used, and 480 video signals forming effective scanning lines are 4-3. After conversion into 360 video signals in the letterbox format, it is converted into interlaced scanning signals. And
The high-frequency component HH of 4.2 MHz to 6 MHz, which exceeds the band of the NTSC system luminance signal, is separated from the signal converted into the interlaced scanning, and then the HH signal is frequency-shifted to the "blank hole" by carrier suppression amplitude modulation. Signal HH '
Is multiplexed on 360 scanning lines (main image portion) in the center of the screen and transmitted as a horizontal resolution enhancement signal. As the carrier wave for this frequency shift, a carrier wave having a characteristic that 16/7 fsc is polarity-reversed line by line and frame by frame and the same phase drops in each field in the vertical-time domain is used.

[1] of FIG. 12 shows signal spectra of a luminance signal YL of 0 to 4.2 MHz, a color signal C, and a horizontal resolution reinforcing signal HH '. The signal HH 'exists in the holes of the first and third quadrants which are conjugate with the color signal in the vertical frequency (ν) -temporal frequency (f) space as shown in [2] of the figure.

2) Vertical resolution enhancement signal The vertical resolution enhancement signal is composed of a VT signal and a VH 'signal. Here, the VT signal is a signal obtained by performing a high-pass filter process on the vertical frequency axis with respect to the video signal subjected to the 4-3 conversion, and then converting it into an interlaced scanning format. This signal is interlaced. Represents the vertical temporal high-pass component that is lost during conversion to scan format. This VT signal is used during image display by progressive scanning, but even in the case of image display by interlaced scanning, the use of the VT signal for the diagonal component of the motion component is effective in eliminating aliasing distortion.

In the VH 'signal, the vertical high-frequency component VH extracted from the progressive scanning video signal is vertically frequency-shifted to the vertical low frequency by a line inversion operation, further 4-3 converted, and then converted to interlaced scanning. It is obtained by The VH 'signal represents a vertical luminance high frequency component lost in the 4-3 conversion, and is transmitted only in the still image.

These VT signals and VH 'signals are horizontally band-limited and then compressed and rearranged to 1/3 in the horizontal direction. The VH' signals are inverted in polarity for each line and frame, and then for the VT signal. Is added. The added output is modulated by using the Q-axis color subcarrier, and then multiplexed and transmitted to the non-image part composed of 60 lines above and below the main image part. The spectrum in the vertical frequency (ν) -temporal frequency (f) space of the VT signal and the VH ′ signal (where the horizontal frequency μ = ± fsc cross section) is
It is represented as in FIG.

On the broadcast station side, the above VT
When the / VH 'signal is multiplexed and transmitted to the non-image part, ED
Ordinary receiver without TV-2 decoder EDT
When the V-2 signal is received, the adaptive setup lowering process as described below is performed so that the multiplex signal of the non-picture part is not noticeable on the screen. That is, V on the transmitting side
When the T / VH 'signal is multiplexed on the 0IRE pedestal and transmitted, the multiplexed pedestal level is lowered according to the amplitude level of the VT / VH' signal.

Referring to FIG. 14, in this figure, A shows the modulation signal of the VT / VH 'signal before multiplexing, and B shows the setup lowering signal with which this modulation signal is multiplexed. In this way, by multiplexing to a signal whose setup is reduced according to the amplitude level of the modulation signal, the peak value of the multiplexed output rarely exceeds 0IRE, and it is observed as noise in the non-image part of the receiver. Is almost gone.

FIG. 15 shows an example in which a specific circuit for performing the adaptive type setup reduction is constituted by a digital circuit. In this circuit, the modulated VT / VH ′ signal (A) is supplied to the BPF 920 to extract the component of the color sub-carrier band, and then the absolute value conversion circuit ABS 921 extracts the amplitude, and then the nonlinear circuit 922. Figure 1
As shown in 6, coring is performed at the level 1 IRE and clipping is performed at the level 5 IRE. That is, the negative peak value of the adaptive setup lowering signal is -5I.
It never falls below RE. Next, the LPF 923 extracts the low-frequency component, and further polar-inverts this to obtain an adaptive setup reduction signal as shown in B of FIG. By multiplexing this signal with the original modulated signal A, a desired multiplex output can be obtained.

3) Discrimination Control Signal The discrimination control signal has the format shown in FIG. 17 and is inserted in the 22nd and 285th lines. By this identification control signal, the aspect ratio, the presence / absence of various reinforcement signals, the phase-based control information of the reinforcement signal, and the like are transmitted as 27-bit information B1 to B27.
Regarding the contents of each bit, the bits B1 and B2 are set to "1" and "0", respectively, to define the reference timing. Bit B3 is set to "1" in the case of letterbox. Bit B6 is the field number, bit B7 is H
It represents the phase of the H modulated carrier and the polarity of the VH vertical-time modulated carrier, respectively. Further, bit B8 indicates the presence or absence of the VT signal, bit B9 indicates the presence or absence of the VH signal, and bit B10.
Represents the presence or absence of an HH signal, and these bits are defined as "present" when "1" and "absent" when "0".

Bits B1 to B5 and bit B24
Is composed of an NRZ waveform. Also, bits B6 to B23
Information is represented by carrier suppression amplitude modulation of the color subcarrier,
In this case, the phases of the color subcarriers are set to 0 and π corresponding to "1" and "0" of each bit, respectively. Further, the bits B25 to B27 are a sine wave (2.04 MHz) for confirmation for distinguishing the existing video signal and the identification control signal.

FIG. 18 shows details of a transmission signal for one frame in the EDTV-2. In this figure, one line is composed of 910 samples at a sampling frequency of 4 fsc, and a halftone dot portion indicates a portion where no signal exists. The 180th line from the 53rd line to the 232nd line and the 180th line from the 316th line to the 495th line configures a main image section in which the above-mentioned HH ′ signal is multiplexed, and the 23rd line above the main image section. 30th lines of the 52nd line and the 286th line to the 315th line are the upper non-image part, and the 233rd line to the 262th line and the 496th line to the 525th line located below the main image part. The 30 lines respectively constitute lower non-image parts, and the above-mentioned VT signal and VH ′ signal are multiplexed.

[0016]

By the way, at present, NT
As a recording / reproducing apparatus for recording / reproducing SC television signals efficiently and in high quality, image signals are 4: 1:
An image compression recording system digital VTR in which data is compressed and recorded by processing such as DCT conversion and variable length coding after sampling in one format and digitizing
(Hereinafter, this type of digital VTR will be simply referred to as "digital VTR") has been proposed and will be put into practical use in the near future.

In this digital VTR, the luminance signal and the color difference signal are recorded in the component format. In this case, the effective image area recorded per frame is designed to facilitate the DCT conversion process at the time of recording. Is determined uniquely, and specifically, a total of 480 lines, which are 240 lines each of the 23rd line to the 262th line and the 285th line to the 524th line, are set in the effective image area.

By the way, A when the luminance signal and the color difference signal are AD-converted and recorded in the above-mentioned digital VTR
The D conversion characteristic is set as shown in FIG. That is, the pedestal level (0IRE) of the luminance signal is the quantized value "16", the white peak (100IRE) is the quantized value "235", and the center level of the color difference signals is the quantized value "12".
8 ”, the maximum peak in the positive direction is the quantized value“ 240 ”,
The maximum peak in the negative direction is converted to the quantized value “16”.

In this case, in particular, the AD of the luminance signal
In the conversion, since AD conversion of a signal portion below the pedestal level is usually unnecessary, the AD conversion is performed only on the signal portion above the pedestal level, that is, above 0 IRE, and the signal conversion below the pedestal level is performed. For the signal portion, all AD conversion outputs are set to have a quantized value of "16".

Therefore, in such a digital VTR, it is impossible to accurately record / reproduce the adaptive setup degradation signal. That is, the noise level appearing in the non-image part is different between when the broadcast EDTV-2 signal is directly displayed on the receiver and when the EDTV-2 signal recorded by the digital VTR is reproduced and displayed on the receiver. It will be very different.

A digital V compatible with EDTV-2
Even if a circuit for generating an adaptive setup lowering signal is specially provided on the reproducing side as the TR, the tape on which the EDTV-2 signal is recorded by the digital VTR is reproduced by the digital VTR which is not compatible with the EDTV-2. In the case of doing, VT /
It is fully conceivable that the VH 'signal will appear as strong noise. An object of the present invention is to solve the above problems and solve the problem of ED.
It is to be able to record a TV-2 signal in a digital VTR.

[0022]

According to a first aspect of the present invention, there is provided a television having a luminance signal, a chrominance signal, and a vertical resolution enhancement signal multiplexed with a signal subjected to adaptive setup reduction processing of a predetermined line. In a recording device for recording a television signal on a recording medium, a separating means for separating a luminance signal, a color signal, a vertical resolution reinforcing signal, and an adaptive setup lowering signal from the television signal, and a luminance separated by the separating means. A luminance signal AD conversion means for AD-converting a signal, and a luminance signal processing circuit for converting the output of the luminance signal AD conversion means into a signal form for recording and recording it on a recording medium; A color signal AD conversion means for AD-converting the generated color signal, and converting the output of the color signal AD conversion means into a signal form for recording. A color signal processing circuit for recording on a medium, a vertical resolution reinforcing signal recording means for recording the vertical resolution reinforcing signal separated by the separating means on a recording medium via the color signal processing circuit, and a separation by the separating means. An adaptive setup lowering signal recording means for recording the adaptive setup lowering signal on the recording medium via the luminance signal processing circuit, and the luminance signal processing circuit further includes AD in the luminance signal AD converting means.
A setting means for setting the level range of the converted luminance signal is provided, and the setting means sets the lower limit level of the level range lower than the pedestal level of the luminance signal.

According to a second aspect of the present invention, a television signal having a luminance signal, a chrominance signal, and a vertical resolution enhancement signal multiplexed with a signal subjected to adaptive setup reduction processing of a predetermined line is transmitted from a recording medium. In a television signal reproducing apparatus for reproducing a television signal, reproducing means for scanning a recording medium, and luminance signal reproducing means for reproducing a luminance signal in which an adaptive setup reduction signal is multiplexed from an output signal of the reproducing means, A color signal reproducing means for reproducing the color signal from the output signal of the reproducing means, a vertical resolution enhancing signal reproducing means for reproducing a vertical resolution enhancing signal from the output signal of the reproducing means, and an output of the vertical resolution enhancing signal reproducing means. And a multiplexing means for multiplexing the output of the color signal reproducing means,
A first output signal terminal for outputting the output signal of the multiplexing means to the outside and a second output signal terminal for outputting the output signal of the luminance signal reproducing means to the outside are provided.

According to a third aspect of the present invention, a television signal having a luminance signal, a chrominance signal, and a vertical resolution reinforcement signal multiplexed with a signal subjected to adaptive setup reduction processing of a predetermined line is recorded on a recording medium. In a recording / reproducing apparatus for recording / reproducing by using, a separating means for separating a luminance signal, a color signal, a vertical resolution enhancing signal, and an adaptive setup lowering signal from the television signal, and a luminance signal separated by the separating means. And a luminance signal processing circuit for converting the output of the luminance signal AD converting means into a signal form for recording and recording the recording medium on a recording medium; A color signal AD conversion means for AD converting the color signal
And a color signal processing circuit for converting the output of the color signal AD conversion means into a signal form for recording and recording the converted signal on a recording medium,
Vertical resolution enhancement signal recording means for recording the vertical resolution enhancement signal separated by the separation means on a recording medium via the color signal processing circuit, and the adaptive setup decrease signal separated by the separation means for the luminance signal An adaptive setup degradation signal recording means for recording on a recording medium via a processing circuit; a reproducing means for scanning the recording medium;
Luminance signal reproducing means for reproducing a luminance signal in which an adaptive setup reduction signal is multiplexed from an output signal of the reproducing means,
A color signal reproducing means for reproducing the color signal from the output signal of the reproducing means, a vertical resolution enhancing signal reproducing means for reproducing a vertical resolution enhancing signal from the output signal of the reproducing means, and an output of the vertical resolution enhancing signal reproducing means. And a first output signal terminal for outputting the output signal of the multiplexing means to the outside, and an output signal of the luminance signal reproducing means to the outside. A second output signal terminal for controlling the brightness signal processing circuit, and the brightness signal processing circuit further includes setting means for setting the level range of the brightness signal AD-converted by the brightness signal AD conversion means. Sets the lower limit level of the level range lower than the pedestal level of the luminance signal.

[0025]

The adaptive setup lowering signal transmitted to the non-picture part of the EDTV-2 signal is faithfully recorded and reproduced. The luminance signal in which the adaptive setup reduction signal is multiplexed and the chrominance signal in which the vertical resolution enhancement signal is multiplexed are separately output from the dedicated output terminals.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a recording apparatus configured to record an EDTV-2 signal according to the present invention will be described, and then a reproducing apparatus for reproducing the EDTV-2 signal recorded by the recording apparatus. explain.

[1] Recording Device FIG. 20 shows the overall configuration of an embodiment of the recording device.
This embodiment shows a tuner 70 as shown.
0, an EDTV-2 recording circuit 600, and a recording unit 800 of the digital VTR described above. The composite video signal output from the tuner is separated into a Y signal and color difference signals CB and CR in the EDTV-2 recording circuit. And is supplied to each input terminal of the digital VTR recording section. Also, the audio signal is directly supplied from the tuner to the audio signal input terminal of the digital VTR recording section.
When the input signal from the tuner is an EDTV-2 signal instead of an NTSC signal, switching information, identification control signal data, and an HH decode flag are added from the EDTV-2 recording circuit in addition to the above signals. It is input to a predetermined input terminal of the digital VTR recording section.

The EDTV-2 recording circuit and the digital VTR recording section will be described in detail below. 1. EDTV-2 Recording Circuit FIG. 21 shows an example of a specific configuration of the EDTV-2 recording circuit. In this figure, the input signal from the tuner is supplied to the sync separation circuit 505, and the sync signal separated here is input to the line decoder switch circuit 506 to generate the gate pulse corresponding to the 22nd line period and the 285th line period. Generate G. This gate pulse is ED
The signals are input to the TV-2ID decoder 504, a gate circuit (not shown) provided in the input section is turned on, and the signals from the tuner on these lines are decoded.

The input signal from the tuner is EDTV-2.
If the signal is a signal, the identification control signal of the EDTV-2 is fetched into the decoder by the above-mentioned gate operation, and this signal is decoded, so that the determination signal D which is recognized as the EDTV-2 signal is obtained. Decoder to line decoder switch circuit 506 and channel divider 5
10 are supplied. Then, the switch circuit outputs the switching signal to the switch 597 only when the EDTV-2 signal is received based on the discrimination signal D, and also generates the switching information representing the period of the 285th line to generate the digital VTR recording from the terminal 518. Input to the section (the role of this switching information will be described later). Further, the channel division device is turned on only when receiving the EDTV-2 signal based on the discrimination signal D, and executes the channel division operation.

The above switching signal connects the movable terminal of the switch 597 to the input terminal side of the VT / VH 'demodulator 502 only during the non-image part period, and inputs to the three-dimensional Y / C separation circuit 503 during the other period. Switch 59 to connect to the terminal side
Control 7 On the other hand, EDTV-2ID decoder 504
Data of bit B16 indicating the presence or absence of the HH signal in the identification control signal decoded in (HH decode flag)
Is output from the terminal 517 to the digital VTR recording unit and is also input to a control circuit (not shown) in the HH ′ decoder 507, and the control circuit sets this flag to “1”.
Only when (HH signal is present), the decoding operation of the decoder 507 is executed.

As a result, the three-dimensional Y / C separation circuit 503
The HH 'signal in the EDTV-2 signal separated in (1) is synchronously detected by the decoder 507 and demodulated into an HH signal, and then combined with the Y signal by the adder circuit 509 to have a band of 6
The wideband Y signal extended to MHz is output from the terminal 513 to the digital VTR recording unit and recorded. In the present embodiment, the identification control signal data obtained by decoding the identification control signal in the decoder 504 is input to the digital VTR from the terminal 516 and recorded.

However, in this case, since the luminance signal recorded in the digital VTR is a wideband luminance signal to which the HH signal obtained by converting the HH 'signal is added as described above, the digital VTR is output from the output terminal 516. The value of the HH decode flag in the identification control signal data output to the recording section is always rewritten to "0" (the reason is that the EDTV-2 signal recorded in the digital VTR of this embodiment is reproduced. When input to a television receiver with a built-in EDTV-2 decoder, since the HH 'signal does not already exist in the chromaticity signal band, the HH' signal is HH 'in this receiver.
Because the operation to convert to a signal is unnecessary).

FIG. 22 shows an example of a concrete circuit of the VT / VH 'demodulation device 502. In this figure, the input non-image part signal is VT / V modulated by the QPF color subcarrier by the BPF 561 and the LPF 563.
The signal H'is separated into the signal representing the lower adaptive setup degradation. The former signal is returned to the baseband VT / VH ′ signal (however, these signals are time-axis compressed to 1/3) in the demodulator 562,
It is divided into two channels in the channel dividing device 510, and further supplied from output terminals 514 and 515 through addition circuits 511 and 512 to a color difference signal input terminal of the digital VTR recording section.

That is, in this embodiment, demodulated VT / VH '.
The signal is recorded in the color signal channel of the digital VTR. The reason why the channel division is performed by the device 510 is that the baseband VT / VH ′ signal is 4 MH.
While the color signal recording channel in the digital VTR having the sampling format of 4: 1: 1 has a recordable band of about 2 MHz, it has a band of about z, and thus the VT / VH ′ signal is divided into channels. This is to reduce the band by half.

A specific circuit of the device 510 is shown in FIG.
Can be configured as follows. In this figure, the AD-converted VT / VH ′ signal is divided into an odd-numbered sample and an even-numbered sample by the sample distribution circuit 551 to halve the sample rate, and thereby DA
The band of each output of the conversion circuits 552 and 553 is set to 1/2 of the band of the original input signal. Although not shown in this figure, as described above, the determination signal D is sent from the EDTV-2ID decoder 504 to the circuits 550 to 553.
Is supplied to the device 5 only when receiving the EDTV-2 signal.
10 is configured to operate, and prevents noise or the like from being mixed into the color signal channel from the device 510 when the NTSC signal is received.

The adaptive setup reduction signal extracted from the LPF 563 of FIG. 2 is added to the adder circuit 5 of FIG.
09 through the output terminal 513 to the digital VTR recording section, and is recorded in the luminance signal channel.

The VT / VH 'signal is converted to a digital VT
As a recording channel for recording in R, a method of recording this signal in a luminance signal channel of a digital VTR can be considered, but when such a method is adopted,
The following problems occur. That is, the VT / VH 'signal is ±
Since it has an amplitude of about 15 IRE, for example, it is necessary to record after multiplexing the VT / VH 'signal with the signal that has been set up for about 15 IRE with respect to the pedestal level. The recorded tape to a normal digital VT that does not support EDTV-2.
When reproduced at R, the above-mentioned multiplexed signal appears in the non-image portion as it is set up, and this is observed as strong noise.

On the other hand, in this embodiment, VT / VH '.
Since the signal is recorded in the chrominance signal channel, the adaptive setup degradation signal can be recorded using the luminance signal channel, and the digital V of the present embodiment can be recorded.
EDTV-2 signal reproduced from TR is converted to EDTV-2
Even if the signal is input to a television receiver that is not equipped with a decoder, the VT / VH 'signal in the non-image area does not stand out on the screen.
Of course, the tape recorded in this embodiment is used as an EDTV.
-When played on a non-compliant normal digital VTR,
The above problem does not occur when a tape is reproduced by using the method of recording the VT / VH 'signal on the luminance signal channel.

Next, the input signal from the tuner is NTS.
The operation in the case of the C signal will be described. In this case, the discrimination signal D is not generated in the EDTV-2ID decoder, and the output of the identification control signal data is also prohibited. Also, the value of the HH decode flag is forcibly set to "0". By these operations, the operation of the HH 'decoder and the channel dividing device is stopped, and the generation of the switching information and the switching signal in the line decoder switch circuit 506 is stopped.

When the supply of the switching signal to the switch 597 is stopped, the movable terminal of the switch becomes 3
It is fixed to the input terminal side of the dimension Y / C separation circuit. By these operations, after all, only the Y signal separated by the three-dimensional YC separation circuit and the color difference signal demodulated by the color demodulation device 508 are digital VT as video data to be recorded.
It is output to the R recording unit, and the HH decode flag having the value “0” is output from the terminal 517 to the digital VTR recording unit.

2. Digital VTR Recording Unit Next, the digital VTR recording unit 800 will be sequentially described according to the following items. 2-1. Digital VTR recording format (1) ITI area (2) AUDIO area (3) VIDEO area (4) SUBCODE area (5) ID structure (6) MIC (7) Pack structure and type (8) Accompanying information recording Area structure (9) Application ID system 2-2. Circuit configuration of digital VTR recorder

FIG. 24 shows the recording format on the tape in the digital VTR recording section of this embodiment. In this figure, margins are provided at both ends of the track.
Inside the recording start end side, an ITI area for surely performing post-recording and an AUD for recording audio signals are provided.
An IO area, a VIDEO area for recording an image signal, and a SUBCODE area for recording secondary data are provided. An inter block gap (IBG) is provided between the areas to secure the areas.

Next, the details of the signals recorded in the above areas will be described. (1) ITI Area As shown in the enlarged portion of FIG. 24, the ITI area has a 1400-bit preamble and 1830-bit SSA (Start-Sync Block Area).
a), 90-bit TIA (Track Information)
(Area) and a 280-bit postamble.

Here, the preamble has a function such as a run-in of the PLL at the time of reproduction, and the postamble has a role of earning a margin. And SSA and TIA
The block data is composed of 30-bit block data, and the first 10 bits of each block data have a predetermined SY.
The NC pattern (ITI-SYNC) is recorded.

In the 20-bit portion following this SYNC pattern, the SYNC block number (0 to 60) is mainly recorded in SSA, and the 3-bit APT information (APT2 to APO) is mainly recorded in TIA. The SP / LP flag for identifying the recording mode and the PF flag indicating the reference frame of the servo system are recorded. Note that A
PT is ID data that defines the data structure on the track, and takes the value "000" in the digital VTR of this embodiment.

As can be seen from the above description, since a large number of sync blocks having a short code length are recorded at fixed positions on the magnetic tape in the ITI area, the 61st SYNC pattern of SSA, for example, is reproduced from the reproduced data. By using the detected position as a reference for defining the post-recording position on the track, the position to be rewritten during post-recording can be defined with high accuracy, and good post-recording can be performed. The digital VTR of this embodiment is designed so that it can be easily applied to various other digital signal recording / reproducing apparatuses as described later, but in any digital signal recording / reproducing apparatus, a specific area can be used. Since it is necessary to rewrite the data, the ITI area on the track entrance side is always provided.

(2) AUDIO area The audio area has a preamble and a postamble before and after the audio area as shown in the enlarged portion of FIG. 24. The preamble is a run-up for pulling in the PLL.
And a pre-SYNC for pre-detection of the audio SYNC block. Also, the postamble is a post S for confirming the end of the audio area.
It is composed of YNC and a guard area for protecting the audio area during video data post-recording.

Here, the pre-SYNC and the post-SYNC are
25, each SYNC block is configured as shown in (1) and (2) of FIG. 25. The pre-SYNC is composed of two SYNC blocks, and the post SYNC is composed of one SYNC block. Then, the SP / LP identification byte is recorded at the 6th byte of the pre-SYNC. This is FF
When h represents SP and 00h represents LP, and when the SP / LP flag recorded in the above-mentioned ITI area is unreadable, the value of the SP / LP identification byte of this pre-SYNC is adopted.

The audio data recorded in the area sandwiched between the amble areas as described above is generated as follows. First, the audio signal for one track to be recorded is subjected to AD conversion and shuffling, then subjected to framing, and further parity is added. FIG. 26 shows a format in which parity is added by performing this framing.
(1) of. In this figure, 72 bytes of audio data is added with 5 bytes of audio accompanying data (this is called AAUX data) to form 1 block of 77 bytes of data, which is vertically stacked for 9 blocks for framing. Then, an 8-bit horizontal parity C1 and a vertical parity C2 corresponding to five blocks are added.

The data to which these parities have been added is read in block units, and 3 bytes are added to the head side of each block.
A byte ID is added, and further, a 2-byte SYNC signal is inserted in the recording modulation circuit.
Is shaped into a signal of 1 SYNC block having a data length of 90 bytes as shown in FIG. Then, this signal is recorded on the tape.

(3) VIDEO area The video area has the same preamble and postamble as the audio area as shown in the enlarged portion of FIG. However, it is different from the audio area in that the guard area is formed longer. The video data sandwiched between these amble areas is generated as follows.

First, the Y signal is AD-converted at a sampling frequency of 13.5 MHz and the color difference signal is ¼ its frequency, and the data of the effective scanning area for one field is extracted from the AD-converted output. To do. The extracted data for this one field is the AD conversion output (DY) of the Y signal.
720 samples horizontally, 240 vertically
It is composed of lines, and the AD conversion output (DR) of the RY signal and the AD conversion output (DB) of the BY signal are 180 samples in the horizontal direction and 24 in the vertical direction, respectively.
It consists of 0 lines. And these extracted data are
It is divided into blocks of 8 samples in the horizontal direction and 4 lines in the vertical direction. This blocking process is performed for one frame of DY
27 is shown in FIG.

Next, the data of 4 lines of the blocks at the corresponding positions of the field 1 and the field 2 blocked in this way are interleaved with each other, and (1) in FIG.
28, a block of 8 samples in the horizontal direction and 8 lines in the vertical direction is formed (for example, by interposing blocks 1-1 ′ and 1-1 ″ in FIG. 27, (1) in FIG. 28).
1 to generate blocks 1-1). The same operation is performed for the color difference signals DR and DB, and (2) in FIG.
Blocking processing for one frame of data is executed as shown in FIG. However, in the case of the color difference signal, the blocks at the right end portion in these fields have only 4 samples in the horizontal direction, and therefore, two blocks vertically adjacent to each other are combined into one block. By the above blocking process, a total of 8100 blocks of 8 samples × 8 lines are formed in DY, DR, and DB per frame. A block composed of 8 samples in the horizontal direction and 8 lines in the vertical direction is called a DCT block.

Next, these blocked data are shuffled in accordance with a predetermined shuffling pattern, then DCT-converted in DCT block units, and subsequently quantized and variable-length coded. Here, the quantization step is set for every 30 DCT blocks, and the value of this quantization step is set so that the total amount of output data obtained by quantizing and variable-length-coding 30 DCT blocks is equal to or less than a predetermined value. It That is, the video data is transferred to the DCT block 30.
Fixed length for each piece. The data for 30 DCT blocks is called a buffering unit.

The data fixed in length as described above is subjected to framing together with video ancillary data (this is called VAUX data) for each data of one track, and then an error correction code is added. FIG. 29 shows a format in which this framing is applied and an error correction code is added.

In this figure, BUF0 to BUF26 each represent one buffering unit. One buffering unit is (1) in FIG.
As shown in (1), it has a structure in which it is vertically divided into five blocks, and each block has a data amount of 77 bytes.
An area Q for storing parameters relating to quantization is provided in the first byte of each block.

Video data is stored in an area of 76 bytes following the quantized data. Then, as shown in FIG. 29, VAUX data α and β corresponding to two blocks in the above buffering unit are arranged above the buffering units arranged in the vertical direction in 27 units. At the same time, VAUX data γ corresponding to one block is arranged in the lower part, and an 8-byte horizontal parity C1 and a vertical parity C2 corresponding to 11 blocks are added to the framed data. To be done.

The signal to which the parity is added in this way is read in units of blocks, a 3-byte ID signal is added to the head side of each block, and a 2-byte SYNC signal is further inserted in the recording modulation circuit. It This allows
For the video data block, a signal of 1 SYNC block having a data amount of 90 bytes as shown in (2) of FIG. 30 is formed, and for the VAUX data block, 1 SYNC block as shown in (3) of FIG. The signal of the block is formed. The signal for each 1SYNC block is sequentially recorded on the tape.

In the framing format described above, since 27 buffering units representing one track of video data have 810 DCT blocks of data, one frame of data (8100 DCT blocks) is stored. The recording will be divided into 10 tracks.

(4) SUBCODE Area The SUBCODE area is an area mainly provided for recording information for high speed search, and its enlarged view is shown in FIG.
It is shown in FIG. As shown in this figure, the SUBCODE area includes 12 SYNC blocks having a data length of 12 bytes, and a preamble and a postamble are provided before and after the SYNC block. However, unlike the audio area and the video area, pre-SYNC and post-SYNC are not provided. And, in each of the 12 SYNC blocks,
A data section for recording 5-byte accompanying data (AUX data) is provided. Also, as the parity for protecting the 5-byte accompanying data, only the 2-byte horizontal parity C1 is used, and the vertical parity is not used.

The AUDIO area described above,
Each SYNC block forming the VIDEO area and the SUBCODE area is converted into 24/25 during recording modulation (converting data of every 24 bits of the recording signal into 25 bits so that the recording code has a pilot frequency for tracking control). Recording modulation method that gives the component)
Therefore, the recording data amount of each area becomes the number of bits as shown in FIG.

(5) Structure of ID part As is clear from the structure of each SYNC block shown in FIGS. 25, 26, 30 and 31, as described above,
UDIO area, VIDEO area, and SUBOCO
The SYNC block recorded in the DE area has ID0, ID1 and IDP (ID
3-byte I consisting of 0, parity that protects ID1)
The structure is common in that the D section is provided. In the audio area and the video area, the data structure of the ID0 and ID1 in the ID portion is determined as shown in FIG.

That is, the ID1 stores the in-track SYNC number from the audio area pre-SYNC to the video area post-SYNC in binary. And I
The track number in one frame is stored in the lower 4 bits of D0. The upper 4 bits of ID0 have AAU
SYNC of X + audio data and video data
In the block, 4 as shown in (1) of this figure
The bit sequence number is stored.

On the other hand, S of the pre-SYNC block, post-SYNC block and parity C2 in the audio area
In the YNC block, 3-bit ID data AP1 defining the data structure of the audio area is stored,
Also, the pre-SYNC block and post S in the video area
In the YNC block and the SYNC block of parity C2, 3-bit ID data AP2 defining the data structure of the video area is stored (see (2) in this figure). The values of AP1 and AP2 are "000" in the digital VTR of this embodiment.

The sequence number is "000".
Twelve numbers from "0" to "1011" are recorded for each frame. By looking at this sequence number, it is possible to judge whether the data obtained during variable speed reproduction are within the same frame. On the other hand, SUBCOD
The structure of the ID part of the SYNC block in the E area is defined as shown in FIG.

This drawing shows the structure of each ID part of SYNC block numbers 0 to 11 for one track in the SUBCODE area, and the FR flag is provided in the most significant bit of ID0. This flag indicates whether or not it is the first 5 tracks of the frame, and takes a value of "0" in the first 5 tracks and "1" in the latter 5 tracks. The next 3 bits have S in the SYNC block whose SYNC block numbers are "0" and "6".
The ID data AP3 defining the data structure of the UBCODE area is recorded, and the SYNC block number “1” is recorded.
The ID data APT defining the data structure on the track is recorded in the SYNC block of "1", and the TAG code is recorded in the other SYNC block. The value of AP3 is the digital V of this embodiment.
In TR, "000" is taken.

Further, the TAG code is composed of three types of ID signals for search, as shown in an enlarged manner in this figure.
That is, it is composed of an INDEX ID for a conventional INDEX search, a SKIP ID for cutting unnecessary scenes such as commercials, and a PP ID (Photo / Picture ID) for a still image search. Also, the absolute number of the track (the continuous track number from the beginning of the tape) is recorded using the lower 4 bits of ID0 and the upper 4 bits of ID1. However,
As shown in this figure, one absolute track number is recorded by using a total of 24 bits for three SYNC blocks. The SYNC block number of the SUBCODE area is recorded in the lower 4 bits of ID1.

(6) MIC In the digital VTR of the present embodiment, the accompanying data is recorded in each area defined on the tape as described above, but the tape is stored outside this area. The circuit board provided with the memory IC is mounted on the cassette,
The accompanying data is also recorded in this memory IC. When this cassette is attached to the digital VTR, the accompanying data written in this memory IC is read out to assist the operation / operation of the digital VTR. This memory IC is referred to as MIC in the present application.
(Memory In Cassette), and its data structure will be described in detail later.

(7) Structure and type of pack As described above, in the digital VTR of this embodiment, the audio area AAUX area and the video area VA area on the tape are used as areas for recording accompanying data.
The AUX data recording area of the UX area and the SUBCODE area is used, and the recording area of the MIC mounted on the tape cassette is used in addition to this. Each of these areas is configured in units of packs having a fixed length of 5 bytes.

Next, the structure and types of these packs will be described. The pack has a basic structure of 5 bytes shown in FIG. Of these 5 bytes, the first byte (PC0) is used as item data (also called a pack header) indicating the content of the data. Then, the format of the subsequent 4 bytes (PC1 to 4) is determined corresponding to this item data, and arbitrary data is provided according to this format.

This item data is divided into upper and lower 4 bits, and the upper 4 bits are called large items and the lower 4 bits are called small items. The large item of the upper 4 bits is, for example, data indicating the use of the subsequent data, and the large item causes the pack to have a control "0000" and a title "0" as shown in the table of [1] of FIG.
"001", chapter "0010", part "001"
1 ”, program“ 0100 ”, voice auxiliary data (AA
UX) "0101", image auxiliary data (VAUX) "0"
110 ", camera" 0111 ", line" 1000 ",
It is developed into 10 types of groups of soft mode “1111”.

In this way, each group of packs expanded by the large item is expanded into 16 packs by each smaller item (for example, the concrete content of the subsequent data is represented), and finally, Up to 256 types of packs can be defined using these items. The large items “1001” to “1110” in the table of [1] of FIG. 35 represent undefined portions left for addition. Therefore, by defining new item data (header) using a code of item data that has not been defined yet, it is possible to arbitrarily record new data in the future. Further, since the content of the data stored in the pack can be grasped by reading the header, the position on the tape for recording the pack can be set arbitrarily.

Next, a specific example of the pack will be described with reference to FIGS. 35 [2] and [3] and FIGS. 36 to 38. 35 [2] and [3], and FIG. 36 [1]-
As can be seen from the value of the item data of each pack shown in [5], VAUX in the table of [1] in FIG.
Belongs to the group of and is used for recording incidental data regarding images.

The recorded contents of these packs will be described below. VAUX SOURCE shown in [2] of FIG.
The E-pack indicates the channel number of the recording signal source, a flag (B / W) indicating whether the recording signal is a monochrome signal, a code (CFL) indicating color framing, and whether the CFL is valid. Flag (EN), a code indicating whether the recording signal source is a camera / line / cable / tuner / soft tape (SOURCE COD)
E), data relating to the television signal system (50 /
60, and STYPE), data relating to identification of UV broadcast / satellite broadcast, etc. (TUNER CATEGORY) is recorded.

VAUX SOU shown in [3] of FIG.
In the RCE CONTROL pack, SCMS data (the upper bit indicates whether or not there is copyright and the lower bit indicates whether it is the original tape), ISR data (whether the recording signal performed immediately before is from an analog signal source or not) Etc.), CMP data (representing the number of compressions), SS data (representing information such as whether or not the recording signal is scrambled), and a flag (REC indicating whether or not it is a recording start frame. ST), an HH flag indicating whether or not the signal to be recorded has a high frequency HH signal component (when it is “0”, there is an HH signal component,
Recording mode data (REC MODE) such as original recording / post-recording recording / insert recording is recorded when “1” indicates that there is no HH signal component), and further data regarding the aspect ratio (BCSYS and DIS).
P), a flag regarding whether to output only the signal of one of the even-odd fields by repeating twice (F)
F), a flag regarding whether to output the signal of the field 1 or the signal of the field 2 during the period of the field 1 (FS), and a flag regarding whether the image data of the frame is different from the image data of the previous frame (FS). FC),
A flag (IL) regarding whether or not interlacing is performed,
Flag relating to whether the recorded image is a still image (S
T), a flag (SC) indicating whether or not the recorded image is recorded in the still camera mode, and a genre of recorded content are recorded.

Further, the VAUX shown in [1] of FIG.
Data relating to the recording date is recorded in the REC DATE pack, and VAUX REC shown in [2] of the figure is displayed.
Data relating to the recording time is recorded in the TIME pack, and the BINARY GROUP shown in [3] of FIG.
The data of the time code binary group is recorded in the pack. CLOSED CA shown in [4] of FIG.
Closed caption information transmitted during a vertical blanking period of a television signal is recorded in the PTION pack.

In the VAUX TR pack of [5] in the figure, system data mainly transmitted in the vertical blanking period is stored. The type of system data recorded is DATA TYPE of the lower 4 bits of PC1.
It is defined as follows according to the value of. 0000 = Video ID data 0001 = WSS data 0010 = EDTV-2 ID in 22 line 0011 = EDTV-2 ID in 285 lin
e 1111 = No information Other = Reserved That is, in this digital VTR, the identification control signal data input from the EDTV-2 recording circuit 600 is the V
It is stored and recorded in the AUX TR pack.

In addition, CASSETTE of (1) in FIG.
ID pack and TAPE LENG of (2) in the figure
The TH pack is a pack belonging to the CONTROL group in FIG. 35, and the CASSETE ID pack has a flag ME indicating whether or not the data recorded in the MIC corresponds to the data recorded on the tape of the cassette. , Memory (MIC) type, memory size information, and tape thickness information (PC4) are recorded.

In the TAPE LENGTH pack, the total length of the magnetic tape body excluding the leader tape of the video tape is recorded as 23-bit data converted into the number of tracks. The number of tracks in this case is calculated by the track pitch (10 microns) in the SP mode. TITLE EN shown in (3) of FIG.
The absolute track number of the final recording position on the tape is recorded in the D pack. This final recording position means the position closest to the tape end in the recorded area on the tape, and is an unrecorded area after this position.

When there is a non-recorded portion (blank) on the tape, a discontinuous portion is generated in the absolute track number recorded on each track on the tape.
The flag BF in the pack is a flag indicating whether or not there is such a discontinuous portion at a position before the absolute track number recorded in this pack. Also,
The flag SL is a flag indicating whether the recording mode at this final recording position is the SP mode or the LP mode, and the flag RE indicates whether or not there is a recorded content that should not be erased on the tape. It is a flag.

The packs shown in (1) to (3) of FIG. 38 belong to the group of programs in the table of [1] of FIG. 35, as can be seen from the item, and the pack of (1) above. The PROGRAM START pack of (1) and the PROGRAM END pack of (2) record the start position and end position of each program recorded on the tape. That is, the program start point and the program end point are stored in the second to fourth bytes (PC1 to PC3) of these packs by 23-bit absolute track numbers, respectively.

The flag TEXT in the PC4 of the PROGRAM START pack is a flag indicating whether the text information about this program is recorded on the MIC (0: text information exists, 1:
No text information). However, when this pack is recorded on the tape, the TEXT flag always takes the value "1". The TT flag is a flag indicating whether the tape recording start position data recorded on the MIC corresponds to the tape recording start position data actually recorded on the tape. GENRE CATEGORY
Is a code representing the genre of the recorded content (for example, "baseball", "movie", "travel", "drama", etc.).

Further, the RP flag stored in the PROGRAM END pack is a flag regarding whether or not the recorded contents can be erased, and the PD flag indicates whether or not this program has been reproduced even once after being recorded by timer recording or the like. The TNT code is a code indicating the number of text events (events will be described later) recorded in the MIC for this program.

Further, PROGRAM R of (3) in FIG.
In the EC DATE TIME pack, the recording date, hour, minute, day of the week, etc. of the program recorded on the tape are recorded. The RM in this pack is a code indicating whether the recording mode is video, audio, or the like.

As a special example of the pack, a pack having an item code of 1 is a non-information pack (No I
nformation pack). As can be seen from the above description, in the digital VTR of the present embodiment, since the structure of the accompanying data is the pack structure common to each area as described above, the software for recording and reproducing these data is common. And processing becomes easy. Further, since the timing at the time of recording / reproducing is constant, it is not necessary to provide an extra memory such as RAM for time adjustment, and the software can be easily developed in the case of developing a new model. be able to.

By adopting a pack structure, for example, even if an error occurs during reproduction, the next pack can be easily taken out. Therefore, a large amount of data will not be destroyed due to error propagation or the like. When the text data is stored in the MIC, the pack structure is exceptionally recorded in one pack in order to save the used area of the storage area of the MIC having a small storage capacity. The structure is a variable-length pack that stores all text data.
The consumption amount of the storage area of C is saved.

(8) Structure of ancillary information recording area Next, the data area of the AAUX area, the VAUX area, the SUBCODE area where various kinds of ancillary data are recorded using a pack, and the recording of the MIC mounted on the tape cassette A specific structure of the area will be described.

AAUX Area In the AAUX area, 1SY shown in (2) of FIG.
5 bytes AA in the NC block format
One pack is constructed in the UX area. Therefore, AA
The UX area consists of 9 packs per track. In the digital VTR of the present embodiment, one frame of data is recorded on 10 tracks, so one frame of AA is recorded.
The UX area is represented as shown in FIG.

In this figure, one section represents one pack. And the numbers 50-55 entered in the section
Is a hexadecimal representation of the item codes of the packs in that section. These six types of packs are called main packs, and the area in which these main packs are recorded is called the AAUX main area. Areas other than this are called AAUX optional areas, and an arbitrary pack can be selected and recorded from a wide variety of packs.

VAUX Area For the VAUX area, VAU in one track
As shown in FIG. 29, the X area is composed of three SYNC blocks α, β and γ, and the number of packs thereof is as shown in FIG.
15 per 1 SYNC block as shown in 0,
It becomes 45 in one track. The 2-byte area immediately before the error code C1 in the 1SYNC block is used as a preliminary recording area.

Regarding the VAUX area for one frame,
FIG. 41 shows the pack structure. In this figure, the packs to which the item codes 60 to 64 and 66 in hexadecimal notation are attached are VAUX main packs constituting the VAUX main area, and are indicated by [2] and [3] in FIG. 35 and [[ 1] to [3], and [5]
The pack shown in is equivalent to this. The other pack constitutes the VAUX optional area. Since the Closed Caption signal is not recorded in the recording of the EDTV-2 signal or the NTSC signal of this embodiment, this pack is not shown in FIG.

Data Area of SUBCODE Area The data area of the SUBCODE area is, as shown in FIG. 31, each SYN of SYNC block numbers 0 to 11.
Five bytes are written in the C block, and each of them constitutes one pack. That is, 12 packs are recorded in one track, of which SYNC block numbers 3 to
The packs 5 and 9 to 11 form a main area, and the other packs form an optional area.

The data for one frame in this SUBCODE area is repeatedly recorded in the format as shown in FIG. In this figure, capital letters represent packs in the main area, and data necessary for high-speed search such as time code and recording date are recorded. The lower case alphabets represent packs in the optional area, and any pack can be selected in this area to record any data.

The main area in each of the areas described above is characterized in that a pack in which ancillary information regarding basic data items common to all tapes is stored is recorded. On the other hand, in the optional area, a soft tape maker or a user can freely write any accompanying data. Examples of such incidental information include various character information,
There are teletext signal data, various system data in the vertical blanking period, television signal data of an arbitrary line in the effective scanning period, computer graphics data, and the like.

Even if the pack is located in the main area (for example, the pack with the item code "66" in FIG. 41), if there is no data to be stored therein, the pack with the item code "66" is used. Instead of
The aforementioned No Information pack can be recorded.

Recording Area of MIC FIG. 43 shows the data structure of the recording area of the MIC. This recording area is also divided into a main area and an optional area. The first 1 byte and unused area (FFh)
All are described in a pack structure except. As described above, only the text data is recorded in a variable-length pack structure, and other than that, it is recorded in the same 5-byte fixed-length pack structure as the VAUX, AAUX, and SUBCODE areas.

At the head address 0 of the MIC main area, ID data A that defines the data structure of the MIC is written.
PM3 bit and BCID (Basic Cassette)
eID) 4 bits are recorded. Here, the value of APM is "000" in the digital VTR of this embodiment. BCID is a basic cassette ID, and
The contents are the same as the ID board for ID recognition (tape thickness, tape type, tape grade) in the C-less cassette. The ID board makes the MIC reading terminal have the same function as the recognition hole of the conventional 8 mm VTR, which eliminates the need to make a hole in the cassette half as in the conventional case.

Three packs of the above-mentioned "cassette ID" pack, "tape length" pack, and "title end" pack are recorded in order from address 1 onward. The recording area from the first address 0 to this TITLE END pack is called a main area, and in this area, data concerning these predetermined contents is recorded in any MIC of any cassette. The recording area following the main area is called an optional area and is composed of an arbitrary number of events. That is, the main area is a fixed area of 16 bytes from addresses 0 to 15, whereas the optional area is a variable area at addresses 16 and thereafter.

The optional area is literally an option, and is mainly TOC (Table of Content).
ts), tag information indicating a point on the tape (for example, a point for performing still reproduction), text data such as a title related to the program, and the like are recorded in units of events.

Here, the event generally means one data group composed of a plurality of packs, and the pack located at the head thereof is called an event header. A specific pack is determined in advance as a pack serving as the event header according to the content of each event.
For example, in the packs described in FIGS. 35 to 38, the PROGRAM START pack is defined as the event header of the program event. Then, in this case, it is prohibited to include a pack defined as an event header of an event of an external type in one event. That is, one event is composed of one event header to the appearance of the next event header.

Next, a specific example of the event recorded in the optional area of the MIC will be described with reference to FIG.
This figure shows PROGRAM START pack, PRO
GRAM END pack, PROGRAM REC D
ATE pack, VAUX SOURCE CONTROL
A representation of an example program event made up of L packs, which gives the information of one particular program recorded on the tape to be displayed by the TOC.

That is, even if the user has stopped the operation of the digital VTR and is not playing back the tape, the user issues a command to a mode processing microcomputer (described later) in the digital VTR to generate an event in these MICs. By displaying the data, it is possible to know the recording date of the desired program recorded on the tape, and whether or not the program is recorded by the broadband image signal including the HH signal. If the digital VTR is in the tape reproducing operation, a command is issued to the mode processing microcomputer to display the contents of the HH flag in the VAUX SOURCE CONTROL pack reproduced from the VAUX main area on the tape, so that the current reproduction is performed. It is also possible to know whether the program being executed is an image based on a wideband video signal including the HH signal.

(9) Application ID System The recording format of the digital VTR in this embodiment has been described above. This format is NT.
The basic design is not limited to the image compression recording type digital VTR for the SC signal, and can be easily commercialized as various other digital signal recording / reproducing devices. The ID data APT, AP1 to AP3, APM appearing in the above description of the format play a role of enabling the expansion to such various digital signal recording devices. Are collectively referred to as an application ID.

Then, next, this application ID
A supplementary explanation of the system will be given. The above-mentioned application ID is used to determine an application example of the digital VTR.
It is an ID that simply determines the data structure of the area of the recording medium, not D, and the APT and APM have the following meanings as described above. APT: Determines the data structure on the track. APM ... Determines the data structure of the MIC.

That is, first, the value of APT defines the data structure on the track in this digital signal recording / reproducing apparatus. That is, the track after the ITI area is divided into several areas as shown in FIG. 45 according to the value of the APT, the positions on those tracks, the SYNC block configuration, and the ECC for protecting the data from errors.
The data structure such as the configuration is uniquely determined. Further, each area has an application ID that determines the data structure of the area. The meaning is as follows. Application ID of area n ... Determines the data structure of area n.

And the application ID on the tape
Has a hierarchical structure as shown in FIG. That is, the area on the track is defined by the original application ID APT, and AP1 to AP1 are further added to each area.
APn is defined. The number of areas is defined by the APT. In FIG. 46, although written in two layers, a layer may be further provided below it if necessary. Thus APT,
By specifying the values of AP1 to APn, the specific signal processing configuration of the digital signal recording / reproducing apparatus and the use of the apparatus are specified.

Note that the application ID APM in the MIC has only one layer, and the same value as the APT is written by the digital signal recording / reproducing apparatus. With this application ID system,
Using the above-mentioned digital VTR, the cassette, mechanism, servo system, ITI area generation / detection circuit, etc. are diverted as they are to create a completely different product group such as a data streamer or a multi-track digital audio tape recorder. It is possible. Also, even if one area is decided, its contents can be further defined by the application ID of that area.
A very wide range of product development is possible, such as video data for a certain application ID value, video / audio data for another value, or computer data.

Next, a specific example when the value of the application ID is designated will be described. First, APT = 0
The state at 00 is shown in FIG. At this time, area 1, area 2, and area 3 are defined on the track. The positions on those tracks, the SYNC block structure, the ECC structure for protecting data from errors, the gap for guaranteeing each area, and the overwriting margin for guaranteeing overwriting are determined. Further, each area has an application ID that determines the data structure of the area. The meaning is as follows.

AP1 ... Determines the data structure of area 1. AP2 ... Determines the data structure of area 2. AP3 ... Determines the data structure of area 3. And the Application ID of each area
, 000 is defined as follows.

AP1 = 000 ... Image compression recording system consumer digital VTR audio, adopting AAUX data structure AP2 = 000 ... Image compression recording system consumer digital VTR audio, adopting AAUX data structure AP3 = 000 ... Adopts data structure of subcode and ID of image compression recording system consumer digital VTR. That is, when realizing image compression recording system consumer digital VTR, APT, AP1, AP2, AP3 = 0.
It becomes 00. At this time, the APM is naturally 000.

2-2. Circuit Configuration of Digital VTR Recording Unit In the recording unit of the digital VTR of the present embodiment, recording on the tape and MIC is performed according to the recording format described above. Next, the recording unit of the recording unit that executes such recording is performed. A specific circuit configuration and its operation will be described.
The circuit configuration of such a recording unit is shown in FIG.

In this figure, the input Y, RY,
Each component signal of RY is supplied to the A / D converter 42 via the clamper 594 and the slicer 910, and the Y signal is also supplied to the sync separation circuit 44.
The sync signal separated here is supplied to the clock generator 45. The clock generator 45 generates a clock signal for the A / D converter 42 and the blocking / shuffling circuit 43, and also generates a clamp pulse used in the clamper 594.

Although the clamper 594 performs a clamp operation as a preprocessing for AD conversion, it is not desirable to record the identification control signal of the line 285 like other image signals as described above. In the clamper, the operation of suppressing the signal level during the identification control signal period to the non-signal level is also performed. The circuit configuration of the clamper is shown in FIG. In this figure, a luminance signal clamp voltage generation circuit 582 generates a DC voltage corresponding to a quantization level "16", and a color difference signal clamp voltage generation circuit 58 is generated.
9 generates a DC voltage corresponding to the quantization level "128". As a result, the pedestal level of the Y signal is clamped to the potential corresponding to the quantization level "16", and the center level of the color difference signal is clamped to the potential corresponding to the quantization level "128" (see FIG. 19).

Also, the switching information representing the line 285 input from the EDTV-2 recording circuit is supplied to the scanning period pulse generation circuit 590, and the pulse corresponding to the scanning period of the line 285 is generated in the generation circuit. By supplying the scanning period pulses to the switches 584, 586, 587, the movable terminals of these switches are connected to the lower fixed terminals only during this scanning period, and the Y signal and the color difference signal output from the clamper are output. The level is fixed to each of the above clamp voltages during the period of the line 285.

When the blocking process is performed as shown in FIG. 27, one block is formed in the vicinity of the boundary between the non-image part and the main image part in FIG. . That is, the lines 51 to 54, the lines 231 to 234, the lines 313 to 316, and the line 49.
The data of each of the four lines from 2 to 495 is included in one block, and the signal of the main image portion and the signal of the non-image portion are mixed in one block. Therefore, depending on the image content, when the DCT conversion is performed and the data is compressed, the vertical resolution enhancement signal component of the non-image portion is adversely affected, and an image defect such as a horizontal line is generated near the center of the screen reproduced from the digital VTR. It may occur.

Therefore, as a method of avoiding such an obstacle, the image signals (that is, the lines 53, 54, 231, 232, 316, 493 to 493-49 included in each of the above blocks are included.
(5 image signals) may be suppressed to 0 level. As a concrete method, for example, in the EDTV-2 ID decoder in the EDTV-2 recording circuit, in addition to the above-mentioned switching information, information representing the above eight lines is also generated, and these information are transferred to the above clamper. Supply to Y, even during the scanning period of the eight lines.
The levels of the signal and the color difference signal may be fixed to the above clamp voltages.

Instead of suppressing the signal level during the scanning period in the clamper as described above, the DY, DR, and DB values at the output side of the A / D conversion circuit 42 in FIG. Alternatively, the suppression may be performed by switching to "" and "128".

Next, the slicer 910 in FIG. 48 will be described. This slicer has a function of setting the level range of the signal that is AD-converted in the next A / D converter 42. For reference, FIG. 50 shows the principle configuration of the slice circuit provided in the slicer. Slice circuits are installed in the luminance signal path and each color difference signal path, respectively. With this circuit, when the maximum peak voltage of the input signal becomes higher than the DC voltage V2 supplied from the high potential side clip voltage generating circuit 925, the value is suppressed to V2, and the minimum voltage is low. When it becomes lower than the DC voltage V1 supplied from the potential side clip voltage generating circuit 926, the value is suppressed to V1.

This signal slicing process will be described particularly with respect to the slicing circuit provided in the luminance signal path relating to the present invention. FIG. The voltage is set to just the pedestal level. As a result, when the setup lowering signal as shown in [1] of this figure is inputted, the output of the slice circuit fixes the potential of the setup lowering portion to the pedestal level as shown in [2] of this figure. As a result, the signal level of the setup lowering portion cannot be faithfully recorded in the digital VTR.

On the other hand, FIG. 1 shows the slice processing according to the present invention, in which the low-potential-side clip voltage V1 is the lower limit potential of the adaptive setup lowering signal -5IRE.
It is set below. This causes the adaptive setup degradation signal to appear accurately at the output of the slice circuit. As described with reference to FIG. 19, the AD conversion characteristic of the brightness signal AD converter has a pedestal level of 0.
IRE has a quantized value of "16" and a white peak of 100 IRE
Is set to the quantized value “235”, the quantized value “0” corresponds to about −7 IRE, and −5 IRE, which is the lower limit potential of the adaptive setup lowering signal, can be sufficiently AD-converted. It is possible. As described above, in this embodiment, it is possible to record the adaptive setup lowering signal in the digital VTR.

Next, returning to FIG. 48 and continuing the explanation, A
The component signal input to the / D converter 42 is Y
Signal is 13.5MHz, color difference signal is 13.5 / 4MHz
A / D conversion is performed at the sampling frequency of. Then, of these A / D converted outputs, only the data DY, DR, and DB in the effective scanning period are supplied to the blocking / shuffling circuit 43.

This blocking / shuffling circuit 43
In the above, valid data DY, DR, DB as described above
Is converted into a block composed of 8 samples in the horizontal direction and 8 lines in the vertical direction, and 4 blocks of DY,
Performs shuffling to increase the compression efficiency of image data in units of one block each for DR and DB, for a total of six blocks, and to disperse errors during reproduction, and then to the compression encoding unit. Supplied.

The compression / encoding unit performs D on the input block data of 8 samples in the horizontal direction and 8 lines in the vertical direction.
A compression circuit 46 that performs CT (discrete cosine transform), an estimator 48 that estimates whether the result can be compressed to a predetermined data amount, and a quantization step that is finally determined based on the determination result, and variable length encoding is performed. And a quantizer 47 that performs data compression using The output of the quantizer 47 is framed by the framing circuit 49 into the format described in FIG.

The mode processing microcomputer 67 in FIG.
Is a microcomputer that has a man-machine interface with humans and operates in synchronization with the frequency of vertical synchronization of television signals. The signal processing microcomputer 55 operates on the side closer to the machine, and the number of rotations of the drum is 9
It operates in synchronization with 000 rpm and 150 Hz.

Then, VAUX, AAUX, SUBCO
The pack data of each area of the DE is basically generated by the mode processing microcomputer (see FIG.
The identification control signal data for storing in the XTR pack and the HH decode flag for storing in the VAUX SOURCE CONTROL package are input from the EDTV-2 recording circuit to the mode processing microcomputer 67) together with
The absolute track number included in the "title end" pack or the like is generated by the signal processing microcomputer 55, and the process of fitting the track at a predetermined position is executed later. The time code data stored in the SUBCODE is also generated by the signal processing microcomputer 55.

These results are the result of the interface VAUX IC5 that links the microcomputer and the hardware.
6, IC57 for SUBCODE and IC58 for AAUX
Given to. The VAUX IC 56 synthesizes the output from the framing circuit 49 with the synthesizer 50 at a proper timing. In addition, the IC57 for SUBCODE is AP3, S
SID, which is the ID of UBCODE, and SUBCODE
To generate pack data SDATA.

On the other hand, the input audio signal is converted into a digital audio signal by the A / D converter 51. Although not shown in this figure, it is necessary to provide an LPF corresponding to the sampling frequency in the preceding stage of the sampling circuit when AD converting the video signal and the audio signal. The AD-converted audio data is subjected to data distribution processing by the shuffling circuit 52 and then framed in the framing circuit 53 into the format described in FIG. At this time AA
The UX IC 58 generates the AAUX pack data, checks the timing, and packs them in a predetermined location in the audio SYNC block in the synthesis circuit 54.

Next, a pack data recording circuit will be described by taking VAUX as an example. FIG. 2 shows the overall flow. First, the mode processing microcomputer 67 generates pack data to be stored in VAUX. It is converted into serial data by the P / S conversion circuit 118 and sent to the signal processing microcomputer 55 according to the communication protocol between the microcomputers. Here, the S / P conversion circuit 119 restores the parallel data and stores it in the buffer memory 123 via the switch 122.

Of the sent pack data, the header section at the beginning of every 5 bytes is used as the pack header detection circuit 120.
Check to see if the pack requires an absolute track number. Switch 122 if needed
To switch the absolute track number generation circuits 121 to 23.
Bit data is stored in 8-bit units. The storage area is a fixed position of PC1, PC2, and PC3 of all packs to be stored as described in the individual pack structure.

Here, the circuit 119 is a serial I / O in the microcomputer, the circuits 120, 121 and 122 are constituted by a microcomputer program, and the circuit 123 is a RAM in the microcomputer. In this way, the processing of the pack structure uses a microcomputer which is advantageous in terms of cost because the processing time of the microcomputer is sufficient even if the processing is not made by hardware. The data thus stored in the buffer memory 123 is VA
Write side timing controller 12 of UX IC 56
It is read out one by one according to the instructions from 5. At this time, the switch 124 is switched so that the first six packs are for the main area and the subsequent 390 packs are for the optional area.

The FIFO 126 for the main area is 30 bytes, and the FIFO 127 for the optional area is 1950.
Has a capacity of bytes. As shown in [1] of FIG. 3, VAUX has SYNC numbers 19, 20, 156 in the track.
It is stored at. Also, the track number in the frame is
When 1, 3, 5, 7, 9 + + azimuth, SYNC number 1
When the track number in the frame is 0, 2, 4, 6, 8 in the first half of 9, the main area is in the second half of the SYNC number 156 in azimuth. This is collectively drawn in one video frame as shown in FIG. 3 [2].
Thus, when the timing signal nMAIN = “L”,
It becomes the main area. Such a signal is generated by the read side timing controller 129, the switch 128 is switched, and the output is passed to the synthesis circuit 50.

Here, when nMAIN = “L”, the data in the main area FIFO 126 is repeatedly read 10 times (525/60) or 12 times (625/50). When nMAIN = “H”, the optional area FIFO 127 is read. This is 1
Read only once in a video frame. FIG. 4 mainly shows the pack data generation unit in the mode processing microcomputer. First, the circuit is roughly divided into a main area and an optional area. The circuit 131 is a main area data collection and generation circuit. The data as shown in the figure is received from the digital bus or the tuner and a data group as shown at 139 is internally generated. This is assembled into a bit-byte structure of the main pack, a pack header is added by the switch 132, and the pack header is input to the P / S conversion circuit 118 via the switch 136.

To the optional area data collection / generation circuit 133, for example, TELETEXT data, a program title, etc. are input from a tuner, and pack data storing these are generated. The VTR set individually decides which optional area to record. The pack header is set by the circuit 134 and added by the switch 135, and the P / S conversion circuit 1 is set through the switch 136.
38. The timing adjustment circuit 137 performs these timings. Again, circuit 1
Reference numeral 18 is a serial I / O in the microcomputer, and the circuits 131 to 137 are composed of a microcomputer program.

In the generator 59 shown in FIG. 48, A
Each ID part of V (Audio / Video) and pre-SYN
C and post SYNC are generated. Here, AP1,
AP2 is also generated and fitted into a predetermined ID part. Output of generator 59, ADATA (AUDIO DATA), VDA
TA (VIDEO DATA), SID (SUBCOD
E ID), SDATA (SUBCODE DATA)
Are switched by the first switching circuit SW1 in view of the timing.

A predetermined parity is added to the output of the first switching circuit SW1 in the parity generation circuit 60, and the random number generation circuit 61 and the 24/25 conversion circuit 62 are added.
Supplied to Here, the randomizing circuit 61 randomizes the input data in order to eliminate the DC component of the data. Also, 2
The 4/25 conversion circuit 62 performs a process of adding 1 bit for every 24 bits of data to give a pilot signal component, and a precoding process (partial response class IV) suitable for digital recording.

The data thus obtained is supplied to the combiner 63, where A / V SYNC and SUBCODE are supplied.
The audio, video and SUBCODE SYNC patterns generated by the SYNC generator 64 are combined.
The output of the combiner 63 is supplied to the second switching circuit SW2. The ITI data output from the ITI generator 65 and the amble pattern output from the amble pattern generator 66 are also supplied to the second switching circuit SW2.

The ITI generator 65 is supplied with each data of APT, SP / LP and PF from the mode processing microcomputer 67. The ITI generator 65 inserts these data into a predetermined position of the TIA, and the second switching circuit SW2
Supply to Therefore, by switching the switching circuit SW2 at a predetermined timing, the amble pattern and ITI data are added to the output of the combiner 63. The output of the second switching circuit SW2 is amplified by a recording amplifier (not shown), and a magnetic head (not shown).
Is recorded on a magnetic tape (not shown).

The mode processing microcomputer 67 is a digital VT.
Performs mode management for the entire R. The third switching circuit SW3 connected to this microcomputer is an external switch of the VTR main body and is a switch group for instructing various operations other than the recording operation and the reproducing operation.
A P / LP recording mode setting switch is also included. The setting result by this switch group is the mode processing microcomputer 67.
And is given to the signal processing microcomputer 55, the MIC microcomputer 69 and the mechanical control microcomputer (not shown) by communication between the microcomputers.

Next, pack data generation in the MIC microcomputer will be described with reference to FIG. In this figure, serial data input from the mode processing microcomputer 67 is converted into parallel data in the S / P conversion circuit 9 and processed inside the microcomputer. In the main area shown in FIG. 43, the VTR side rewrites the address 0
APM, ME flag in CASSETTE ID pack, and TITLEND pack (note that TAP
The data in the ELENGTH pack is written by the tape manufacturer). Among these, RE flag and ME
The flag is generated inside the MIC microcomputer, but other than that, data is received from the mode processing microcomputer 67. The absolute track number, SL flag and BF flag are generated by the signal processing microcomputer and received via the mode processing microcomputer.

The data thus obtained is assembled according to the operation of the MIC and written in the MIC 68. The switch 12 is for supplying the pack header when writing the TITLE END pack, and is switched to the upper side only at this time. Various events are recorded in the optional area of the MIC. For example, the user inputs necessary data to the mode processing microcomputer to create various packs to be used for the program event, transmits these packs to the MIC microcomputer, and the MIC microcomputer assembles these as needed to create the program event. Then M
Transmit to IC.

The data assembled by the MIC microcomputer is converted into the IIC bus format which is the MIC communication protocol in the circuit 8 and then transmitted to the MIC. The circuits other than the circuits 8 and 9 in the figure are microcomputer programs,
Actually, the data of the circuits 1 and 3 are stored in the RAM inside the microcomputer.

The above series of recording operations are carried out by the cooperation of the mechanical control microcomputer or signal processing microcomputer 55 and the ICs in charge of each part, centering on the mode processing microcomputer 67.
The MIC microcomputer 69 is a MIC processing microcomputer. Here, pack data, APM, etc. in the MIC are generated and given to the MIC 68 in the MIC cassette (not shown) via the MIC contact (not shown).

In the recording apparatus of this embodiment, the EDTV-2 signal is recorded on the recording medium as described above.
An embodiment of the reproducing apparatus for reproducing the EDTV-2 signal from the recording medium thus recorded will be described.

[2] Reproducing Device FIG. 6 shows the overall structure of an embodiment of such a reproducing device. As shown, in this embodiment, a digital VTR
Between the reproducing unit 801 and the television receiver 900, the EDTV-
A two-playback circuit 601 is provided, and component signals Y, BY, and RY derived by performing playback processing from a recording medium in the digital VTR playback unit 801 are EDTV-2.
The signals are input to the Y input terminal, the CB input terminal, and the CR input terminal of the reproduction circuit 601, respectively. In addition to this, VAUX
The TR pack data is also input to the EDTV-2 reproduction circuit. The EDTV-2 reproducing circuit generates an EDTV-2 signal or an NTSC composite signal based on these input signals, and outputs it to the television receiver. The audio signal reproduced by the digital VTR reproducing section is directly input to the television receiver.

The digital VTR reproducing section 801 and the EDTV-2 reproducing circuit 601 will be described in detail below. 1. Digital VTR Reproducing Unit Details of the digital VTR reproducing unit in this embodiment will be described with reference to FIGS. 7 and 8. In FIG. 7, a weak signal reproduced from a magnetic tape (not shown) by a magnetic head (not shown) is amplified by a head amplifier (not shown) and added to the equalizer circuit 71. The equalizer circuit 71 performs reverse processing of the emphasis processing (for example, partial response class IV) performed to improve the electromagnetic conversion characteristics of the magnetic tape and the magnetic head during recording.

The clock extraction circuit 72 extracts the clock CK from the output of the equalizer circuit 71. This clock CK is supplied to the A / D converter 73, and the output of the equalizer circuit 71 is digitized. The 1-bit data thus obtained is written in the FIFO 74 using the clock CK. This clock CK is a temporally unstable signal containing a jitter component of the rotary head drum. However, since the data itself before A / D conversion also contains a jitter component, there is no problem in sampling itself. However, when extracting image data or the like from this point, the time axis adjustment is performed using the FIFO 74 because the data cannot be extracted unless the data is temporally stable. That is, writing is performed with an unstable clock, but reading is performed with a stable clock SCK from a self-excited oscillator (not shown) using a crystal oscillator or the like. The depth of the FIFO 74 is set to have a margin that does not read faster than the input speed of the input data.

The output of each stage of the FIFO 74 is applied to the SYNC pattern detection circuit 75. Here, the SYNC pattern of each area is switched and given by the timing circuit 79 by the fifth switching circuit SW5. The SYNC pattern detection circuit 75 has a flywheel configuration, and once a SYNC pattern is detected, the same S pattern is re-established after a predetermined SYNC block length.
See if the YNC pattern comes. For example 3
It is configured so that it is regarded as true if it is correct more than once to prevent erroneous detection. The depth of the FIFO 74 is required for this several minutes.

When the SYNC pattern is detected in this way, the shift amount is determined which part of the output of each stage of the FIFO 74 should be extracted to extract one SYNC block. Based on this, the fourth switching circuit is determined. SW4 is closed and the necessary bits are fetched into the SYNC block confirmation latch 77. As a result, the captured SY
The NC number is fetched by the SYNC number extraction circuit 78 and supplied to the timing circuit 79. This read S
Since the position on the track where the head is scanning is known from the YNC number, the fifth switching circuit SW5 and the sixth switching circuit SW6 are switched accordingly.

The sixth switching circuit SW6 is switched to the lower side when the head is scanning the ITI area, the ITISYNC pattern is removed by the subtractor 80, and the ITISYNC pattern is added to the ITI decoder 81. Since the ITI area is coded and recorded, each data of APT, SP / LP and PF can be taken out by decoding it. These data are stored in the mode processing microcomputer 82.
Given to. The mode processing microcomputer 82 is connected to a seventh switching circuit SW7 which is a switch group for inputting various commands such as SP / LP mode. The mode processing microcomputer 82 is a digital VT
The operation mode of the entire R is determined, and system control of the entire set is performed in cooperation with the mechanical control microcomputer 85 and the signal processing microcomputer 100 in FIG.

The mode processing microcomputer 82 is connected to the MIC microcomputer 83 for managing the APM and the like. MIC
Information from the MIC 84 in the attached cassette (not shown) is transferred to this MI via a MIC contact switch (not shown).
It is given to the C microcomputer 83 and performs processing of the MIC while sharing the role with the mode processing microcomputer 82. Depending on the set, the MIC microcomputer 83 may be omitted and the mode processing microcomputer 82 may perform the MIC processing.

When the head is scanning the audio area, the video area, or the SUBCODE area, the sixth switching circuit SW6 is switched to the upper side. After the SYNC pattern of each area is extracted by the subtractor 86, it is passed through the 24/25 inverse conversion circuit 87, further added to the inverse randomization circuit 88, and returned to the original data string.
The data thus fetched is added to the error correction circuit 89.

The error correction circuit 89 detects and corrects error data by using the parity added on the recording side. However, the data that cannot be completely removed is ERROR.
Output with flags. Each data is switched and output by the eighth switching circuit SW8. AV
The ID, pre-SYNC, and post-SYNC extraction circuit 90
A / V area, SYNC number stored in pre-SYNC and post-SYNC, track number, and pre-S
Each SP / LP signal stored in the YNC is extracted. These are given to the timing circuit 79 and used for generating various timings. In the extraction circuit 90, AP1 and AP2 are also extracted and supplied to the mode processing microcomputer 82 for checking. AP
When 1, AP2 = 000, it operates normally, but when it is any other value, warning operation such as warning processing is performed.

Regarding SP / LP, the mode processing microcomputer 82 makes a comparative study with that obtained from ITI.
In the ITI area, there are 3 times SP / in the TIA area.
The LP information is written, and the reliability is increased by taking the majority vote etc. There are 2 SYNCs for each of the audio and video in the pre-SYNC, and SP / LP information is written at four locations in total. Here too, there is a majority vote to improve reliability. Finally, if they do not match, the ITI area is preferentially adopted.

VDATA output from the eighth switching circuit SW8 is divided into video data and video accompanying data by the ninth switching circuit SW9 shown in FIG. Then, the video data is given to the deframing circuit 94 together with the error flag. The deframing circuit 94 performs the inverse conversion of the framing on the recording side, and grasps the property of the data packed therein. Then, when there is an error that can not be caught in one data, I understand how it affects other data, so I will handle the propagation error here.
As a result, the ERROR flag becomes a VERROR flag that newly includes a propagation error. The deframing circuit 94 also performs processing for removing error flags by modifying the image data if the data has an error but is not important for image reproduction.

The video data is returned to the data before compression through the dequantization circuit 95 and the decompression circuit 96. Next, the deshuffling / deblocking circuit 97 restores the data to the original image space arrangement. Only after the data is returned to this real image space, the image can be repaired based on the VERROR flag. That is, for example, the image data of one frame before is always stored in the memory, and the image block in error is substituted with the previous image data.

After the deshuffling, DY, DR,
Data is handled by dividing it into 3 systems of DB. Then, the D / A converters 101 to 103 restore the Y, RY, and BY analog components. Clock at this time, 13.5MH _Z for Y, R-Y, the B-Y are 3.375
MH _Z.

The three signal components thus obtained are Y /
The synthesis is performed in the C synthesis circuit 104, and is further performed by the synthesizer 10.
5, the composite sync signal from the sync signal generation circuit 93 is combined and the composite video signal is output from the terminal 106. The digital VTR reproducing section is also provided with a component signal output terminal as shown in this figure, and this component signal is supplied to the EDTV-2 reproducing circuit. Then, in this component signal, the composite sync signal from the sync signal generation circuit 93 is combined with the Y signal (composition circuit 595).

Further, the character display image signal from the character display control circuit 598 is also synthesized with these component signals (synthesis circuits 599, 540, 5).
41). This character display is executed according to the input data from the mode processing microcomputer 82 in FIG.
For example, the user can
The TOC display when a display command is issued, or,
During the reproducing operation of the digital VTR, when it is desired to know whether or not the image currently reproduced is the reproduced image by the wide band image signal including the HH signal, it is displayed whether or not it is the wide band image signal (ie, The mode processing microcomputer
VAUX currently playing from VAUX main area
The contents of the HH flag in the SOURCE CONTROL pack are identified, and the result is displayed on the screen via the character display control circuit 598). The image signal for character display is for terminal 1
Although it is also combined with the composite signal output from 06, it is omitted in this figure.

The ADATA output from the eighth switching circuit SW8 is divided into audio data and audio accompanying data by the tenth switching circuit SW10 shown in FIG. Then, the audio data is given to the deframing circuit 107 together with the ERROR flag.

The deframing circuit 107 performs the inverse conversion of the framing on the recording side, and grasps the property of the data packed therein. Then, when there is an error that can not be caught in one data, I understand how it affects other data, so I will handle the propagation error here. For example, in the case of 16-bit sampling, since one data is in 8-bit units, one ERROR flag indicates that the AER newly includes a propagation error.
It becomes the ROR flag.

The audio data is returned to the original time axis by the next deshuffling circuit 108. At this time, the audio data repair work is performed based on the AERROR flag. That is, a process such as a previous value hold that substitutes the sound immediately before the error is performed. The error period is too long,
If the repair is not effective, the sound itself is stopped by taking measures such as muting.

After performing such a treatment, the D / A converter 1
It is returned to the analog value by 09, and is output from the analog audio output terminal 110 while timing such as lip sync with the image data is taken. Now, each data of VAUX and AAUX separated by the ninth switching circuit SW9 and the tenth switching circuit SW10 is
IC for VAUX 98 and IC for AAUX 111, respectively
In the above, preprocessing such as majority processing is performed while referring to the error flag.

Further, the SUBCODE area ID data SID and pack data SDATA output from the eighth switching circuit SW8 are the SUBCODE IC 11
2, the preprocessing such as the majority processing is performed while also referring to the error flag. The data that has been subjected to these pre-processing is then given to the signal processing microcomputer 100, and the final reading operation is performed. The errors that could not be removed in the pre-processing are VAUXE
It is given to the signal processing microcomputer 100 as R, SUBER, and AAUXER.

Here, the SUBCODE IC 112 is the AP
3 and APT are extracted and passed to the mode processing microcomputer 82 via the signal processing microcomputer 100 for checking. The mode processing microcomputer 82 uses the A from the ITI.
A based on PT and APT from SUBCODE
The value of PT is confirmed, and when the value is not "000", an operation such as a warning process is performed. Further, when AP3 = 000, the normal operation is performed, but when the value is other than that, warning operation such as warning processing is performed.

Here, supplementing the error processing of the pack data, each area has a main area and an optional area. Since the same data is written 10 times in the main area, even if some of them have an error, they can be supplemented and reproduced with other data, and the ERROR flag there is no longer an error.
However, since the data is written once for the optional areas other than SUBCODE, the error remains VAU.
It will remain as XER and AAUXER.

The signal processing microcomputer 100 further performs propagation error processing, data repair processing, etc., by analogy with the context of each data pack. The result of this determination is given to the mode processing microcomputer 82 and used as a material for determining the behavior of the entire set. Next, take VAUX as an example.
A circuit for reproducing pack data in the IC 98 for processing and the signal processing microcomputer 100 will be described. Here, a configuration example using a simple processing method of not writing in the memory in the case of an error will be described as the preprocessing, not the majority processing. FIG. 9 shows a circuit example of the VAUX IC 98. First, the VAUX pack data from the switching circuit SW9 is transferred to the nMA of FIG.
At the timing of IN = “L”, the switch 141 is switched to allocate to the main area memory 145 and the optional area FIFO 148.

The pack data in the main area is read by the pack header detection circuit 143 and the switch 144 is switched. Then, the data is written in the main area memory only when it is not ERROR. This memory has a 9-bit configuration, and the shaded portion in the figure is the storage bit of the error flag. As the initial setting of the memory for the main area, all the contents are set to 1 (= no information) for each video frame. And if it is ERROR, do nothing and ERRO
If it is not R, the data is written and 0 is written in the error flag. Since the same pack is written 10 or 12 times in one frame in the main area, the place where 1 is set in the error flag at the end of one video frame is finally recognized as an error.

Since the optional area is basically written once, the ERROR flag is written as it is in the optional area FIFO 148 together with the data. These are sent to the signal processing microcomputer 100 via the switches 146 and 147 which are switched by the read side timing controller 149. The signal processing microcomputer 100 analyzes the received pack data and the error flag.
The processing operation in the signal processing microcomputer 100 will be described with reference to FIG. In this figure, the pack header identification circuit 150 sorts the pack data (VAUXDT) sent from the VAUX IC 98 and stores it in the memory 151. This does not particularly distinguish between the main area and the optional area.

In the case of a pack in the main area, VAU
Similar to the X IC 98, the writing process is not performed when the error flag “1” is set in VAUXER. As a result, at least one video frame before can be repaired. Since it is considered that the content of the main area has a very strong correlation with the value one video frame before, there is no particular problem even if it is substituted by this processing.

On the other hand, in the case of an optional area pack, it is considered that there is no correlation with the value one video frame before, so error propagation processing is performed in pack units.
This method is basically carried out by changing all the data to FFh if there is an error in the fixed-length pack data of 5 bytes, but it is also necessary to deal with individual packs. . For example, in the case of a "Telexext" pack in which Teletext data is stored,
Because of the number of consecutive packs, even if there is an error in the pack header between the packs, the pack can be easily replaced with the Teletxt pack header. Even if there is an error in the data part, if there is no error in the pack header, the pack will not be changed to the "pack without information".
This restores the Teletext data to the Tel
Since it is entrusted to the parity check of the etext decoder, the data is left as it is even if an error is found.

That is, in the digital VTR of this embodiment, although not shown in the reproduction circuit of FIG. 8, the data amount is large, such as text data and Teletext data, and a single data sequence is formed. The characteristic pack data is transferred from the signal processing microcomputer 100 to a dedicated data processing circuit to perform error correction with higher efficiency and reduce the load on the mode processing microcomputer 82.

No error flag already exists in the data prepared by the processing in the signal processing microcomputer 100 as described above. These are converted into serial data by the P / S conversion circuit 152 and sent to the mode processing microcomputer 82 according to the communication protocol between the microcomputers. Where S / P
The conversion circuit 153 restores the parallel data and performs pack data decomposition analysis.

Here, the circuits 150 and 155 and the switch 154 are constituted by a program of a microcomputer, the memory 151 is a memory inside the microcomputer, and the circuits 152 and 153 are serial I / O inside the microcomputer. In the pack data decomposition analysis in the mode processing microcomputer 82, the pack data is analyzed based on the confirmed pack header, and various control information, display information, etc. obtained as the analysis result are respectively controlled circuits, display circuits, etc. Supply to. For example, as described above, the TOC display data and the like are supplied to the character display control circuit 598 in FIG. 8, but in addition to this, as shown in FIG.
The TR pack data is supplied to the EDTV-2 reproducing circuit via an interface (not shown).

2. EDTV-2 Reproducing Circuit Next, the EDTV-2 for inputting the component signal and VAUX TR pack data from the digital VTR reproducing section described above to generate a desired composite signal.
The reproduction circuit 601 will be described.

FIG. 11 shows an example of a specific circuit of the reproducing circuit 601. In this figure, the VAUX TR supplied from the mode processing microcomputer of the digital VTR reproducing section.
The pack data is input to the DATA TYPE identification circuit 570 from the terminal 520, and the DATA TYPE stored in the lower 4 bits of PC1 of the pack is checked here (the mode processing microcomputer uses the V
When the VAUX TR pack is not recorded in the main area of the AUX area, "1" is stored in all of PC1 to PC4 No Information
The pack is supplied to the terminal 520).

The identification circuit 570 is a DATA TYPE
Is "EDTV-2 data", or only when it is "0011", the discrimination signal DS is set to EDT.
The V-2ID encoder 524, the line decoder switch circuit 530, and the VT / VH ′ signal modulator 531 are supplied to turn on the operation of these circuit blocks.
At this time, the line decoder switch circuit 530 generates a control signal only during the non-image part period, and outputs this control signal to the channel synthesizer 528 and the color modulator 526.
During this non-image part period, the channel synthesizer 528 is kept on and the color modulator is kept off.

As a result, the VT / V recorded on the recording medium through the color difference signal recording channel during the non-image portion period.
The H'signal is subjected to a conversion process opposite to the conversion process received by the channel divider of FIG. 21 in the channel synthesizer, and further, the VT / VH 'signal modulator 531 modulates the Q-axis color subcarrier. After that, in the adding circuit 529, it is combined with the chroma signal from the color modulator 526. The color subcarrier used for color modulation in the color modulator 526 can be obtained by supplying the burst signal separated in the sync separation circuit 525 to a color subcarrier reproducing circuit (not shown) in the color modulator.

The line decoder switch circuit 530
Outputs the gate pulse G corresponding to the period of the 22nd line and the 285th line to the EDTV-2ID encoder 524. On the other hand, the encoder 524 uses the DATA T
An identification control signal defined by EDTV-2 is generated based on the VAUX TR pack data input from the YPE identification circuit, and this identification control signal is output to the addition circuit 527 during the line period in which the gate pulse is input. , Terminal 5
It is combined with the reproduction luminance signal input from the reference numeral 21 (note that the adaptive setup reduction signal reproduced from this terminal is input during the non-image portion period).

The luminance signal and identification control signal obtained from the adder circuit 527 and the chroma signal and VT / VH 'signal obtained from the adder circuit 529 are further added to the Y / C synthesis circuit 532.
The EDTV-2 signal is generated by being combined in (1) and is output from the terminal 533 to the television receiver. Note that the output terminals 534 and 535 are terminals for outputting to a television receiver having an input terminal in which a luminance signal and a chroma signal are separated, and even when a letterbox screen is displayed on such a receiver. , Obstacles in the non-image area are not noticeable

When the signal reproduced by the digital VTR reproducing unit is of the NTSC system,
Since the discrimination signal DS is not output from the DATA TYPE discrimination circuit 570, the encoder 524 and the switch circuit 53
0, the modulator 531 is turned off, the color modulator 526 is always kept on, and the gate pulse G is not output. Therefore, the output side of the Y / C synthesis circuit 532 is An NTSC signal obtained by combining the luminance signal input to the terminal 521 and the chroma signal output from the color modulator 526 is obtained.

Although the embodiments of the recording apparatus and the reproducing apparatus according to the present invention have been described above, it goes without saying that the recording and reproducing apparatus can be immediately constructed by combining these embodiments. Specific configurations and circuit operations of the embodiment of the recording / reproducing apparatus can be those shown in the circuit configurations and the circuit operations of the respective embodiments of the recording apparatus and the reproducing apparatus, and therefore description thereof will be omitted. To do.

[0182]

When the reproduction signal from the digital VTR is input to the receiver not equipped with the EDTV-2 decoder, the vertical direction of the non-image part is the same as when the EDTV-2 signal from the broadcasting station is directly received. The resolution enhancement signal is inconspicuous.
Even in a receiver in which a luminance signal and a chrominance signal can be separately input using dedicated input terminals, when an image based on the EDTV-2 signal is displayed on a letterbox screen, a vertical resolution enhancement signal of a non-image part is displayed. Is not noticeable.

[Brief description of drawings]

FIG. 1 is a diagram illustrating slice processing according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating generation of pack data in a recording circuit of a digital VTR.

FIG. 3 is a diagram illustrating a main area on a recording track.

FIG. 4 is a diagram illustrating generation of pack data in a mode processing microcomputer.

FIG. 5 is a diagram illustrating generation of pack data in an MIC microcomputer.

FIG. 6 is a diagram showing an overall configuration of a playback device.

FIG. 7 is a diagram showing a configuration of a part of a digital VTR reproducing unit.

FIG. 8 is a diagram showing the configuration of another portion of the digital VTR reproducing unit.

FIG. 9 is a diagram illustrating processing of reproduction pack data in a VAUX IC.

FIG. 10 is a diagram illustrating processing of reproduction pack data in a signal processing microcomputer.

FIG. 11 is a diagram showing a configuration example of an EDTV-2 reproducing circuit.

FIG. 12 is a diagram illustrating distributions of a luminance signal, a color signal, and a horizontal resolution enhancement signal in an EDTV-2 signal.

FIG. 13 is a diagram illustrating the distribution of vertical resolution enhancement signals.

FIG. 14 is a diagram illustrating an adaptive setup lowering process.

FIG. 15 is a diagram showing an example of a specific circuit for performing adaptive setup lowering processing.

FIG. 16 is a diagram showing characteristics of a non-linear circuit used in the adaptive setup degradation processing circuit.

FIG. 17 is a diagram showing a format of an identification control signal.

FIG. 18 is a diagram illustrating a format of an EDTV-2 signal for one frame.

FIG. 20 is a diagram showing an overall configuration of a recording device.

FIG. 21 is a diagram showing a circuit configuration example of an EDTV-2 recording circuit.

FIG. 22 is a diagram showing a circuit configuration example of a VT / VH ′ demodulation device.

FIG. 23 is a diagram showing a specific circuit example of a channel division device.

FIG. 24 is a diagram showing a recording format of one track of a digital VTR.

FIG. 25 is a pre-SYNC block and a post-SYNC.
It is a figure which shows the structure of C block.

[Fig. 26] Fig. 26 is a diagram illustrating the framing format of AUDIO and the structure of a 1SYNC block.

FIG. 27 is a diagram illustrating blocking of image data for one frame.

FIG. 28 is a diagram illustrating generation of a DCT block for one frame.

FIG. 29 is a diagram showing a VIDEO framing format to which an error correction code is added.

[Fig. 30] Fig. 30 is a diagram illustrating the configuration of a VIDEO buffering unit and a 1SYNC block.

FIG. 31 is a diagram illustrating a structure of a SUBCODE area for one track.

[Fig. 32] Fig. 32 is a diagram for describing the structure of the ID part of the SYNC block in the AUDIO area and the VIDEO area.

FIG. 33 is a diagram for explaining the structure of the ID part of the SYNC block in the SUBCODE area.

FIG. 34 is a diagram showing a basic structure of a pack.

FIG. 35: Definition of a group of packs with large items,
And VAUX SOURCE pack and VAUX SOU
It is a figure which shows the detail of RCE CONTROL pack.

FIG. 36: VAUX REC DATE pack, VAU
X REC TIME Pack, VAUX REC TI
ME BINARY GROUP pack, CLOSED
It is a figure which shows the detail of a CAPTION pack and a VAUX TR pack.

FIG. 37: CASSETTE ID pack, TAPE
It is a figure which shows the detail of a LENGTH pack and a TITLE END pack.

FIG. 38: PROGRAM START Pack, PRO
GRAM END pack and PROGRAM REC
It is a figure which shows the detail of DATE TIME pack.

FIG. 39 is a diagram illustrating the structure of an AAUX area for one frame.

FIG. 40 is a diagram illustrating a structure of a VAUX area for one track.

FIG. 41 is a diagram illustrating a pack structure of a VAUX area for one frame.

FIG. 42 is a diagram for explaining multiple writing of pack data in a SUBCODE area.

FIG. 43 is a diagram illustrating a memory map of a memory-in cassette.

FIG. 44 is a diagram showing an example of a program event.

FIG. 45 is a diagram illustrating definition of a track format by APT.

FIG. 46 is a diagram illustrating a hierarchical structure of application IDs.

FIG. 47 is a diagram illustrating a format on a track when the application ID is “000”.

FIG. 48 is a diagram showing a recording circuit of a digital VTR.

FIG. 49 is a diagram showing an example of a circuit of a clamper.

FIG. 50 is a diagram showing a principle configuration of a slicer.

FIG. 51 is a diagram for explaining slice processing in a conventional digital VTR.

[Explanation of symbols]

600 ... EDTV-2 recording circuit, 502 ... VT / V
H'demodulator, 503 ... Three-dimensional Y / C separation circuit, 5
04 ... EDTV-2ID decoder, 506, 530 ... Line decoder switch circuit, 507 ... HH 'signal decoder, 510 ... Channel dividing device, 524 ... EDT
V-2ID encoder, 528 ... Channel synthesizer, 531 ... VT / VH 'signal modulator, 570 ...
DATA TYPE identification circuit 910 ... slicer,

─────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] May 18, 1995

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Brief description of the drawing

[Correction method] Change

[Correction content]

[Brief description of drawings]

FIG. 1 is a diagram illustrating slice processing according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating generation of pack data in a recording circuit of a digital VTR.

FIG. 3 is a diagram illustrating a main area on a recording track.

FIG. 4 is a diagram illustrating generation of pack data in a mode processing microcomputer.

FIG. 5 is a diagram illustrating generation of pack data in an MIC microcomputer.

FIG. 6 is a diagram showing an overall configuration of a playback device.

FIG. 7 is a diagram showing a configuration of a part of a digital VTR reproducing unit.

FIG. 8 is a diagram showing the configuration of another portion of the digital VTR reproducing unit.

FIG. 9 is a diagram illustrating processing of reproduction pack data in a VAUX IC.

FIG. 10 is a diagram illustrating processing of reproduction pack data in a signal processing microcomputer.

FIG. 11 is a diagram showing a configuration example of an EDTV-2 reproducing circuit.

FIG. 12 is a diagram illustrating distributions of a luminance signal, a color signal, and a horizontal resolution enhancement signal in an EDTV-2 signal.

FIG. 13 is a diagram illustrating the distribution of vertical resolution enhancement signals.

FIG. 14 is a diagram illustrating an adaptive setup lowering process.

FIG. 15 is a diagram showing an example of a specific circuit for performing adaptive setup lowering processing.

FIG. 16 is a diagram showing characteristics of a non-linear circuit used in the adaptive setup degradation processing circuit.

FIG. 17 is a diagram showing a format of an identification control signal.

FIG. 18 is a diagram illustrating a format of an EDTV-2 signal for one frame.

FIG. 19 is a diagram illustrating conversion characteristics when AD converting a luminance signal and a color difference signal.

FIG. 20 is a diagram showing an overall configuration of a recording device.

FIG. 21 is a diagram showing a circuit configuration example of an EDTV-2 recording circuit.

FIG. 22 is a diagram showing a circuit configuration example of a VT / VH ′ demodulation device.

FIG. 23 is a diagram showing a specific circuit example of a channel division device.

FIG. 24 is a diagram showing a recording format of one track of a digital VTR.

FIG. 25 is a pre-SYNC block and a post-SYNC.
It is a figure which shows the structure of C block.

[Fig. 26] Fig. 26 is a diagram illustrating the framing format of AUDIO and the structure of a 1SYNC block.

FIG. 27 is a diagram illustrating blocking of image data for one frame.

FIG. 28 is a diagram illustrating generation of a DCT block for one frame.

FIG. 29 is a diagram showing a VIDEO framing format to which an error correction code is added.

[Fig. 30] Fig. 30 is a diagram illustrating the configuration of a VIDEO buffering unit and a 1SYNC block.

FIG. 31 is a diagram illustrating a structure of a SUBCODE area for one track.

[Fig. 32] Fig. 32 is a diagram for describing the structure of the ID part of the SYNC block in the AUDIO area and the VIDEO area.

FIG. 33 is a diagram for explaining the structure of the ID part of the SYNC block in the SUBCODE area.

FIG. 34 is a diagram showing a basic structure of a pack.

FIG. 35: Definition of a group of packs with large items,
And VAUX SOURCE pack and VAUX SOU
It is a figure which shows the detail of RCE CONTROL pack.

FIG. 36: VAUX REC DATE pack, VAU
X REC TIME Pack, VAUX REC TI
ME BINARY GROUP pack, CLOSED
It is a figure which shows the detail of a CAPTION pack and a VAUX TR pack.

FIG. 37: CASSETTE ID pack, TAPE
It is a figure which shows the detail of a LENGTH pack and a TITLE END pack.

FIG. 38: PROGRAM START Pack, PRO
GRAM END pack and PROGRAM REC
It is a figure which shows the detail of DATE TIME pack.

FIG. 39 is a diagram illustrating the structure of an AAUX area for one frame.

FIG. 40 is a diagram illustrating a structure of a VAUX area for one track.

FIG. 41 is a diagram illustrating a pack structure of a VAUX area for one frame.

FIG. 42 is a diagram for explaining multiple writing of pack data in a SUBCODE area.

FIG. 43 is a diagram illustrating a memory map of a memory-in cassette.

FIG. 44 is a diagram showing an example of a program event.

FIG. 45 is a diagram illustrating definition of a track format by APT.

FIG. 46 is a diagram illustrating a hierarchical structure of application IDs.

FIG. 47 is a diagram illustrating a format on a track when the application ID is “000”.

FIG. 48 is a diagram showing a recording circuit of a digital VTR.

FIG. 49 is a diagram showing an example of a circuit of a clamper.

FIG. 50 is a diagram showing a principle configuration of a slicer.

FIG. 51 is a diagram for explaining slice processing in a conventional digital VTR.

[Explanation of Codes] 600 ... EDTV-2 recording circuit, 502 ... VT / V
H'demodulator, 503 ... Three-dimensional Y / C separation circuit, 5
04 ... EDTV-2ID decoder, 506, 530 ... Line decoder switch circuit, 507 ... HH 'signal decoder, 510 ... Channel dividing device, 524 ... EDT
V-2ID encoder, 528 ... Channel synthesizer, 531 ... VT / VH 'signal modulator, 570 ...
DATA TYPE identification circuit 910 ... slicer,

Claims (3)

[Claims] 1. A recording apparatus for recording on a recording medium a television signal having a luminance signal, a color signal, and a vertical resolution enhancement signal multiplexed with a signal subjected to adaptive setup lowering processing of a predetermined line, (1) From the television signal, a luminance signal, a color signal, a vertical resolution enhancement signal,
And (2) a luminance signal AD conversion means for performing AD conversion on the luminance signal separated by the separation means, and
A luminance signal processing circuit for converting the output of the luminance signal AD converting means into a signal form for recording and recording it on a recording medium;
(3) A color signal AD conversion unit for AD converting the color signal separated by the separation unit is provided, and the color signal AD
A color signal processing circuit for converting the output of the converting means into a signal form for recording and recording it on a recording medium, and (4) the vertical resolution enhancement signal separated by the separating means via the color signal processing circuit. Vertical resolution enhancing signal recording means for recording on a recording medium; and (5) adaptive setup lowering signal recording means for recording the adaptive setup lowering signal separated by the separating means on the recording medium via the luminance signal processing circuit. , And the luminance signal processing circuit,
Further, the brightness signal AD conversion means includes setting means for setting a level range of the brightness signal AD-converted, and the setting means sets the lower limit level of the level range lower than the pedestal level of the brightness signal. A recording device for television signals characterized by. 2. A television signal having a luminance signal, a chrominance signal, and a vertical resolution reinforcement signal multiplexed with a signal subjected to adaptive setup lowering processing of a predetermined line reproduces the television signal from a recording medium. In a television signal reproducing apparatus, (1) reproducing means for scanning a recording medium, and (2) luminance signal reproducing means for reproducing a luminance signal in which an adaptive setup reduction signal is multiplexed from an output signal of the reproducing means, (3) A color signal reproducing means for reproducing the color signal from the output signal of the reproducing means, (4) a vertical resolution enhancing signal reproducing means for reproducing a vertical resolution enhancing signal from the output signal of the reproducing means, and (5). Multiplexing means for multiplexing the output of the vertical resolution enhancing signal reproducing means and the output of the color signal reproducing means, and (6) a first output signal for outputting the output signal of the multiplexing means to the outside. And a second output signal terminal (7) for outputting the output signal of the luminance signal reproducing means to the outside. 3. A television signal having a luminance signal, a chrominance signal, and a vertical resolution reinforcement signal multiplexed with a signal subjected to adaptive setup lowering processing of a predetermined line is recorded and reproduced using a recording medium. In the recording / reproducing device,
(1) Separation means for separating a luminance signal, a color signal, a vertical resolution enhancement signal, and an adaptive setup reduction signal from the television signal, and (2) luminance for AD-converting the luminance signal separated by the separation means. A luminance signal processing circuit which includes a signal AD converting means and which converts the output of the luminance signal AD converting means into a signal form for recording and records it on a recording medium; and (3) the colors separated by the separating means. A color signal processing circuit that includes a color signal AD conversion unit that performs AD conversion of the signal, and that converts the output of the color signal AD conversion unit into a signal form for recording and records the signal on a recording medium;
(4) Vertical resolution reinforcement signal recording means for recording the vertical resolution reinforcement signal separated by the separation means on a recording medium via the color signal processing circuit, and (5) adaptive setup separated by the separation means. Adaptive setup drop signal recording means for recording a drop signal on a recording medium via the luminance signal processing circuit, (6) reproducing means for scanning the recording medium, and (7) adaptive setup from an output signal of the reproducing means. Luminance signal reproducing means for reproducing a luminance signal in which the lowered signal is multiplexed, (8) Color signal reproducing means for reproducing the color signal from the output signal of the reproducing means, and (9) Vertical from the output signal of the reproducing means. Vertical resolution enhancing signal reproducing means for reproducing the resolution enhancing signal, and (10) multiplexing means for multiplexing the output of the vertical resolution enhancing signal reproducing means and the output of the color signal reproducing means. , (11) a first output signal terminal for outputting an output signal of said multiplexing means to the outside, (12)
A second output signal terminal for outputting the output signal of the luminance signal reproduction means to the outside, and the luminance signal processing circuit is further subjected to AD conversion in the luminance signal AD conversion means. A recording / reproducing apparatus for a television signal, comprising: setting means for setting the level range of 1., wherein the setting means sets the lower limit level of the level range lower than the pedestal level of the luminance signal.