JP3521495B2 - Audio signal recording method, audio signal reproducing apparatus, and audio signal recording / reproducing method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio signal recording method for encoding and recording an audio signal, an audio signal reproducing apparatus for reproducing an audio signal recorded by the audio signal recording method, and an audio signal encoding method. The present invention relates to an audio signal recording / reproducing method in which recording and reproduction are performed.

[0002]

2. Description of the Related Art In a consumer digital VTR of an image compression recording system which is currently being researched and developed, the number of quantization bits and sample frequency for encoding and recording an audio signal are as follows. Is specified. 16-bit mode; 48 KHz, 44.1 KHz, 32
KHz 12-bit mode; 32 KHz Further, in the digital recording of audio signals conventionally performed in consumer equipment, the following quantum bit number and sample frequency are adopted.

Satellite broadcasting A mode: 10 bits, 32 KHz, B mode: 16 bits, 48 KHz, CD, LD 16 bits; 44.1 KHz, MD, DCC, S-VHS, 16 bits; 48 KHz, DAT 16 bits; 48 KHz, 44.1KHz, 32KH
z, NT 12 bits; 32 KHz, On the other hand, in a commercial digital VTR, a composite type D2, a component type D1, a digital BE
Both TACAM and HDVTR use 20 bits; 48 KHz. Therefore, the number of quantization bits is always different between digital audio data in consumer equipment and digital audio data in business equipment.

Further, in order to develop the above-mentioned consumer digital VTR into a commercial digital VTR, it is indispensable to record audio in a 20-bit mode. In this case, the same cassette tape is used for consumer use. And the possibility of being used in both digital VTRs for commercial use. However, since the consumer digital VTR is not provided with a 20-bit mode recording / reproducing circuit, it is impossible to reproduce the voice recorded by the business digital VTR by the consumer digital VTR.

On the other hand, regarding the processing of the image signal,
Both consumer and commercial digital VTRs employ the same compression processing method and are therefore compatible. Therefore,
A single cassette tape is recorded on both consumer and commercial digital VTRs, and this tape is recorded on a consumer digital VTR.
When reproduced by TR, a situation occurs in which the sound is not output even if the image is reproduced in the portion recorded on the tape for professional digital VTR on the tape.

[0006]

An image compression recording type consumer digital VTR is developed into a commercial digital VTR capable of recording high quality 20-bit mode audio. Then, the commercial digital VTR and the consumer digital VTR are made compatible with each other in reproduction operation not only for image data but also for audio data.

[0007]

According to a first aspect of the present invention, encoded audio data of each channel obtained by encoding audio signals of a plurality of channels has item data for defining a format of subsequent data. Each area is constructed in units of packs with fixed length bytes,
An audio signal recording method of recording on a recording medium in which an audio area, an AAUX area, a video area, a VAUX area, and a SUBCODE area are used. While making it possible to arbitrarily select from among the number of quantization bits, the encoded audio data of each channel is recorded independently in each channel in the recording area of each channel provided on the recording medium, and, The data amount of the encoded audio data obtained by encoding the audio signal according to the selected number of quantized bits exceeds the recording capacity of the recording area of the encoded audio data of each channel configured in the pack. Occasionally, recording of the audio signal of a specific channel among the audio signals of a plurality of channels is stopped, and For coded audio data of other channels other than, only the data part consisting of the upper bit components of the bit components forming the coded audio data within the range not exceeding the recording capacity of the recording area of the coded audio data. Is recorded in a recording area constituted by each pack of the audio signal of the other channel as a unit, and the data portion including the lower bit component other than the upper bit component in the encoded audio data is recorded in the audio of the specific channel. It is characterized in that the signal pack is recorded in a recording area that is configured in units.

According to a second aspect of the present invention, an audio area, an AAUX area, and a video area, each area of which is composed of a pack having a fixed-length byte having item data that defines a format of subsequent data, V
In the recording area of each channel provided on the recording medium in which the AUX area and the SUBCODE area are used,
Encoded audio data of each channel obtained by encoding audio signals of a plurality of channels is independently recorded for each channel, and the number of quantization bits at the time of encoding is set to a value of a plurality of quantization bit numbers. By making it possible to arbitrarily select from among the above, the code representing the selected quantization bit number is recorded as additional data on the recording medium, and the audio signal is encoded according to the selected quantization bit number. When the data amount of the encoded audio data to be obtained exceeds the recording capacity of the recording area of the encoded audio data of each channel configured by using the pack as a unit, the audio signal of a specific channel among the audio signals of a plurality of channels Is stopped and the encoded audio data of other channels other than the specific channel is recorded. Of the constituent bit components, only the data portion consisting of the higher-order bit components in a range that does not exceed the recording capacity of the recording area of the encoded audio data is recorded with each pack of audio signals of the other channels as a unit. The data part is recorded in the area, and further, the data portion including the lower bit component other than the upper bit component in the encoded audio data is recorded in the recording area configured by the pack of the audio signal of the specific channel as a unit. An audio signal reproducing apparatus for reproducing an audio signal from a recording medium recorded according to an audio signal recording method, comprising: a DA conversion circuit for DA converting encoded audio data reproduced from the recording medium; Encoded audio data reproduced based on the accompanying data reproduced from a pack having a fixed length byte in the AAUX area A quantizing bit number identifying circuit for identifying the quantizing bit number, and when the quantizing bit number identified by the quantizing bit number identifying circuit is larger than the quantizing bit number of the DA conversion circuit. , The bit components constituting the reproduced encoded audio data are extracted from the upper bits by the number of bits corresponding to the number of quantization bits of the DA conversion circuit, and the upper bit component of the extracted encoded audio data is extracted from the DA. The feature is that the audio signal is reproduced by inputting to the conversion circuit. In this case, when the quantization bit number identified by the quantization bit number identifying circuit is larger than the quantization bit number of the DA converting circuit, the data reproduced from the recording area in which the data portion including the lower bit component is recorded. It is preferable to have means for stopping the operation of the circuit for processing.

According to a fourth aspect of the present invention, an audio area, an AAUX area, and a video area, each area of which is composed of a pack having a fixed length byte having item data which defines a format of subsequent data, V
In the recording area of each channel provided on the recording medium in which the AUX area and the SUBCODE area are used,
Encoded audio data of each channel obtained by encoding audio signals of a plurality of channels is independently recorded for each channel, and the number of quantization bits at the time of encoding is set to a value of a plurality of quantization bit numbers. By making it possible to arbitrarily select from among the above, the code representing the selected quantization bit number is recorded as additional data on the recording medium, and the audio signal is encoded according to the selected quantization bit number. When the data amount of the obtained encoded audio data exceeds the recording capacity of the recording area of the encoded audio data of each channel configured in units of the pack, a specific channel of the encoded audio data of a plurality of channels is recorded. The recording of the encoded audio data is stopped, and the encoded audio data of the channels other than the specific channel is Of the bit components that make up the encoded audio data, only the data portion consisting of the upper bit components in a range that does not exceed the recording capacity of the recording area of the encoded audio data is packed in each of the encoded audio data of the other channels. Is recorded in a recording area configured as a unit, and a data portion composed of lower bit components other than the upper bit component in the encoded audio data is further configured in units of a pack of encoded audio data of the specific channel. An audio signal reproducing apparatus for reproducing an audio signal from a recording medium recorded according to an audio signal recording method adapted to record in a recording area, and DA-converting encoded audio data reproduced from the recording medium. Based on the DA conversion circuit and the accompanying data reproduced from the pack having the fixed length bytes of the AAUX area of the recording medium. And a quantization bit number identifying circuit for identifying the quantization bit number of the reproduced encoded audio data, wherein the quantization bit number identified by the quantization bit number identifying circuit is the quantum of the DA conversion circuit. If it is smaller than the number of encoded bits, the reproduced encoded audio data is set to the input side of the DA conversion circuit as the upper bit component of the input data to the DA conversion circuit, and the remaining lower bits of the input data are set. It is characterized in that the reproduced audio signal is taken out from the DA conversion circuit by setting predetermined dummy data as a component.

According to a fifth aspect of the present invention, the encoding of each channel obtained by encoding the audio signals of the plurality of channels in accordance with the number of quantization bits arbitrarily selected from the plurality of number of quantization bits is performed. Voice data,
After recording each channel independently in the recording area of each channel provided on the recording medium and replacing the error part of the encoded audio data reproduced from the recording medium with a predetermined error code. , A voice signal recording / reproducing method adapted to perform a decoding process for extracting an original voice signal, the encoded voice data being obtained by encoding the voice signal according to the selected number of quantization bits. When the data amount exceeds the recording capacity of the recording area of the encoded audio data of each channel, the recording of the audio signal of the specific channel among the audio signals of the plurality of channels is stopped, and the data other than the specific channel is stopped. For the audio signal of the channel, the recording capacity of the recording area of the audio signal among the bit components that make up the encoded audio data. Only the data part consisting of the upper bit component of the range not exceeding is recorded in each recording area of the audio signal of the other channel, and the data part consisting of the lower bit component other than the upper bit component in the encoded audio data is recorded. The data is recorded in the recording area of the audio signal of the specific channel, and further, in the recording of the data portion including the lower bit component, predetermined dummy data is recorded in the remaining empty area in which the lower bit component is recorded. The data value is set to a value that allows the data reproduced from the recording area of the audio signal of the specific channel to be distinguished from the error code.

[0011]

[0012]

The audio data recording channel having a large number of quantization bits is recorded using the audio data recording channel having a small number of quantization bits of the consumer digital VTR. Also in a commercial digital VTR, a voice signal recorded by being converted into a code for consumer use with a small number of quantization bits is reproduced. Also, in a consumer digital VTR, a voice signal which is converted into a code having a large number of quantization bits for business and recorded is reproduced, and in this case, reproduction from a channel in which only lower bit components of audio data are recorded. Muting the signal prevents the generation of noise.

In a channel for recording the lower bit component of audio data having a large number of quantization bits, the value of dummy data recorded in the remaining empty area where the lower bit component is recorded is used in the error processing of the reproduction system of the audio data. By setting the value so as not to be confused with the error code, the error processing using the error code can be performed as the error processing in the reproduction processing system of the channel in which the lower bit component is recorded, like the other channels. .

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments in which the present invention is applied to an image compression recording type consumer digital VTR (hereinafter referred to as a digital VTR) in a helical scan format will be sequentially described according to the following items. 1. Overview of digital VTR 1-1. Digital VTR recording format (1) ITI area (2) AUDIO area (3) VIDEO area (4) SUBCODE area (5) ID structure (6) MIC (7) Pack structure and type (8) Associated information recording Area structure 1-2. Recording circuit of digital VTR 1-3. Digital VTR reproduction circuit 2. Application ID system 3. Recording / playback of audio data 3-1. 16-bit mode recording 3-2. 20-bit mode recording 3-3. 20-bit and 16-bit mixed mode recording 3-4. Audio data processing circuit (1) Consumer digital VTR (2) Professional digital VTR

1. Outline of Digital VTR First, an outline of the digital VTR constituting this embodiment will be described in the order of its recording format, recording circuit, and reproducing circuit. 1-1. Recording Format of Digital VTR FIG. 24 shows the recording format of the digital VTR on the tape. In this figure, margins are provided at both ends of the track. Inside the recording start end side, an ITI area for surely performing post-recording, an AUDIO area for recording audio signals, a VIDEO area for recording image signals, and an S for recording secondary data.
A UBCODE area is provided. An inter-block gap (I
BG) is provided.

Next, details of the signals recorded in the above areas will be described. (1) ITI Area As shown in the enlarged portion of FIG. 24, the ITI area has a 1400-bit preamble and an 1830-bit SSA (Start-Sync Block Area).
a), 90-bit TIA (Track Information)
(Area) and a 280-bit postamble.

Here, the preamble has a function such as a run-in of the PLL at the time of reproduction, and the postamble has a role of earning a margin. And SSA and TIA
The block data is composed of 30-bit block data, and the first 10 bits of each block data have a predetermined SY.
The NC pattern (ITI-SYNC) is recorded.

In the 20-bit portion following this SYNC pattern, the SYNC block number (0 to 60) is mainly recorded in SSA, and the 3-bit APT information (APT2 to APO) is mainly recorded in TIA. The SP / LP flag for identifying the recording mode and the PF flag indicating the reference frame of the servo system are recorded. In addition, A
PT is ID data that defines the data structure on the track, and takes the value "000" in the digital VTR of this embodiment.

As can be seen from the above description, since a large number of sync blocks having a short code length are recorded at fixed positions on the magnetic tape in the ITI area, the 61st SYNC pattern of SSA, for example, is reproduced from the reproduced data. By using the detected position as a reference for defining the post-recording position on the track, the position to be rewritten during post-recording can be defined with high accuracy, and good post-recording can be performed. The digital VTR of this embodiment is designed so that it can be easily applied to various other digital signal recording / reproducing apparatuses as described later, but in any digital signal recording / reproducing apparatus, a specific area can be used. Since it is necessary to rewrite the data, the ITI area on the track entrance side is always provided.

(2) AUDIO area The audio area has a preamble and a postamble before and after the audio area as shown in the enlarged portion of FIG. 24. The preamble is a run-up for pulling in the PLL.
And a pre-SYNC for pre-detection of the audio SYNC block. Also, the postamble is a post S for confirming the end of the audio area.
It is composed of YNC and a guard area for protecting the audio area during video data post-recording.

Here, the pre-SYNC and the post-SYNC are
25, each SYNC block is configured as shown in (1) and (2) of FIG. 25. The pre-SYNC is composed of two SYNC blocks, and the post SYNC is composed of one SYNC block. Then, the SP / LP identification byte is recorded at the 6th byte of the pre-SYNC. This is FF
When h represents SP and OOh represents LP, and when the SP / LP flag recorded in the above-mentioned ITI area is unreadable, the value of the SP / LP identification byte of this pre-SYNC is adopted.

The audio data recorded in the area sandwiched between the amble areas as described above is generated as follows. First, the audio signal for one track to be recorded is subjected to AD conversion and shuffling, then subjected to framing, and further parity is added. FIG. 26 shows a format in which parity is added by performing this framing.
(1) of. In this figure, 72 bytes of audio data is added with 5 bytes of audio accompanying data (this is called AAUX data) to form 1 block of 77 bytes of data, which is vertically stacked for 9 blocks for framing. Then, an 8-bit horizontal parity C1 and a vertical parity C2 corresponding to five blocks are added.

The data to which these parities are added is read out in units of blocks, and 3 bytes are added to the head side of each block.
A byte ID is added, and further, a 2-byte SYNC signal is inserted in the recording modulation circuit.
Is shaped into a signal of 1 SYNC block having a data length of 90 bytes as shown in FIG. Then, this signal is recorded on the tape.

(3) VIDEO area The video area has the same preamble and postamble as the audio area as shown in the enlarged portion of FIG. However, it is different from the audio area in that the guard area is formed longer. The video data sandwiched between these amble areas is generated as follows.

First, the video signals to be recorded are Y, RY,
After being separated into BY component signals, AD conversion is performed, and data of an effective scanning area for one frame is extracted from the AD converted output. This extracted data for one frame is Y when the video signal is a 525/60 system.
For the AD conversion output (DY) of the signal, the horizontal direction 72
It consists of 0 samples and 480 lines in the vertical direction.
AD conversion output (DR) of RY signal and A of BY signal
For D conversion output (DB), the horizontal direction is 18
It consists of 0 samples and 480 lines in the vertical direction. Then, these extracted data are divided into blocks of 8 samples in the horizontal direction and 8 lines in the vertical direction as shown in FIG. However, in the case of the color difference signal, the block at the right end portion of (2) in FIG. 27 has only 4 samples in the horizontal direction, and therefore, two blocks vertically adjacent to each other are combined into one block. By the above blocking processing, a total of 8100 blocks are formed for DY, DR, and DB per frame. A block composed of 8 samples in the horizontal direction and 8 lines in the vertical direction is called a DCT block.

Next, after the blocked data is shuffled according to a predetermined shuffling pattern, DCT conversion is performed in DCT block units, followed by quantization and variable length coding. Here, the quantization step is set for every 30 DCT blocks, and the value of this quantization step is set so that the total amount of output data obtained by quantizing and variable-length-coding 30 DCT blocks is equal to or less than a predetermined value. It That is, the video data is transferred to the DCT block 30.
Fixed length for each piece. The data for 30 DCT blocks is called a buffering unit.

The data fixed in length as described above is subjected to framing together with video accompanying data (this is referred to as VAUX data) for each data of one track, and then an error correction code is added. FIG. 28 shows a format in which this framing is applied and an error correction code is added.

In this figure, BUF0 to BUF26 each represent one buffering unit. Then, one buffering unit is (1) in FIG.
As shown in (1), it has a structure in which it is vertically divided into five blocks, and each block has a data amount of 77 bytes.
An area Q for storing parameters relating to quantization is provided in the first byte of each block.

Video data is stored in an area of 76 bytes following the quantized data. Then, as shown in FIG. 28, VAUX data α and β corresponding to two blocks in the above buffering unit are arranged above the buffering units arranged 27 in the vertical direction. At the same time, VAUX data γ corresponding to one block is arranged in the lower part, and an 8-byte horizontal parity C1 and a vertical parity C2 corresponding to 11 blocks are added to the framing data. To be done.

The signal to which the parity is added in this way is read in units of blocks, a 3-byte ID signal is added to the head side of each block, and a 2-byte SYNC signal is further inserted in the recording modulation circuit. It This allows
For the video data block, a signal of 1 SYNC block having a data amount of 90 bytes as shown in (2) of FIG. 29 is formed, and for the VAUX data block, 1 SYNC block as shown in (3) of FIG. The signal of the block is formed. The signal for each 1SYNC block is sequentially recorded on the tape.

In the framing format described above, 27 buffering units representing one track of video data have 810 DCT blocks of data, so one frame of data (8100 DCT blocks) is stored. The recording will be divided into 10 tracks.

(4) SUBCODE area The SUBCODE area is an area provided mainly for recording information for high speed search, and its enlarged view is shown in FIG.
It shows in 0. As shown in this figure, the SUBCODE area includes 12 SYNC blocks having a data length of 12 bytes, and a preamble and a postamble are provided before and after the SYNC block. However, unlike the audio area and the video area, pre-SYNC and post-SYNC are not provided. And, in each of the 12 SYNC blocks,
A data section for recording 5-byte accompanying data (AUX data) is provided. Also, as the parity for protecting the 5-byte accompanying data, only the 2-byte horizontal parity C1 is used, and the vertical parity is not used.

The AUDIO area described above,
Each SYNC block constituting the VIDEO area and the SUBCODE area is 24/25 in recording modulation.
Since the conversion (recording modulation method in which the data for every 24 bits of the recording signal is converted to 25 bits, the tracking control pilot frequency component is added to the recording code) is performed, the recording data amount of each area Figure 24
The number of bits is as shown in.

(5) Structure of ID part As is clear from the structure of each SYNC block shown in FIG. 25, FIG. 26, FIG. 29, and FIG.
UDIO area, VIDEO area, and SUBOCO
The SYNC block recorded in the DE area has ID0, ID1 and IDP (ID
3-byte I consisting of 0, parity that protects ID1)
The structure is common in that the D section is provided. Then, in the audio area and the video area, the data structure of ID0 and ID1 in the ID portion is determined as shown in FIG.

That is, the ID1 stores the in-track SYNC number from the audio area pre-SYNC to the video area post-SYNC in binary. And I
The track number in one frame is stored in the lower 4 bits of D0. The upper 4 bits of ID0 have AAU
SYNC of X + audio data and video data
In the block, 4 as shown in (1) of this figure
The bit sequence number is stored. On the other hand, in the pre-SYNC block, the post-SYNC block and the SYNC block of the parity C2 in the audio area, a 3-bit ID that defines the data structure of the audio area.
The data AP1 is stored, and the pre-S of the video area is stored.
3-bit ID data AP2 defining the data structure of the video area is stored in the YNC block, the post SYNC block, and the SYNC block of the parity C2 (see (2) in this figure). The values of AP1 and AP2 are "0" in the digital VTR of this embodiment.
00 ”.

The above sequence number is "000".
Twelve numbers from "0" to "1011" are recorded for each frame. By looking at this sequence number, it is possible to judge whether the data obtained during variable speed reproduction are within the same frame. On the other hand, SUBCOD
The structure of the ID part of the SYNC block in the E area is defined as shown in FIG.

This figure shows the structure of each ID part of the SYNC block numbers 0 to 11 for one track of the SUBCODE area, and the FR flag is provided in the most significant bit of ID0. This flag indicates whether or not it is the first 5 tracks of the frame, and takes a value of "0" in the first 5 tracks and "1" in the latter 5 tracks. The next 3 bits have S in the SYNC block whose SYNC block numbers are "0" and "6".
The ID data AP3 defining the data structure of the UBCODE area is recorded, and the SYNC block number “1” is recorded.
The ID data APT defining the data structure on the track is recorded in the SYNC block of "1", and the TAG code is recorded in the other SYNC block. The value of AP3 is the digital V of this embodiment.
In TR, "000" is taken.

Further, the TAG code is composed of three types of ID signals for search, as shown enlarged in FIG.
That is, it is composed of an INDEX ID for a conventional INDEX search, a SKIP ID for cutting unnecessary scenes such as commercials, and a PP ID (Photo / Picture ID) for a still image search. Also, the absolute number of the track (the continuous track number from the beginning of the tape) is recorded using the lower 4 bits of ID0 and the upper 4 bits of ID1. However,
As shown in this figure, one absolute track number is recorded by using a total of 24 bits for three SYNC blocks. The SYNC block number of the SUBCODE area is recorded in the lower 4 bits of ID1.

(6) MIC In the digital VTR of the present embodiment, the accompanying data is recorded in each area defined on the tape as described above, but the tape is stored outside this area. The circuit board provided with the memory IC is mounted on the cassette,
The accompanying data is also recorded in this memory IC. When the cassette is mounted on the digital VTR, the accompanying data written in the memory IC is read out to assist the operation / operation of the digital VTR (Japanese Patent Application No. 4-165444, Japanese Patent Application No. 4-165444). See Japanese Patent Application No. 4-287875). This memory IC is called MIC (Memory In Cassette) in the present application, and its data structure will be described in detail later.

(7) Structure and types of packs As described above, in the digital VTR of this embodiment, the audio area AAUX area and the video area VA area on the tape are used as areas for recording accompanying data.
The AUX data recording area of the UX area and the SUBCODE area is used, and the recording area of the MIC mounted on the tape cassette is used in addition to this. Each of these areas is configured in units of packs having a fixed length of 5 bytes.

Next, the structure and types of these packs will be described. The pack has a basic structure of 5 bytes shown in FIG. Of these 5 bytes, the first byte (PC0) is used as item data (also called a pack header) indicating the content of the data. Then, the format of the subsequent 4 bytes (PC1 to 4) is determined corresponding to this item data, and arbitrary data is provided according to this format.

This item data is divided into upper and lower 4 bits, and the upper 4 bits are called large items and the lower 4 bits are called small items. The large item of the upper 4 bits is, for example, data indicating the use of the subsequent data, and the pack is controlled by this large item as shown in the table of [1] of FIG.
"001", chapter "0010", part "001"
1 ”, program“ 0100 ”, voice auxiliary data (AA
UX) "0101", image auxiliary data (VAUX) "0"
110 ", camera" 0111 ", line" 1000 ",
It is developed into 10 types of groups of soft mode “1111”.

In this way, each group of packs expanded by the large item is expanded into 16 packs by each smaller item (which represents the concrete content of the subsequent data, for example). Up to 256 types of packs can be defined using these items. The large items “1001” to “1110” in the table [1] of FIG. 34 represent undefined portions left for addition. Therefore, by defining new item data (header) using a code of item data that has not been defined yet, it is possible to arbitrarily record new data in the future. Further, since the content of the data stored in the pack can be grasped by reading the header, the position on the tape for recording the pack can be set arbitrarily.

Next, a specific example of the pack will be described with reference to FIGS. 34 [2] and [3] and FIG. 35. The pack shown in [2] of FIG. 34 belongs to the AAUX group in the table of [1] of FIG.
It is called an E-pack and is used to record accompanying data regarding voice. That is, as shown in the figure, a flag (LF) indicating whether the audio sample frequency is locked with the video signal, the number of audio samples per frame (AF SIZE), the number of audio channels (C
H), information about modes such as stereo / monaural of each audio channel (PA and AUDIO MODE), information about television system (50/60 and STYP)
E), presence / absence of emphasis (EF), time constant of emphasis (TC), sampling frequency (SMP), and quantization information (QU) are recorded.

The sample frequency and the quantization information are specifically defined as follows. SMP: Sample frequency 000 = 48 KHz 001 = 44.1 KHz 010 = 32 KHz Other than the above = Reserve QU: Quantization bit number 000 = 16 bits 001 = 12 bits 010 = 20 bits 011 = 20 bits and 16 bits mixed mode Other than the above = Reserve

Further, the packs shown in [3] of FIG. 34 and [1] to [5] of FIG. 35 have VAUX in the table of [1] of FIG. It belongs to a group and is used to record incidental data about images. The recording contents of these packs will be described. In the VAUX SOURCE pack shown in [3] of FIG. 34, the channel number of the recording signal source and a flag (B / W) indicating whether the recording signal is a monochrome signal or not. , A code representing color framing (C
FL), a flag indicating whether or not CFL is valid (E
N), a code (SOURCE CODE) indicating whether the recording signal source is a camera / line / cable / tuner / soft tape, etc., data relating to a television signal system (50/60, and TYPE), UV
Data related to identification of broadcasting / satellite broadcasting (TUNER
CATEGORY) is recorded.

VAUX SO shown in [1] of FIG.
In the UR CONTROL pack, SCMS data (the upper bits represent the presence or absence of copyright, the lower bits represent the original tape), copy source data (representing whether it is an analog signal source, etc.), copy generation data, Cipher (encryption) type data (CP), cipher data (CI), a flag indicating whether or not a recording start frame (REC ST), recording mode data (REC MOD) such as original recording / after-recording / insert recording
E) is recorded, and data relating to the aspect ratio and the like (BCSYS and DISP), a flag (FF) relating to whether or not only the signal of one of the even-odd fields is repeatedly output twice, a field A flag (FS) regarding whether to output a field 1 signal or a field 2 signal during the period of 1, a flag (FC) regarding whether the image data of the frame is different from the image data of the previous frame (FC), interlace Flag (IL), whether the recorded image is a still image (ST), whether the recorded image is recorded in the still camera mode (SC), And the genre of the recorded content is recorded.

Further, VAUX shown in [2] of FIG.
Data relating to the recording date is recorded in the REC DATE pack, and the VAUX REC T shown in [3] of FIG.
Data regarding the recording time is recorded in the IME pack,
The binary group data of the time code is recorded in the BINARY GROUP pack shown in [4] of FIG. CLOSED CAP shown in [5] of the figure
Closed caption information transmitted during a vertical blanking period of a television signal is recorded in the TION pack.

As a special example of the pack, a pack having an item code of all 1 is a non-information pack (No I
nformation pack). As can be seen from the above description, in the digital VTR of this embodiment, since the structure of the accompanying data is the pack structure common to each area as described above, the software for recording and reproducing these data is common. And processing becomes easy. Further, since the timing at the time of recording / reproducing is constant, it is not necessary to provide an extra memory such as RAM for time adjustment, and the software can be easily developed in the case of developing a new model. be able to.

Further, by adopting the pack structure, for example, even when an error occurs during reproduction, the next pack can be easily taken out. Therefore, a large amount of data will not be destroyed due to error propagation or the like. When the text data is stored in the MIC described above, the structure of the pack is exceptionally recorded in one pack in order to save the use area of the storage area of the MIC having a small storage capacity. The structure is a variable-length pack that stores all text data.
The consumption amount of the storage area of C is saved.

(8) Structure of ancillary information recording area Next, a data area of an AAUX area, a VAUX area, a SUBCODE area where various kinds of ancillary data are recorded by using a pack, and recording of the MIC mounted on the tape cassette. A specific structure of the area will be described. AAUX area In the AAUX area, 1SY shown in (2) of FIG.
5 bytes AA in the NC block format
One pack is constructed in the UX area. Therefore, AA
The UX area consists of 9 packs per track. Since one frame of data is recorded in 10 tracks in the digital VTR of the 525/60 system, the AAUX area for one frame is represented as shown in FIG.

In this figure, one section represents one pack. And the numbers 50-55 entered in the section
Is the hexadecimal representation of the item code of the pack in that section (the number 50 in this figure is the A
AUX SOURCE pack), these six types of packs are called main packs, and the area in which these main packs are recorded is called the AAUX main area. Areas other than this are called AAUX optional areas, and an arbitrary pack can be selected and recorded from a wide variety of packs.

VAUX area For VAUX area, VAU in one track
As shown in FIG. 28, the X area is composed of three SYNC blocks α, β and γ, and the number of packs thereof is as shown in FIG.
15 per 1 SYNC block as shown in 7.
It becomes 45 in one track. The 2-byte area immediately before the error code C1 in the 1SYNC block is used as a preliminary recording area.

Regarding the VAUX area for one frame,
The pack structure is shown in FIG. In this figure, the packs to which the item codes 60 to 65 are displayed in hexadecimal notation are the VAs forming the VAUX main area.
It is a UX main pack, and is [5] of FIG. 34 and FIG.
The packs shown in [1] to [5] correspond to this. The other pack constitutes the VAUX optional area.

The data area of the SUBCODE area The data area of the SUBCODE area is as shown in FIG.
Five bytes are written in the C block, and each of them constitutes one pack. That is, 12 packs are recorded in one track, of which SYNC block numbers 3 to
The packs 5 and 9 to 11 form a main area, and the other packs form an optional area.

In this SUBCODE area, 1
Data for a frame is repeatedly recorded in a format as shown in FIG. In this figure, capital letters represent packs in the main area, and data necessary for high-speed search such as time code and recording date are recorded.
The lower case alphabets represent packs in the optional area, and any pack can be selected in this area to record any data.

Note that FIG. 39 shows the recording pattern in the case of the 525-60 system, but for reference, the recording pattern of one frame of SUBCODE data in the case of the 625/50 system is shown in FIG. As shown in this figure, in the case of the 625/50 system, one frame is composed of 12 tracks, and the SUBCODE in one track is 12 SYNC as in the case of the 525/60 system.
It is composed of blocks, and only the number of tracks is different.

It should be noted that the main area in each of the areas described above is characterized in that a pack storing ancillary information relating to basic data items common to all tapes is recorded. On the other hand, in the optional area, a soft tape maker or a user can freely write any accompanying data. Examples of such incidental information include various character information,
There are teletext signal data, television signal data of an arbitrary line within the vertical blanking period or effective scanning period, computer graphics data, and the like.

Recording Area of MIC FIG. 41 shows the data structure of the recording area of the MIC. This recording area is also divided into a main area and an optional area. The first 1 byte and unused area (FFh)
All are described in a pack structure except. As described above, only the text data is recorded in a variable-length pack structure, and other than that, it is recorded in the same 5-byte fixed-length pack structure as in the VAUX, AAUX, and SUBCODE areas.

At the head address 0 of the MIC main area, ID data A that defines the data structure of the MIC is written.
PM3 bit and BCID (Basic Cassette)
eID) 4 bits are recorded. Here, the value of APM is "000" in the digital VTR of this embodiment. BCID is a basic cassette ID, and
The contents are the same as the ID board for ID recognition (tape thickness, tape type, tape grade) in the C-less cassette. The ID board makes the MIC reading terminal have the same function as the recognition hole of the conventional 8 mm VTR, which eliminates the need to make a hole in the cassette half as in the conventional case.

"Cassette ID" in order from address 1 onward
A pack, a “tape length” pack, and a “title end” pack are recorded. Tape thickness information and memory information about the MIC are recorded in the "cassette ID" pack. The tape length of the cassette is recorded in the "tape length" pack by the tape manufacturer in terms of the number of tracks, and this data and the absolute track number indicating the final recording position stored in the next "title end" pack. Therefore, the remaining amount of tape can be calculated immediately. Further, this recording last position information provides a convenient usability when the reproduction is stopped by the camcorder and then the recording is returned to the original last recording position or when the timer is reserved.

The optional area is composed of optional events. Main area has addresses 0 to 1
The area up to 5 was a fixed area of 16 bytes, whereas the optional area is a variable area located after address 16. The length of the area changes depending on the content, and when the event is erased, the remaining events are packed and stored after address 16. FFh is written in all the data that is no longer needed after the stuffing work to make it an unused area. The optional area is literally an option, mainly TO
Tag information indicating C (Table of Contents) and points on the tape (for example, points for performing still reproduction), and text data such as titles related to programs are recorded.

At the time of reading the MIC, the next pack header appears every 5 bytes or every variable length byte (text data) depending on the contents of the pack header, but when FFh of the unused area is read as a header, Corresponds to the pack header of an information-free pack (NO INFO pack), so that the control microcomputer can detect that there is no information thereafter.

The optional area is composed of a common option and a maker option, and the common option contains, for example, text data. In the maker optional area, a "maker code" pack having a large item of soft mode "1111" and a small item of "0000" is provided, and subsequently, contents unique to each manufacturer are provided. When recording and writing to the optional area, the contents of the common options are recorded first,
After that, the manufacturer options are recorded.

Therefore, when this "maker code" pack is discriminated, it is discriminated that the contents have been made common before that and the contents peculiar to each manufacturer thereafter.
In addition, the contents of the common option or "maker code"
One or both of the pack-specific and manufacturer-specific contents may not exist.

1-2. Recording Circuit of Digital VTR In the digital VTR of this embodiment, recording on the tape and the MIC is performed according to the recording format described above. Next, the digital VTR for executing such recording.
The configuration and operation of the TR recording circuit will be described. The structure of such a recording circuit is shown in FIG.

In this figure, the input analog composite video signal is converted into Y, R by the Y / C separation circuit 41.
-Y, RY separated into each component signal, A /
It is supplied to the D converter 42. Further, the analog composite video signal is supplied to the sync separation circuit 44, and the sync signal separated here is supplied to the clock generator 45.
The clock generator 45 generates a clock signal for the A / D converter 42 and the blocking / shuffling circuit 43.

The component signal input to the A / D converter 42 is 1 when the Y signal is 525/60 system.
3.5 MHz, the color difference signal has a sampling frequency of 13.5 / 4 MHz, and in the case of the 625/50 system, Y
Signal is 13.5MHz, color difference signal is 13.5 / 2MHz
A / D conversion is performed at the sampling frequency of. Then, of these A / D converted outputs, only the data DY, DR, and DB in the effective scanning period are supplied to the blocking / shuffling circuit 43.

This blocking / shuffling circuit 43
, The effective data DY, DR, and DB are 8 in the horizontal direction.
Blocking processing is performed with the sample and 8 lines in the vertical direction as one block, and further 4 DY blocks,
After performing shuffling to increase the compression efficiency of image data in units of one block each of DR and DB and a total of six blocks, and to disperse errors during reproduction,
It is supplied to the compression encoding unit.

The compression / encoding unit performs D on the input block data of 8 samples in the horizontal direction and 8 lines in the vertical direction.
A compression circuit 46 that performs CT (discrete cosine transform), an estimator 48 that estimates whether the result can be compressed to a predetermined data amount, and a quantization step that is finally determined based on the determination result, and variable length encoding is performed. And a quantizer 47 that performs data compression using The output of the quantizer 47 is framed by the framing circuit 49 into the format described in FIG.

The mode processing microcomputer 67 in FIG.
Is a microcomputer that has a man-machine interface with humans and operates in synchronization with the frequency of vertical synchronization of television signals. The signal processing microcomputer 55 operates on the side closer to the machine, and the number of rotations of the drum is 9
It operates in synchronization with 000 rpm and 150 Hz.

Then, VAUX, AAUX, SUBCO
The pack data of each area of the DE is basically generated by the mode processing microcomputer, and the absolute track number included in the “title end” pack or the like is the signal processing microcomputer 5.
5 is generated, and the process of fitting it in a predetermined position is executed later. The time code data stored in the SUBCODE is also generated by the signal processing microcomputer 55.

These results are the result of the interface VAUX IC5 that links the microcomputer and the hardware.
6, IC57 for SUBCODE and IC58 for AAUX
Given to. The VAUX IC 56 synthesizes the output from the framing circuit 49 with the synthesizer 50 at a proper timing. In addition, the IC57 for SUBCODE is AP3, S
SID, which is the ID of UBCODE, and SUBCODE
To generate pack data SDATA.

On the other hand, the input audio signal is converted into a digital audio signal by the A / D converter 51. Although not shown in this figure, it is necessary to provide an LPF corresponding to the sampling frequency in the preceding stage of the sampling circuit when AD converting the video signal and the audio signal. The AD-converted audio data is subjected to data distribution processing by the shuffling circuit 52 and then framed in the framing circuit 53 into the format described in FIG. At this time AA
The UX IC 58 generates the AAUX pack data, checks the timing, and packs them in a predetermined location in the audio SYNC block in the synthesis circuit 54.

Next, a pack data recording circuit will be described by taking VAUX as an example. FIG. 43 shows the overall flow. First, the mode processing microcomputer 67 generates pack data to be stored in VAUX. It is converted into serial data by the P / S conversion circuit 118 and sent to the signal processing microcomputer 55 according to the communication protocol between the microcomputers. Here, the S / P conversion circuit 119 restores the parallel data and stores it in the buffer memory 123 via the switch 122. The header part at the beginning of every 5 bytes of the sent pack data is extracted by the pack header detection circuit 120, and it is checked whether or not the pack requires an absolute track number. If necessary, the switch 122 is switched to store 23-bit data from the absolute track number generation circuit 121 in 8-bit units. The storage area is the PC 1 of the pack to be stored as described in the individual pack structure,
This is a fixed position of PC2 and PC3.

Here, the circuit 119 is a serial I / O in the microcomputer, the circuits 120, 121 and 122 are constituted by a microcomputer program, and the circuit 123 is a RAM in the microcomputer. In this way, the processing of the pack structure uses a microcomputer which is advantageous in terms of cost because the processing time of the microcomputer is sufficient even if the processing is not made by hardware. The data thus stored in the buffer memory 123 is VA
Write side timing controller 12 of UX IC 56
It is read out one by one according to the instructions from 5. At this time, the switch 124 is switched so that the first six packs are for the main area and the subsequent 390 packs are for the optional area.

The FIFO 126 for the main area is 30 bytes, and the FIFO 127 for the optional area is 1950.
Bytes (525/60) or 2340 bytes (6
25/50) capacity. The VAUX is, as shown in [1] of FIG. 44, the SYNC number 19 in the track,
It is stored at 20, 156 places. When the track numbers in the frame are 1, 3, 5, 7, and 9, + azimuth is used for SY.
When the main area is in the first half of the NC number 19 and the track number in the frame is 0, 2, 4, 6, 8 -S in azimuth
There is a main area in the latter half of YNC number 156. This is collectively drawn in one video frame as shown in FIG. 44 [2]. In this way, the timing signal nMAIN =
When it is "L", it becomes the main area. Such a signal is generated by the read side timing controller 129, the switch 128 is switched, and the output is passed to the synthesis circuit 50.

Here, when nMAIN = “L”, the data in the main area FIFO 126 is repeatedly read 10 times (525/60) or 12 times (625/50). When nMAIN = “H”, the optional area FIFO 127 is read. This is 1
Read only once in a video frame. FIG. 45 mainly shows the pack data generation unit in the mode processing microcomputer. First, the circuit is roughly divided into a main area and an optional area. The circuit 131 is a main area data collection and generation circuit. The data as shown in the figure is received from the digital bus or the tuner and a data group as shown at 139 is internally generated. This is assembled into a bit-byte structure of the main pack, a pack header is added by the switch 132, and the pack header is input to the P / S conversion circuit 118 via the switch 136.

The optional area data collection / generation circuit 133 receives, for example, TELETEXT data, a program title, and the like from a tuner, and generates pack data in which these are stored. The VTR set individually decides which optional area to record. The pack header is set by the circuit 134 and added by the switch 135, and the P / S conversion circuit 1 is set through the switch 136.
38. The timing adjustment circuit 137 performs these timings. Again, circuit 1
Reference numeral 18 is a serial I / O in the microcomputer, and the circuits 131 to 137 are composed of a microcomputer program.

Further, in the generator 59 shown in FIG.
Each ID part of V (Audio / Video) and pre-SYN
C and post SYNC are generated. Here, AP1,
AP2 is also generated and fitted into a predetermined ID part. Output of generator 59, ADATA (AUDIO DATA), VDA
TA (VIDEO DATA), SID, SDATA
Are switched by the first switching circuit SW1 in view of the timing.

A predetermined parity is added to the output of the first switching circuit SW1 in the parity generation circuit 60, and the random number generation circuit 61 and the 24/25 conversion circuit 62 are added.
Is supplied to. Here, the randomizing circuit 61 randomizes the input data in order to eliminate the DC component of the data. Also, 2
The 4/25 conversion circuit 62 performs a process of adding one bit for every 24 bits of data to give a pilot signal component and a precoding process (partial response class IV) suitable for digital recording.

The data thus obtained is supplied to the combiner 63, where A / V SYNC and SUBCODE are supplied.
The audio, video and SUBCODE SYNC patterns generated by the SYNC generator 64 are combined.
The output of the combiner 63 is supplied to the second switching circuit SW2. The ITI data output from the ITI generator 65 and the amble pattern output from the amble pattern generator 66 are also supplied to the second switching circuit SW2.

The ITI generator 65 is supplied with data of APT, SP / LP and PF from the mode processing microcomputer 67. The ITI generator 65 inserts these data into a predetermined position of the TIA, and the second switching circuit SW2
Supply to. Therefore, by switching the switching circuit SW2 at a predetermined timing, the amble pattern and ITI data are added to the output of the combiner 63. The output of the second switching circuit SW2 is amplified by a recording amplifier (not shown), and a magnetic head (not shown).
Is recorded on a magnetic tape (not shown).

The mode processing microcomputer 67 is a digital VT.
Performs mode management for the entire R. The third switching circuit SW3 connected to this microcomputer is a switch group for instructing recording, reproduction, etc. by an external switch of the VTR main body. Among these, an SP / LP recording mode setting switch is also included. The setting result by the switch group is detected by the mode processing microcomputer 67 and is given to the signal processing microcomputer 55, the MIC microcomputer 69 and the mechanical control microcomputer (not shown) by communication between the microcomputers.

The above-described series of recording operations are performed mainly by the mode processing microcomputer 67 in cooperation with the mechanical control microcomputer or signal processing microcomputer 55 and the ICs in charge of each part.
The MIC microcomputer 69 is a MIC processing microcomputer. Here, pack data, APM, etc. in the MIC are generated and given to the MIC 68 in the MIC cassette (not shown) via the MIC contact (not shown).

1-3. Digital VTR Reproducing Circuit Next, the digital VTR reproducing circuit in this embodiment will be described with reference to FIGS. 46 and 47. In these figures, a weak signal reproduced from a magnetic tape (not shown) by a magnetic head (not shown) is amplified by a head amplifier (not shown), and the equalizer circuit 71
Added to. The equalizer circuit 71 performs reverse processing of the emphasis processing (for example, partial response class IV) performed to improve the electromagnetic conversion characteristics of the magnetic tape and the magnetic head during recording.

The clock CK is extracted from the output of the equalizer circuit 71 by the clock extraction circuit 72. This clock CK is supplied to the A / D converter 73, and the output of the equalizer circuit 71 is digitized. The 1-bit data thus obtained is written in the FIFO 74 using the clock CK. This clock CK is a temporally unstable signal containing a jitter component of the rotary head drum. However, since the data itself before A / D conversion also contains a jitter component, there is no problem in sampling itself. However, when extracting image data or the like from this point, the time axis adjustment is performed using the FIFO 74 because the data cannot be extracted unless the data is temporally stable. That is, writing is performed with an unstable clock, but reading is performed with a stable clock SCK from the self-excited oscillator 91 using a crystal oscillator or the like shown in FIG. FIFO7
The depth of 4 has a margin such that the data is not read faster than the input speed of the input data.

The output of each stage of the FIFO 74 is applied to the SYNC pattern detection circuit 75. Here, the SYNC pattern of each area is switched and given by the timing circuit 79 by the fifth switching circuit SW5. The SYNC pattern detection circuit 75 has a flywheel configuration, and once a SYNC pattern is detected, the same S pattern is re-established after a predetermined SYNC block length.
See if the YNC pattern comes. For example 3
It is configured so that it is regarded as true if it is correct more than once to prevent erroneous detection. The depth of the FIFO 74 is required for this several minutes.

When the SYNC pattern is detected in this way, the shift amount is determined which part of the output of each stage of the FIFO 74 should be extracted to obtain one SYNC block. SW4 is closed and the necessary bits are fetched into the SYNC block confirmation latch 77. As a result, the captured SY
The NC number is fetched by the SYNC number extraction circuit 78 and supplied to the timing circuit 79. This read S
Since the position on the track where the head is scanning is known from the YNC number, the fifth switching circuit SW5 and the sixth switching circuit SW6 are switched accordingly.

The sixth switching circuit SW6 is switched to the lower side when the head is scanning the ITI area, removes the ITISYNC pattern by the subtractor 80, and adds it to the ITI decoder 81. Since the ITI area is coded and recorded, each data of APT, SP / LP and PF can be taken out by decoding it. These data are given to the mode processing microcomputer 82 to which the seventh switching circuit SW7 for setting the SP / LP mode is connected. Mode processing microcomputer 8
Reference numeral 2 designates the operation mode of the digital VTR as a whole, such as the mechanical control microcomputer 85 and the signal processing microcomputer 10.
Cooperate with 0 to control the system of the entire set.

The mode processing microcomputer 82 is connected to the MIC microcomputer 83 that manages the APM and the like. MIC
Information from the MIC 84 in the attached cassette (not shown) is transferred to this MI via a MIC contact switch (not shown).
It is given to the C microcomputer 83 and performs processing of the MIC while sharing the role with the mode processing microcomputer 82. Depending on the set, the MIC microcomputer 83 may be omitted and the mode processing microcomputer 82 may perform MIC processing.

When the head is scanning the audio area, the video area, or the SUBCODE area, the sixth switching circuit SW6 is switched to the upper side. After the SYNC pattern of each area is extracted by the subtractor 86, it is passed through the 24/25 inverse conversion circuit 87, further added to the inverse randomization circuit 88, and returned to the original data string.
The data thus fetched is added to the error correction circuit 89.

The error correction circuit 89 uses the parity added on the recording side to detect and correct the error data, but the data that cannot be completely removed is ERROR.
Output with flags. Each data is switched and output by the eighth switching circuit SW8. AV
The ID, pre-SYNC, and post-SYNC extraction circuit 90
A / V area, SYNC number stored in pre-SYNC and post-SYNC, track number, and pre-S
Each SP / LP signal stored in the YNC is extracted. These are given to the timing circuit 79 and used for generating various timings. In the extraction circuit 90, AP1 and AP2 are also extracted and supplied to the mode processing microcomputer 82 for checking. AP
When 1, AP2 = 000, it operates normally, but when it is any other value, warning operation such as warning processing is performed.

Regarding SP / LP, the mode processing microcomputer 82 makes a comparative study with that obtained from ITI.
In the ITI area, there are 3 times SP / in the TIA area.
The LP information is written, and the reliability is increased by taking the majority vote etc. There are 2 SYNCs for each of the audio and video in the pre-SYNC, and SP / LP information is written at four locations in total. Here too, there is a majority vote to improve reliability. Finally, if they do not match, the ITI area is preferentially adopted.

VDATA output from the eighth switching circuit SW8 is divided into video data and video accompanying data by the ninth switching circuit SW9 shown in FIG. Then, the video data is given to the deframing circuit 94 together with the error flag. The deframing circuit 94 performs the inverse conversion of the framing on the recording side, and grasps the property of the data packed therein. Therefore, when there is an error that can not be caught in one data, I understand how it affects other data, so I will handle the propagation error here. As a result, the ERROR flag becomes a VERROR flag that newly includes a propagation error. The deframing circuit 94 also performs processing for removing error flags by modifying the image data if the data has an error but is not important for image reproduction.

The video data is returned to the data before compression through the dequantization circuit 95 and the decompression circuit 96. Next, the deshuffling / deblocking circuit 97 restores the data to the original image space arrangement. Only after the data is returned to this real image space, the image can be repaired based on the VERROR flag. That is, for example, the image data of one frame before is always stored in the memory, and the image block in error is substituted with the previous image data.

After the deshuffling, DY, DR,
Data is handled by dividing it into 3 systems of DB. Then, the D / A converters 101 to 103 restore the Y, RY, and BY analog components. The clock at this time uses the output of the oscillation circuit 91 and the output obtained by dividing the frequency by the frequency divider 92. That Y _{is, 13.5MH Z, R-Y,} B-Y 6.7
Is a 5MH _Z or 3.375MH _Z.

The three signal components thus obtained are Y /
The synthesis is performed in the C synthesis circuit 104, and is further performed by the synthesizer 10.
5, the composite sync signal from the sync signal generation circuit 93 is combined and the composite video signal is output from the terminal 106. Eighth switching circuit SW8
The ADATA output from is the tenth data shown in FIG.
The switching circuit SW10 divides the audio data into audio data and audio accompanying data. Then, the audio data is given to the deframing circuit 107 together with the ERROR flag.

The deframing circuit 107 performs the inverse conversion of the framing on the recording side, and grasps the property of the data packed therein. Therefore, when there is an error that can not be caught in one data, I understand how it affects other data, so I will handle the propagation error here. For example, at the time of 16-bit sampling, one data is in 8-bit units, so one E
The RROR flag is the AERR that newly contains the propagation error.
It becomes an OR flag.

The audio data is returned to the original time axis by the next deshuffling circuit 108. At this time, the audio data repair work is performed based on the AERROR flag. That is, a process such as a previous value hold that substitutes the sound immediately before the error is performed. The error period is too long,
If the repair is not effective, the sound itself is stopped by taking measures such as muting.

After such a treatment, the D / A converter 1
It is returned to the analog value by 09, and is output from the analog audio output terminal 110 while timing such as lip sync with the image data is taken. Now, each data of VAUX and AAUX separated by the ninth switching circuit SW9 and the tenth switching circuit SW10 is
IC for VAUX 98 and IC for AAUX 111, respectively
In the above, preprocessing such as majority processing is performed while also referring to the error flag.

The ID data SID of the SUBCODE area and the pack data SDATA output from the eighth switching circuit SW8 are the SUBCODE IC 11
2, the preprocessing such as the majority processing is performed while also referring to the error flag. The data that has been subjected to these pre-processing is then given to the signal processing microcomputer 100, and the final reading operation is performed. The errors that could not be removed in the pre-processing are VAUXE
It is given to the signal processing microcomputer 100 as R, SUBER, and AAUXER.

Here, the SUBCODE IC 112 is the AP
3 and APT are extracted and passed to the mode processing microcomputer 82 via the signal processing microcomputer 100 for checking. The mode processing microcomputer 82 uses the A from the ITI.
A based on PT and APT from SUBCODE
The value of PT is confirmed, and when the value is not "000", an operation such as a warning process is performed. Further, when AP3 = 000, the normal operation is performed, but when the value is other than that, warning operation such as warning processing is performed.

Here, supplementing the error processing of the pack data, each area has a main area and an optional area. In the case of the 525/60 system, the same data is written 10 times in the main area.
Therefore, even if some of them have an error, they can be supplemented and reproduced with other data, and the ERROR flag there is no longer an error. However, since the data is written once in the optional areas other than SUBCODE, the error remains as VAUXER and AAUXER.

The signal processing microcomputer 100 further performs propagation error processing, data repair processing, etc., by analogy with the context of each data pack. The result of this determination is given to the mode processing microcomputer 82 and used as a material for determining the behavior of the entire set. Next, take VAUX as an example.
A circuit for reproducing pack data in the IC 98 for processing and the signal processing microcomputer 100 will be described. Here, a configuration example using a simple processing method of not writing in the memory in the case of an error will be described as the preprocessing, not the majority processing. FIG. 48 shows a circuit example of the VAUX IC 98.
First, the VAUX pack data coming from the switching circuit SW9 is written by the write side controller 142 to n in FIG.
At the timing of MAIN = “L”, the switch 141 is switched to allocate to the main area memory 145 and the optional area FIFO 148.

The pack data in the main area is read by the pack header detection circuit 143 and the switch 144 is switched. Then, the data is written in the main area memory only when it is not ERROR. This memory has a 9-bit configuration, and the shaded portion in the figure is the storage bit of the error flag. As the initial setting of the memory for the main area, all the contents are set to 1 (= no information) for each video frame. And if it is ERROR, do nothing and ERRO
If it is not R, the data is written and 0 is written in the error flag. Since the same pack is written 10 or 12 times in one frame in the main area, the place where the error flag is set to 1 at the end of one video frame is finally recognized as an error.

Since the optional area is basically written once, the ERROR flag is written as it is in the optional area FIFO 148 together with the data. These are sent to the signal processing microcomputer 100 via the switches 146 and 147 which are switched by the read side timing controller 149. The signal processing microcomputer 100 analyzes the received pack data and the error flag.
The processing operation in the signal processing microcomputer 100 will be described with reference to FIG. In this figure, the pack header identification circuit 150 sorts the pack data (VAUXDT) sent from the VAUX IC 98 and stores it in the memory 151. This does not particularly distinguish between the main area and the optional area.

For packs in the main area, VAU
Similar to the X IC 98, the writing process is not performed when the error flag “1” is set in VAUXER. As a result, at least one video frame before can be repaired. Since it is considered that the content of the main area has a very strong correlation with the value one video frame before, there is no particular problem even if it is substituted by this processing.

On the other hand, in the case of the pack of the optional area, it is considered that there is no correlation with the value one video frame before, so the error propagation processing is performed in the pack unit.
This method is basically carried out by changing all the data to FFh if there is an error in the fixed-length pack data of 5 bytes, but it is also necessary to deal with individual packs. . For example, in the case of a "Telexext" pack in which Teletext data is stored,
Because of the number of consecutive packs, even if there is an error in the pack header between the packs, the pack can be easily replaced with the Teletxt pack header. Even if there is an error in the data part, if there is no error in the pack header, the pack will not be changed to the "pack without information".
This restores the Teletext data to the Tel
Since it is entrusted to the parity check of the etext decoder, the data is left as it is even if an error is found.

That is, in the digital VTR of this embodiment, although not shown in the reproducing circuit of FIG. 47, it has a large amount of data such as text data and Teletext data, and is a continuous data sequence. The characteristic pack data is transferred from the signal processing microcomputer 100 to a dedicated data processing circuit to perform error correction with higher efficiency and reduce the load on the mode processing microcomputer 82.

The data prepared by the processing in the signal processing microcomputer 100 as described above does not already have an error flag. These are converted into serial data by the P / S conversion circuit 152 and sent to the mode processing microcomputer 82 according to the communication protocol between the microcomputers. Where S / P
The conversion circuit 153 restores the parallel data and performs pack data decomposition analysis.

Here, the circuits 150 and 155 and the switch 154 are constituted by a program of a microcomputer, the memory 151 is a memory inside the microcomputer, and the circuits 152 and 153 are serial I / O inside the microcomputer. In the pack data decomposition analysis in the mode processing microcomputer 82, the pack data is analyzed based on the confirmed pack header, and various control information, display information, etc. obtained as the analysis result are respectively controlled circuits, display circuits, etc. Supply to.

The outline of the digital VTR of the present embodiment has been described above focusing on the case of the 525/60 system. However, the digital VTR of the present embodiment is not limited to this system but is of another SD (Standard Density) system. 625/50 system, and HD (High De
1125/60 system and 1
It is immediately applicable to the 250/50 system. Here, the data format in one track is common in all systems, and the only difference is the difference in the number of tracks constituting one frame. That is, one frame is composed of 12 tracks in the 625/50 system, 20 tracks in the 1125/60 system, and 24 tracks in the 1250/50 system, as described above.

2. Application ID System The outline of the digital VTR in the present embodiment has been described above. However, the digital VTR is not limited to a consumer digital VTR of the image compression recording system, and various other digital signal recording / reproducing devices can be easily developed. Basically designed so that you can. The ID data APT, AP appearing in the above description of the digital VTR
1 to AP3 and APM play a role of enabling expansion to such various digital signal recording devices, and these ID data are collectively referred to as an application ID.

Then, next, this application ID
A supplementary explanation of the system will be given. The above-mentioned application ID is not an ID for determining an application example of the digital VTR, but an ID for simply determining the data structure of the area of the recording medium, and the APT and APM have the following meanings as described above. APT: Determines the data structure on the track. APM ... Determines the data structure of the MIC.

That is, first, the value of APT defines the data structure on the track in this digital signal recording / reproducing apparatus. That is, the track after the ITI area is divided into several areas according to the value of the APT as shown in FIG.
The data structure such as the configuration is uniquely determined. Further, each area has an application ID that determines the data structure of the area. The meaning is as follows. Application ID of area n ... Determines the data structure of area n.

The application ID on the tape
Has a hierarchical structure as shown in FIG. That is, the area on the track is defined by the original application ID APT, and AP1 to AP1 are further added to each area.
APn is defined. The number of areas is defined by the APT. In FIG. 51, although written in two layers, a layer may be further provided below it if necessary. Thus APT,
By specifying the values of AP1 to APn, the specific signal processing configuration of the digital signal recording / reproducing apparatus and the use of the apparatus are specified.

The application ID in the MIC, APM, has only one layer, and its value is written by the digital signal recording / reproducing apparatus as the same value as the APT. With this application ID system,
Using a consumer digital VTR as it is with its cassette, mechanism, servo system, ITI area generation detection circuit, etc., a completely different product group such as a data streamer or a multi-track digital audio tape recorder is used. It is possible to create it. Also, even if one area is decided, its contents can be further defined by the application ID of that area.
A very wide range of product development is possible, such as when there is an application ID value, there is video data, and when there is another value, there is video / audio data, or computer data.

Next, a specific example when the value of the application ID is designated will be described. First, APT = 0
The state at 00 is shown in FIG. At this time, area 1, area 2, and area 3 are defined on the track. The positions on those tracks, the SYNC block structure, the ECC structure for protecting data from errors, the gap for guaranteeing each area, and the overwriting margin for guaranteeing overwriting are determined. Further, each area has an application ID that determines the data structure of the area. The meaning is as follows.

AP1 ... Determines the data structure of area 1. AP2 ... Determines the data structure of area 2. AP3 ... Determines the data structure of area 3. And the Application ID of each area
, 000 is defined as follows.

AP1 = 000 ... Image compression / recording system consumer digital VTR audio, AAUX data structure AP2 = 000 ... Image compression / recording system consumer digital VTR audio system, AAUX data structure AP3 = 000 ... Adopts the data structure of the subcode and ID of the image compression recording system consumer digital VTR. That is, when realizing the image compression recording system consumer digital VTR, APT, AP1, AP2, AP3 = 0.
It becomes 00. At this time, the APM is naturally 000.

2-1. Digital Television Broadcast Signal Recording / Reproducing Device Finally, a specific example in which the digital signal recording / reproducing device having the application ID system described above is developed as a digital television broadcast signal recording / reproducing device will be described. In the consumer digital VTR, which is an image compression recording system configured to helically record video data, which has been data-compressed by the DCT conversion, variable-length encoding, etc., as described above, the recording rate after compression of the video part is SD standard. The recording mode is about 25 Mbps, and the HD recording mode is about 50 Mbps. On the other hand, a high-efficiency coding method combining DCT conversion, variable-length coding, and motion compensation, compresses HDTV signals, and also compresses audio signals, and transmits all digital HDTV signals using terrestrial waves. Broadcast (hereinafter ATV (Adva
It is proposed that the TV is called "nended TV)". Various methods have been proposed for such an ATV signal, but the transmission rate is 2 at most including video and audio.
It is considered to be around 0 Mbps.

Therefore, in order to develop the digital VTR in this embodiment so that such an ATV broadcast can be recorded / reproduced, the value of the application ID (AP2) of the area 2 allocated as the video area is newly set to 000. It may be set to something other than the above, and recording / reproducing may be performed. In this case, the area of Audio or Subcode may be the same as before.

However, there is a possibility that some of the ATV signal systems have a transmission rate exceeding 25 Mbps. In this case, since the area 2 which is already allocated as the video area cannot be accommodated, the audio area 1 is also used. At this time, the value of APT is not changed, and the value of the application ID (AP1) of area 1 is newly set to a value other than 000 for use. The advantage of this system is that it is a digital VTR.
The point is that the circuit of the standard recording mode is used as it is and only the input signal is switched.

However, according to this method, data having the same property is protected by two different product code configurations, and there are various problems in reliability of image reproduction, capture at variable speed reproduction, and the like. . If this is unacceptable, set the APT to something other than 000 and change the track format itself. Then, a product code structure corresponding to the recording rate is newly designed to protect the data. Also in this case, if the position of the Subcode area in the standard recording mode is left unchanged, I
C and microcomputer software can be used as they are.

The above is summarized and shown in FIG. First, when recording / reproducing in the track format of APT = 000. Standard recording mode AP1 = 000, AP2 = 000, AP3 = 000 ATV recording mode (25 Mbps or less) AP1 = 000, AP2 = 001, AP3 = 000 ATV recording mode (when exceeding 25 Mbps) AP1 = 002, AP2 = 002, AP3 = 000 Next, when recording / reproducing by changing the APT. ATV recording mode AP1 = 000, AP2 = 000

ATV broadcasting is transmitted by a so-called packet structure. FIG. 54 shows an example. A service type is provided at the beginning of the packet. This is an ID indicating the attribute of this packet. For example, 00h is a video packet, 01h is an audio packet, and 02h is an AUX packet. This service type is followed by each piece of data, and parity is added to protect the data. As shown in FIG. 55, this packet is modulated in a mixed form and enters the radio wave.

Next, a concrete circuit example of the digital VTR for recording / reproducing this ATV broadcast will be described. Here, the digital VT shown in FIGS. 42, 46 and 47 is used.
A circuit coexisting with the R recording / reproducing circuit will be described. In the case of a VTR having only an ATV, it suffices to delete a portion relating only to recording and reproduction of a normal television signal. Figure 56 ATV
The recording side circuit of the VTR and the reproducing side circuit are shown in FIG. Incidentally, the blocks of the recording circuit and the reproducing circuit of the digital VTR shown in FIGS. 42, 46, and 47 shown in these figures are deeply related in the connection with the ATV tuner section. Only the part is shown, and the structure of other parts is omitted.

First, the recording side circuit of FIG. 56 will be described. In this example, APT = 000 is recorded in area 2.
It is a coexistence circuit with a rate of 25 Mbps or less. In FIG. 56, a desired channel of the ATV radio wave signal captured by the ATV antenna A1 is selected by the ATV receiving circuit A2. This is extracted by the ATV demodulation unit A3 in packet units as shown in FIG. This is the error correction circuit A
In step 4, error detection and correction are performed.

The service type is extracted from the decided packet data, and the switch A6 is switched based on this information. The switches A13a, A13b, A13c are switched to the upper side during recording. In the case of AUX packets, the switch A6 switches to the upper side, and in the case of video / audio packets, it switches to the lower side. AUX packet is AUX
It is decoded in the decoder A8. At this time, the error ATVER that could not be removed by the error correction circuit A4 is
It is reflected in this decoder. In the case of a video / audio packet, it is further switched by the switch A7 and decoded by the video decoder A9 and the audio decoder A10. At this time also, error countermeasures are taken based on the ATV rules. This decoded output is sent to the monitor TV and reproduced as a received audio image.

When recording the above ATV signal in the digital VTR, it is efficient to record and reproduce without decoding both video and audio, and the image quality is excellent. . Incidentally, in this case, by inputting the packet to the recording system of the digital VTR after passing through the ATV packet error correction section A4, the error occurring in the transmission system of the ATV broadcast is corrected in advance.

The recording buffer circuit A11 is for adjusting the timing when performing the framing operation. No error ATVER is input here. Video / audio packet data is recorded / reproduced with errors other than correctable errors. The processing is entrusted to the video / audio coders A9 and A10 of the ATV tuner unit which are finally input during reproduction. Switch A12
Is switched by the mode processing microcomputer 67 when the input to the synthesizer 50 is switched.
It is on the upper side when recording V.

The output of the AUX decoder A8 is applied to the signal processing microcomputer 55, and V output defined by APT = 000 is applied.
It is edited and recorded with a pack structure in the AUX area. At this time, the VAUX IC 56 works to store the ATV AUX, and the value of AP2 in the circuit 59 is set to 001 as in the example of FIG. Audio to area 1 in Figure 53
When recording video in area 2, the timing is adjusted through the buffer circuits from the latter stage of the switch A7 in FIG. 56 and then input to the audio / video framing circuit. If the rate exceeds 25 Mbps, a new dedicated error correction code circuit is required. The output is switched by a switch and input to a channel coder to generate a recording code.

Next, the reproducing side circuit of FIG. 57 will be described. The tape is reproduced, and the mode processing microcomputer 82 receives the APT information from the ITI channel decoder. By judging this, it is judged which type of recording in FIG. Here, a coexistence circuit for recording in area 2 with APT = 000 and having a rate of 25 Mbps or less is shown. Playback mode, so switches A13a, A13b, A13c
Is switching to the bottom.

The data corrected by the error correction circuit 89 is switched by the eighth switching circuit SW8, and the data in area 2 is input to the ninth switching circuit SW9 as VDATA. Here, it is divided into video data and VAUX data. The circuit 90 is the AV ID extracted by the eighth switching circuit SW8.
From these, AP1 and AP2 are extracted. These are transmitted to the mode processing microcomputer 82. Here, when AP2 = 001, since ATV data is contained in area 2, the circuit operation after the deframing circuit 94 for the standard recording mode is stopped.

After that, the output of the reproduction buffer circuit A14, which has stored the data of area 2, becomes active for a period of time until the detection of AP2 is determined in advance. Data of a SYNC block dedicated to video data and an ERROR flag for the data are stored here. The data of the reproduction buffer circuit A14 is also added to the service type extraction circuit A5, and it is judged here whether it is an audio packet or a video packet. Thereby, the switch A7 is switched. Whether the service type extraction circuit A5 judges the packet from A4 or the packet from A14 depends on the instruction from the mode processing microcomputer 82.

Video coder A9, audio coder A1
In addition to the respective packet data, error data generated during reproduction is input to 0. First, based on this, each decoder determines where and how the error affects, and performs propagation error processing. After that, an error that cannot be completely removed due to an error that occurred when it was transmitted as a radio wave at the time of recording is detected by using the parity of FIG. The above error data is processed based on the ATV processing rule. In this way, each video / audio data is restored.

Here, there is no AUX packet that originally existed. This is because the contents are disassembled at the time of recording and are edited again as a pack structure in the VAUX area and then recorded on the tape. At the time of reproduction, since the contents are read and processed, there is no need to reassemble them into an AUX packet. When audio is recorded in area 1 in FIG. 53 and video is recorded in area 2, the timing is adjusted through the reproduction buffer circuit and input after the switch A7 in FIG. 57. When the rate exceeds 25 Mbps, a new dedicated error correction code circuit is provided and its output is input to the reproduction buffer circuit A14.

3. Recording / Reproduction of Audio Data Next, recording / reproduction of audio data, which is a problem of the present application, will be described in detail. In the digital VTR of this embodiment, as described above, the audio recording mode is 16-bit mode: 48 KHz, 44.1 KHz, 32.
KHz 12-bit mode: 32 KHz is prepared.

The digital VTR shown in FIG.
As shown in 6, the audio data storage area can store 9 SYNC blocks per track, that is, 72 bytes x 9 = 648 bytes. From this, audio data for one channel in 16-bit mode per one frame period can be stored. When the number of tracks required for recording is calculated, it is 5 tracks in the 525/60 system and 6 tracks in the 625/50 system. In the case of 12-bit mode audio data, audio data for two channels can be recorded with the same number of tracks.

The 1125/60 system or 1
In the case of the 250/50 system, the number of tracks per frame is doubled as compared with the case of the 525/60 system or the 625/50 system, and therefore doubled if the same sampling frequency and the number of quantization bits are used. Audio channels can be provided.

Since the 12-bit mode is a subset of the 16-bit mode and the sound quality is not suitable for business use, in the following description, a digital VTR equipped with a 16-bit mode voice recording circuit will be referred to as a 20-bit mode. This section describes an example of the configuration when it is developed so that it can record audio. First, the recording of audio data in the 16-bit mode in the digital VTR will be described, and next,
A case where the digital VTR is developed for commercial use so that 20-bit voice can be recorded will be described.

3-1. 16-bit mode recording [1] of FIG. 58 is a schematic diagram of an audio track in a digital VTR for the 1125/60 system, of which the figure shows the audio track in the 16-bit mode. In this figure, one rectangle represents 5 tracks, which constitutes one audio channel. Since there are 20 tracks for one video frame, four channels can be recorded.

In the 12-bit mode shown in the figure, since 2 channels are included in 5 tracks, there are a total of 8 channels. 525/60 shown in [2] of FIG.
In the case of the system, the number of channels is halved. Next, the 1125/60 system and the 1250/50
FIG. 59 shows a shuffling pattern formula when voice recording is performed in the 16-bit mode in the system. This figure shows the position (that is, the track number, the SYNC block number, and the byte position number in the SYNC block) on the tape where the nth sample data of the audio signal is recorded.

In particular, in the equation [1] representing the track number, the calculation of mod5 in the 1125/60 system is
Also, as is clear from the calculation of mod6 in the 1250/50 system, the audio data of channel 1 in the 1125/60 system is track numbers 0 to 4.
The channel 2 audio data is track numbers 5-9.
The audio data of channel 3 is track numbers 10 to 1
4, the audio data of channel 4 is track number 15-
The audio data of channel 1 is recorded in track numbers 0 to 5 in the 1250/50 system.
The audio data of channel 2 is track numbers 6-11.
The audio data of channel 3 is track numbers 12 to 1
7, the audio data of channel 4 is track number 18-
It can be seen that each is recorded in 23.

Looking at the equation [3], the upper 8 bits and the lower 8 bits of the 16-bit audio data are the same SYN.
It can be seen that the data is recorded at the adjacent byte position in the C block. In addition, SD system 525/60 system and 62
In the 5/50 system, only the recording positions of channel 1 and channel 2 in this figure are used for recording. Further, the maximum value of the sample number n changes according to the sampling frequency as described in the lower part of this figure.

The actual shuffling pattern for the 525/60 system determined by the shuffling pattern formula of FIG. 59 is shown in FIG. In this figure, the value of j marked at the top is the byte position number 10 in which audio data is recorded in one SYNC block.
81, and the value of i written in the left part of this figure represents 9 SYNC block numbers 2 to 10 in each track 0 to 9 (note that SYNC block numbers 0 and 1 are pre-SYNC numbers). Is the block number).

As described above, the audio data of channel 1 is recorded on tracks 0 to 4, and the audio data of channel 2 is recorded on tracks 5 to 9. Also,
16-bit audio data is recorded by using adjacent bytes in the SYNC block. For example, in this figure, audio data D1 of sample number 15 of channel 1 is recorded.
5 is the SYNC block number 3 in the track number 0
It is shown to be recorded at byte positions 10 and 11 of. In this figure, the track numbers in parentheses indicate shuffling patterns in tracks 10 to 19 in the case of the 1125/60 system.

Similarly, 625/50 system and 1
The shuffling pattern for the 250/50 system is shown in FIG. When performing the 16-bit mode recording as described above, the value of the QU code in the AAUX SOURCE pack recorded as the accompanying data is
Set to "000" as indicated in the definition above.

3-2. 20-bit mode recording Next, a description will be given of a configuration example in which the above-described digital VTR for performing voice recording in the 16-bit mode is expanded to a business-use digital VTR capable of performing voice recording in the 20-bit mode.

A schematic diagram of an audio track in such a configuration example is shown in FIG. In this figure, [1] is 1125 /
It is a schematic diagram in the case of a 60 system, and as shown here, the upper 16 bits of each audio data of channels 1 to 3 are in the same track, SYNC block, and byte position as in the case of recording in the above 16 bit mode. Make a record. Then, the lower 4 bits of each channel are recorded in the track, the SYNC block, and the byte position where the audio data of the channel 4 in the 16-bit mode is recorded. Therefore, in this case, the number of recorded audio channels is three. When audio recording is performed in this mode, the value of the QU code in the AAUX SOURCE pack recorded as the accompanying data is set to "010".

The manner in which audio data is actually recorded in the SYNC block of each track will be described with reference to FIG. This figure shows the state of the audio data recorded in the first SYNC block (SYNC block number i = 2) of the track in which the upper 16 bits and the lower 4 bits of each audio data of channels 1 to 3 are recorded first. As shown in the figure, the audio data D0 to D1575 shown in FIG. 60 are recorded in each SYNC block.

Here, the bit component from MSB to LSB of 20-bit audio data of channels 1 to 3 is b1.
9, b18, ..., b0, the upper 16 bits b19 to b4 are tracks 0, 5, 10 as shown in the figure.
Are recorded in the predetermined two byte positions of the above, and the lower 4 bits b3 to b0 are the audio data of the channel 4 in the 16-bit mode as shown in the enlarged view at the bottom of this figure. Is recorded using all the bits of the first byte and the upper 4 bits of the second byte of the recording position of the track 15 on which is recorded. "1111" is set as dummy data in the lower 4 bits of the second byte.
To record.

The reason for setting the value of the dummy data in this way is as follows. That is, a consumer-use digital VTR that records audio in the 16-bit mode described above.
Then, as shown in the reproducing circuit of FIG. 12 described later, the error code "10000000000000" is set to the data of the portion in which the error occurs in the reproduction of the audio data.
00 ”(8000h in hexadecimal notation) before performing error processing. Even in audio recording in the 20-bit mode as shown in FIG. 2, in audio processing in each channel of the reproduction system, In particular, even in the audio processing in the channel in which the lower 4-bit audio data is recorded, it is possible to perform the error processing by the above replacement with 8000h.

That is, in this figure, channels 1 to 1
It is obvious that the above replacement process can be performed for the error portion generated in 3), but the lower 4
For the bit channel, for example, when the value of the dummy data is “0000”, the value of the code composed of two bytes is set even if no error occurs in the data of the three lower four bits. Since there is a sufficient possibility that it will be 8000h, there is a possibility that error processing will be performed on a portion that is not originally an error, by determining this as an error occurrence portion. Therefore, in the present embodiment, the value "1111" that is unlikely to cause confusion with such an error code is used as dummy data.

As the value of the dummy data,
Any code other than "1111" may be used as long as it can be completely distinguished from the error code 8000h.
800 due to an error in the dummy data itself
Considering that 0h may appear,
"1111", which has the lowest possibility, is the optimum dummy data.

In the recording of the lower 4 bits shown in this figure, the data of channel 1 is recorded in the upper 4 bits of the first byte, and the data of the channel 3 is recorded in the lower 4 bits of this byte. The data of the channel 2 is recorded in the upper 4 bits of the second byte, but the arrangement is not limited to such a recording arrangement, for example, the recording position of the data of the channel 2 and the recording position of the data of the channel 3 And may be exchanged. However, it is desirable to record data of two particularly important audio channels (for example, R audio and L audio) at different byte positions.

That is, by making the recorded byte positions different from each other, even if an error occurs in one byte, the audio data recorded in the other byte can be reproduced, and audio of two important channels is reproduced. This is because the possibility that both are damaged is significantly reduced. Of course,
In this case, it is necessary to configure the system so that the process of replacing the error part with 8000h is not performed for the lower 4 bits channel. Also,
Propagation error processing (processing of converting error information in byte units into error information in units of audio data (for example, in units of 2 bytes)), which will be described later, which is performed in the normal deframing circuit of the reproduction system, is also performed for the channels of the lower 4 bits. It is necessary not to do it.

Note that FIG. 1 [2] is a diagram showing 20-bit mode recording in the case of the 525/60 system. In the channel in which the lower 4 bits are recorded, the lower 4 bits of the audio data and the dummy data are recorded. 12-bit all-one data is recorded in each 2-byte recording area. Then, only 20-bit audio data for one channel is recorded.

FIG. 3 shows a shuffling pattern formula for realizing the recording mode of the 20-bit audio shown in [1] of FIG. As can be seen by comparing the shuffling pattern expression shown in this figure with the shuffling pattern expression in the case of the 1125/60 system shown in FIG. 59, the upper 16 bits of the audio data of channels 1 to 3 are 16 bits. This is the same as the shuffling pattern formula used for the data of channels 1 to 3 in the case of recording in the mode, and the 2-byte area in which the data of the lower 4 bits of each channel is recorded is recorded in the 16-bit mode. The same shuffling pattern as the data of channel 4 in the case is given. However, the recording position of each 4-bit data in this 2-byte area is unique to this configuration example as described above.

Next, with respect to the tape of 20-bit mode audio recorded in this way, the compatibility at the time of reproduction between the commercial digital VTR and the consumer digital VTR will be described. The sampling frequency and the number of quantization bits of the audio data in the tape reproduced by the digital VTR are recorded in AAUX which is the main pack of the AAUX area.
The determination can be made immediately from the data stored in the SOURCE pack, and both the consumer digital VTR and the business digital VTR in the embodiment of the present invention are set to be suitable for the processing of the audio reproduction system based on the result of this determination. Is configured to.

FIG. 4 is a schematic diagram of a case where a tape recorded in 20-bit mode audio by a commercial digital VTR in the case of the 1125/60 system is reproduced by a consumer digital VTR. Consumer digital VTR
In the playback system by the mode processing microcomputer described above.
The QU value in the AUX SOURCE pack is read to recognize that it is 20-bit mode audio, and based on this, the audio data of channels 1 to 3 is reproduced as 16-bit audio, and the lower 4-bit data is processed. The processing operation is stopped for the channel. In this case, since only the lower 4 bits of the audio data of the channels 1 to 3 are truncated, no adverse effect is caused, and the reproduced data from the channel in which the lower 4 bits of data are recorded is not affected. Since the processing is stopped, the lower 4 bits of data will not be emitted as noise.

In addition, 1 is set by the consumer digital VTR.
When a tape recorded in 6-bit mode audio is played back by a digital VTR for professional use, a playback-system mode processing microcomputer recognizes that it is 16-bit mode audio. The audio data is set to the upper level of the 20-bit DA conversion circuit provided in each channel, and the dummy data is set to the lower 4 bits of each DA conversion circuit to extract the analog audio.

In FIG. 5, a tape recorded by a commercial digital VTR is further partially post-recorded by a consumer digital VTR. Particularly, a recording mode of audio data is recorded in the first half and the second half of one frame. 3 shows a reproducing operation for a tape portion in which the number is different. In this figure, the part surrounded by the dotted line is
The reproducing operation by the consumer digital VTR is shown, and the portion surrounded by the dotted line shows the reproducing operation by the commercial digital VTR.

As shown in the figure, when the tape recorded on the first half of the consumer digital VTR is reproduced by the consumer digital VTR, the audio of the latter half channel of this frame is in the 20-bit mode. It is determined by the mode processing microcomputer that the data is recorded in the above, and the audio processing circuit of the channel 4 is stopped based on this to mute the audio of the channel, and the audio data of the channels 1 to 3 is as usual. At 16
It processes as bit voice data and reproduces voice.

Further, the above tape is used as a commercial digital V
When playing back in TR, the mode processing microcomputer recognizes that it is a tape portion in which such recording modes are mixed, and regards all audio data of channels 1 to 3 as 16-bit mode data. The lower 4 bits of dummy data is added to the audio data of No. 1 and reproduced, or the audio data of channels 1 and 2 is added with the lower 4 bits of dummy data as 16-bit mode audio and reproduced. Then, regarding the audio data of the channel 3, the lower 4 bits of the audio of the channel 3 extracted from the channel in which the lower 4 bits of data are recorded are added and reproduced as the audio data of the 20-bit mode. Here, a commercial digital VTR
Which reproduction operation is to be executed is designed by designing the mode processing microcomputer and the processing circuit so that the desired operation is realized in each set.

When reproducing the tape portion recorded in the latter half by the consumer digital VTR, the reproduction VT
When R is a consumer digital VTR, the audio data of channels 1 to 4 are all reproduced as audio data in the 16-bit mode as shown in. When the playback VTR is a digital VTR for business use, all the audio data of channels 1 to 3 are regarded as 16-bit mode audio data as shown in (3), and the lower 4 bits of dummy data are added to each of them for reproduction. The operation of the audio data processing circuit of the lower 4-bit channel is stopped.

As described above, even if the tape recorded in any mode is loaded in any digital VTR, the sound can be reproduced and the compatibility is established. The above is
This is a description of 20-bit mode audio recording for the 1125/60 system.
FIG. 6 shows a shuffling pattern formula used for 20-bit mode voice recording in the case of the system. Also in this case,
As is clear from comparison with the shuffling pattern formula for the 1250/50 system in FIG. 59, 1125/60 is obtained in 16-bit mode recording and 20-bit mode recording.
The same relationship as for the system holds.

3-3. 20-bit and 16-bit mixed mode recording Next, a voice recording of a professional-use digital VTR configured to record 20-bit audio and 16-bit audio simultaneously (hereinafter, this audio recording mode is referred to as mixed-mode recording).
Will be described. In this mixed mode recording, the value of the QU code in the AAUX SOURCE pack recorded on the tape is set to "011", and for the audio of channels 1 and 2, the recording of 20 bit mode is recorded in the channel 3 of the channel 3. For audio, 16-bit mode recording is performed.

1125 / adopting this mixed mode recording
Professional Digital VTR and 1250 for 60 Systems
FIG. 7 shows a schematic diagram of an audio track in a digital VTR for business use for the / 50 system. FIG. 8 shows the structure of the SYNC block in which the audio data of each track in the professional digital VTR for 1125/60 system using this mixed mode recording is recorded. As you can see from this figure, the fourth channel of the recording track
The lower 4 bits of the audio data of channels 1 and 2 are repeatedly recorded. The shuffling pattern formula is 1
In case of 125/60 system, according to FIG.
The case of the / 50 system is represented by FIG.

When the mixed mode recording is adopted, there is an advantage that voice dubbing is easy to be performed.
That is, for example, when high-quality stereo R and L audios are recorded in 20-bit mode as channel 1 and 2 audios and narration is recorded in 16-bit mode as channel 3 audio, usually the narration is post-recorded. However, since the narration is recorded using only one channel in this mixed mode recording, rewriting by post-recording can be easily executed.

On the other hand, when the narration is recorded as the 20-bit audio data of the channel 3 by using the 20-bit mode recording described above, when rewriting only the narration data, the channel 4 of the recording track is recorded. It is also necessary to rewrite the lower 4 bits of the recorded narration data. Therefore, the lower 4 bit components of the audio data of the other channel are also recorded in this channel 4. So in this case,
The lower 4-bit data of channel 4 is read in advance by the read-ahead head and stored in the memory. After that, when performing post-recording of the upper 16 bits of channel 3, among the lower 4-bit components stored in the memory. The complicated operation of rewriting only the lower 4 bits of the narration and dubbing to channel 4 is required, and the cost increase due to the mounting of the pre-reading head cannot be avoided.

Regarding the compatibility between the consumer digital VTR and the commercial digital VTR adopting the mixed mode recording, the same compatibility as in the case of the 20-bit mode recording described in FIGS. 4 and 5 is established. To do. However,
In FIG. 5, in the operation of reproducing the tape recorded in the first half of the consumer VTR by the commercial VTR, CH
All the audios of 1 to 3 are reproduced as 16-bit audio (CH1 and CH2 are 16-bit audio, and C
It is not possible to perform the operation of reproducing H3 as 20-bit audio).

3-4. Audio Data Processing Circuit Next, a specific circuit configuration for audio data processing in each of the consumer and commercial digital VTRs described above will be described.

(1) Consumer digital VTR a. Voice data recording circuit Fig. 11 shows a consumer digital V of the 1125/60 system.
The main part of the circuit for recording 16-bit mode audio in TR is shown. In this figure, each analog audio signal of channels 1 to 4 is AD-converted by AD converter circuits 1 to 4.
After being converted, they are supplied to the shuffling circuits 5 to 8 respectively (note that the internal configuration of the shuffling circuits 6 to 8 is
Since the internal structure of the shuffling circuit 5 is the same, the description is omitted in this figure).

The audio data of channel 1 supplied to the shuffling circuit 5 is transferred to the FIFO memory 16 for time adjustment.
And is input to the pair of shuffling memories 10 and 11. Here, the write control circuit 15 calculates the address in the shuffling memory where the audio data should be stored from the sample number n of the audio data based on the above-mentioned shuffling pattern formula, and the write address having this write address is calculated. The control signal is supplied to the shuffling circuit 5. This write control signal is alternately supplied to the shuffling memories 10 and 11 for each frame via the switch S1, and the audio data from the FIFO memory 16 is alternately written to the shuffling memories 10 and 11 for each frame. .

The read control circuit 13 generates a read control signal for reading audio data from the shuffling memory, and this read control signal is supplied to the channels during the timing period corresponding to tracks 0 to 4 by the switching operation of the switch 12. 1 to the shuffling circuit 5 of channel 1, to the shuffling circuit 6 of channel 2 in the timing period corresponding to tracks 5 to 9, and to the shuffling circuit 7 of channel 3 in the timing period corresponding to tracks 10 to 14.
To the shuffling circuit 8 of the channel 4 in the timing period corresponding to the tracks 15 to 19, respectively.

By reading the audio data from the shuffling memory in the order of addresses by this read control signal, the shuffled audio data is taken out to the output side of the shuffling circuit. In reading from the shuffling memory, the switching state of the switch S2 is controlled so that the shuffling memory in which the writing operation is not performed is always read. The output of each shuffling circuit is supplied to the framing circuit 53 in FIG. 42 via the switch 9, and is further subjected to processing such as AAUX data addition and parity addition.

B. Audio Data Reproducing Circuit Next, the main part of the 16-bit mode audio reproducing circuit in the consumer digital VTR of the 1125/60 system will be described with reference to FIG. In this figure, the ERROR flag from the error correction circuit 89 and the audio data from the switching circuit SW10 are input to the deframing circuit 107 as shown in FIGS. Then, the audio data is supplied from the deframing circuit 107 to the switch 22. Here, the audio data is switched according to the track number by the switching control signal from the switching control circuit 17, whereby the channels 1 to 1 are switched.
The audio data No. 4 is input to the deshuffling circuits 23 to 26 for each channel.

On the other hand, the ERROR flag input to the deframing circuit 107 is subjected to propagation error processing here and converted into an AERROR signal. This propagation error processing is an operation of converting the error information (ERROR) in byte units generated in the error correction circuit 89 into an error in audio data units of 2 bytes.
When there is no error in the first byte of the 2-byte audio data input to the deframing circuit and only the second byte has the ERROR flag set, the operation of setting the ERROR flag in the first byte is also performed. .

The AERROR signal formed by this propagation error processing is input to the switch 21, where it is switched in conjunction with the switch 22 and distributed to the deshuffling circuits 23 to 26 for each channel.
Further, the error code generation circuit 20 generates the above-mentioned error code 8000h (ec), and this error code is also input to each deshuffling circuit.

The audio data of the channel 1 supplied to the deshuffling circuit 23 is input to the pair of deshuffling memories 27 and 28 via the switch S3. When an error occurs in the audio data here, , The movable terminal of the switch S3 is tilted upward, so that the error code ec is input to the deshuffling memory instead of the input audio data. The switch S3 is switched based on the discrimination result of the error discrimination circuit 29 for discriminating the content of the AERROR signal (1) input to the deshuffling circuit.

The circuit for propagation error processing described above is configured, for example, as a circuit 315 shown in FIG. In this circuit, the D flip-flop 31
4, 313 and the OR gate 312 constitute a circuit for generating the AERROR signal, and the D flip-flop 3
10 and 311 indicate the timing of audio data by AERR.
A delay circuit for adjusting the timing of the OR signal is configured. The operation of this circuit 315 will be described with reference to FIG.

The signal (2) in FIG. 14 represents the audio data input to the D flip-flop 310, and d1
1, d12, d13, ... are SYN of AUDIO
Each byte position number in C block is 1
1, 12, 13, ..., 8 bits of audio data are represented (that is, d10 and d11, d12 and d1).
3, d14 and d15, ... Compose 16-bit audio data for one sample each. If an error occurs at the positions of d11, d16, d20, and d21 as shown in (3) of this figure, the OR gate 312 that adds this error signal and its 1-clock delay output. Is output as shown in (5) of FIG.

Next, the output of this OR gate is input to the D flip-flop 313, and this 313 is further input to the second byte of each 16-bit audio data in the input data of (2) as shown in (6). Stand up at the trailing edge 1 /
By driving with a clock having a frequency of 2, as shown in (7) as the output of 313, at least one of the two byte positions of 16-bit audio data has an error signal of "1". Obtain the AERROR signal representing the bit audio data period.

Since this AERROR signal is delayed by one sample from the original input voice data of (2), the input voice data of (2) is also set to 1 by passing through the D flip-flops 310 and 311. The sample is delayed, and the delayed voice and the AERROR signal are supplied to the deshuffling circuit. Thereby, as shown in (8) of FIG. 14 by the replacement operation in the deshuffling circuit,
d10 and d11, d16 and d17, d20 and d2
Desired voice data in which the part 1 is replaced with the error code ec is obtained. In addition, ec1 in this (8)
And ec2 are the upper 8 bits and the lower 8 bits of the error code ec in FIG.

The audio data that has been subjected to the error replacement processing as described above is supplied to the deshuffling memories 27 and 28 in the deshuffling circuit of FIG. 12, and alternately every frame based on the switching operation of the switch S4. It is written in the memories 27 and 28 according to the write control signal. The write control signal has a write address corresponding to the audio data track number, the SYNC block number, and the sample number of the audio data determined based on the byte position number. It is rearranged in the order of sample numbers on the shuffling memory. Reading from the deshuffling memory is executed by a reading control signal from the reading control circuit 19, the audio data is returned to the original time axis and is read in the order of sample numbers.

The voice data read from the deshuffling memory is input to the error interpolation circuit 30, and the data portion replaced with the error code ec is subjected to error interpolation by a method such as holding the previous value. The audio data that passed through the error interpolation circuit is 16-bit D
The original analog audio signal of channel 1 is extracted by being supplied to the A conversion circuit 31. The internal structure of the deshuffling circuits 24 to 26 is the same as that of the deshuffling circuit 23, and the audio signals of channels 2 to 4 are taken out.

The mode processing microcomputer 82 checks the value of the quantized bit number code QU in the reproduced AAUX SOURCE pack, and when the value is "010" or "011", the mode processing microcomputer 82 deshuffles. A control signal for stopping the operation of the circuit 26 and the DA conversion circuit 34 is output to stop the operation of these circuits, and the noise due to the lower 4 bit components is prevented from being generated from the channel 4. And at this time, D
If the value of QU is "010", the A conversion circuits 31 to 33 can obtain the decoded output of the upper 16-bit component of the 20-bit audio data of channels 1 to 3, and
If the value of QU is "011", the decoded output of the upper 16-bit component of the 20-bit audio data of channels 1 and 2 and the decoded output of the 16-bit audio data of channel 3 are obtained, and the audio processing is performed respectively. It is connected to the speaker through the circuit.

As can be seen from the above description, in the consumer digital VTR of this embodiment, the mode processing microcomputer is required for the reproduction of the audio signal from the tape recorded by the business digital VTR. It only requires the addition of software and a small amount of additional circuitry, with almost no increase in cost.

(2) Professional Digital VTR Next, the voice data processing circuit of the professional digital VTR according to the present invention will be described. It should be noted that in the following description, only models applicable to the 1125/60 system will be described.

I) Professional digital VTR adopting 20-bit mode recording a. Voice Data Recording Circuit The voice data recording circuit of such a commercial digital VTR will be described with reference to FIG. In this circuit, 5-8
Are respectively the consumer digital VTs shown in FIG.
Shuffling circuit 5 used in R voice recording circuit
~ 8 are the same. Further, although omitted in FIG. 15, the write control signal and the read control signal to be supplied to each shuffling circuit in this figure are the write control circuit 15, the read control circuit 13, the switch in FIG. 1
2. The switching control circuit 14 has the same configuration as that of the switching control circuit 14. As a result, the professional digital VTR performs shuffling with the same shuffling pattern as that of the consumer digital VTR shown in FIG.

Then, the input analog audio signals of channels 1 to 3 are respectively converted into 20-bit audio data by the AD conversion circuits 35 to 37, and these 2
The upper 16 bits of the 0-bit audio data are supplied to the shuffling circuits 5 to 7, respectively, and
The lower 4 bits are supplied to the shuffling circuit 8. In the 16-bit data input to the shuffling circuit 8, the most significant 4 bits are the lower 4 bits of the channel 1 audio data, the next 4 bits are the lower 4 bits of the channel 3 audio data, and the next 4 bits are the lower 4 bits of the audio data of channel 2, and the last 4 bits are dummy data "1111". The voice data thus input to each shuffling circuit is read out at the same timing as in the case of voice recording in the 16-bit mode in the consumer digital VTR and is supplied to the framing circuit of the next stage.

B. Audio Data Reproducing Circuit FIG. 16 shows a main part of a 20-bit mode audio data reproducing circuit. In this circuit, the deframing circuit 10
The audio data and the AERROR signal output from the switch 7 are supplied to the switches 22 and 21, respectively.
Switching is performed in the same manner as in the case of reproducing the 16-bit mode audio data of No. 2 and is distributed to the deshuffling circuits 23 to 26. These deshuffling circuits have the same internal configuration as the deshuffling circuit 23 in FIG.
An operation of replacing an error occurrence portion with an error code ec, a deshuffling operation, and an error interpolation operation are executed (note that the write control signals to and the read control signals supplied to these deshuffling circuits are the same as those in FIG. 12). Will be generated).

However, the error interpolation in the deshuffling circuit 26 of FIG. 16 is not a method of holding the previous value, but a method of forcibly replacing the value with 0000h (that is, replacing all lower 4 bits of the audio data with "0000"). Has been adopted. The reason for using such a method is that it is meaningless to purposely interpolate the lower-order 4-bit component, which changes drastically, by holding the previous value, and such simple replacement is sufficient. In this case, by setting the value of ec in the replacement operation to the error code ec performed at the input side of the circuit 26 to 0000h, the above "0" is set.
Alternatively, the error interpolating circuit may not be provided at the final stage in the circuit 26. In addition, the value that replaces the lower 4 bits is "00".
Instead of “00”, “0111” near the middle may be used (in this case, the code value to be replaced is, for example, 777).
0h).

The 16-bit audio data output from the deshuffling circuits 23 to 25 is set in the upper 16 bits of the 20-bit DA conversion circuits 38 to 40, and the 16-bit audio data is output from the deshuffling circuit 26.
The bit data is separated into the lower 4 bits of each channel and set in the lower 4 bits of the DA conversion circuits 38-40. As a result, the original analog audio signals of channels 1 to 3 are taken out from each DA conversion circuit.

When the value of the QU code in the reproduced AAUX SOURCE pack is "000" (that is, 16-bit mode recording), the mode processing microcomputer 82 determines that the mode processing microcomputer 82 has the deshuffling circuit 26. A switching signal is output to the triple switch 301 provided on the output path of the switch, and each movable terminal of this switch is tilted to the right. As a result, 16-bit mode audio data is set in the upper 16 bits of each DA converter, and the switch 301 is set in the lower 4 bits.
The 4-bit dummy data "0000" supplied to the right terminal of the
The DA conversion output of the bit data is taken out as the analog audio signal of each channel.

When the reproduction operation of the audio data in the 20-bit mode is being executed in this circuit, the lowest 4 bits of the data output from the deshuffling circuit 26 are the dummy data "1111". The lower 4 bits of data can be used to determine whether the error detection function of this digital VTR is operating normally.

The error detection function check device 300 shown in the figure is provided to make this determination. The least significant 4 bits are input to the check device 300 and to the deshuffling circuit 26. AERR
The OR signal (4) is also input to the detection device 300. Then, when the least significant 4 bits indicate a value different from "1111," the AERRO associated with the least significant 4 bits.
Examine the value of the R signal. At this time, since the value of the investigated AERROR signal should have originally indicated that it is an error, when it does not indicate that it is an error, the error detection function in this digital VTR is Means that the check is not working normally, and the check device 300 performs an operation such as a warning process.

In the reproducing circuit described above, the propagation error processing is also performed for the error occurring in the channel of the lower 4 bits, but one of the lower 4 bit components of the first and second byte positions is used. When an error occurs only in the 4-bit component at the byte position, the propagation error processing may not be performed so that the data at the other byte position where the error has not occurred is utilized.

FIG. 17 shows an example of a reproducing circuit constructed on the basis of such an idea. A propagation error processing circuit 31 is provided to each of the deshuffling circuits 23 to 25 of channels 1 to 3.
The voice data from 5 and the AERROR signal are switched 3
26 and switch 328. On the other hand, the audio data and the ERROR signal reproduced from the channel 4 are input to the error processing circuit 341 without passing through the propagation error processing circuit 315 by the ON operation of the switch 327, where the error processing is performed, and then the four channels are processed. Are supplied to the deshuffling circuit 340.

The error processing circuit 341 is constructed as shown in FIG. The circuit operation will be described with reference to FIG. (2) of FIG. 19 represents the audio data input to the switch 350, and the movable terminal of this switch is tilted downward only when the level of the ERROR signal is HIGH (that is, when an error occurs). Then, as shown in (4) of FIG. 19, the error portion in the voice data is the compensation data c. d. Is replaced by c. d. As the value of, for example, 00h is used. The output of the switch 350 is 351
And 352 are delayed by 2 clocks before being output. The delay operation is to match the timing with the audio data of channels 1 to 3.

Ii) Professional digital VTR employing mixed mode recording a. Voice Data Recording Circuit FIG. 20 shows a voice data recording circuit in such a commercial digital VTR. The difference from the case of the 20-bit mode recording shown in FIG. 15 is that the original audio data of channel 3 is 16 bits, and the lower 4 bits of the audio data of channels 1 and 2 are repeated twice in channel 4. It is a point to be recorded, and there is no particular difference other than that.

B. Voice data reproduction circuit Digital V for professional use adopting mixed mode recording in FIG.
The main part of the audio data reproducing circuit in TR is shown. In this circuit, the audio data reproduced from channels 1 to 3 and the ERROR signal are subjected to the propagation error processing by the propagation error processing circuit 315 in the deframing circuit 107 as in the case of the 20-bit mode recording, and then, respectively. Channels 1 through switches 326 and 328
3 to the respective deshuffling circuits 23 to 25.

On the other hand, the audio data and the ERROR signal reproduced from the channel 4 are supplied to the error processing circuit 322 without passing through the propagation error processing circuit 315 by the switching operation of the switch 327, and after the error processing here, the shuffling is performed. It is input to the ring circuit 324. The error processing circuit 322 uses the lower 4-bit component repeatedly recorded in the first byte and the second byte of the 16-bit reproduction data when the error occurs in one byte and the data of the other byte. In addition, the reproduction data is compensated data c. d. It has a function of substituting (for example, 00h is used as a specific value), and its circuit configuration is shown in FIG.

Next, the operation of this circuit 322 will be described with reference to FIG. The signal (2) in FIG. 23 represents the audio data input to the D flip-flops 330 and 333, and the signal (3) represents the ERROR signal accompanying this audio data. In this circuit, when there is no error in the input audio data, the movable terminal of the switch 331 is held on the upper side and the movable terminal of the switch 332 is held on the lower side, and the D flip-flop 3
The output of 30 is output from this error processing circuit. Here, the D flip-flop 330 is driven by a clock pulse having a 1/2 frequency as shown in (4) which rises at the trailing edge of the second byte of each 16-bit audio data of the input data of (2). Therefore, the delayed output of the audio data at the second byte position is obtained from the flip-flop as shown in (6).

On the other hand, when an error has occurred in the audio data at the second byte position, this is detected by the D flip-flop 335 and the output side is HIGH.
The latch output of the state appears (see (8) in FIG. 23), and the switch 3 is turned on by the latch output of the HIGH state.
The movable terminal 31 is tilted downward. On the other hand, the switch 33
To the fixed terminal on the lower side of 1, a data string consisting of only the audio data at the first byte position obtained by passing the input audio data through the D flip-flop 333 and the D flip-flop 334 is supplied (see FIG. 23). (See (7)), the audio output data is replaced with the audio data at the first byte position only during the HIGH state.

When an error occurs in both the first and second byte positions, the output of the AND gate 336 regarding the ERROR signal becomes HIGH (FIG. 23).
(10)). Then, this is detected by the D flip-flop 337, and the switch 3 is detected by this detection output.
The movable terminal of 32 is tilted upward to reproduce the reproduction data from the compensation data c. d. The operation of replacing
See 1) and (12).

The audio data subjected to the desired error processing as described above is subjected to the deshuffling processing by the deshuffling circuit 324 in the next stage in FIG. It is supplied to the conversion circuit and the original analog voice is taken out. It should be noted that the mode processing microcomputer 82 uses the reproduced AAUX
When the value of the QU code in the SOURCE pack is "000", tilt the movable terminal in the switch 323 to the right and
Dummy data "0000" is set in the lower 4 bits of the A conversion circuits 38 and 39 to enable decoding of 16-bit audio data reproduced from channels 1 and 2.

Although various embodiments of the digital VTR according to the present invention have been described above, various other embodiments can be configured within the scope of the technical idea of the present invention. For example, in each reproducing circuit shown in FIGS. 17 and 21, the compensation data c. d. 00h is used as the value of, but 77h may be used instead. Also, in these reproduction circuits, the propagation error processing is performed on the channel 1
It is configured to be independently performed only in each of channels 4 to 4. However, for example, when an error occurs in the lower 4-bit component of a specific channel, an error is also generated in the upper 16-bit component of the specific channel. Alternatively, the entire 20-bit data may be processed as an error by performing such a propagation error process.

As can be seen from the entire description up to now, the commercial digital VTR according to the present invention uses most of the circuit configuration used in the consumer digital VTR as the circuit configuration of the signal processing system. Therefore, a commercial digital VTR capable of recording / reproducing audio data in 20-bit mode can be constructed by making a slight design change to the consumer digital VTR. Also, with respect to the consumer digital VTR, it is possible to reproduce the 20-bit audio data recorded by the commercial digital VTR as 16-bit audio data by adding a small circuit and microcomputer software.

Furthermore, for example, from the similarity between the reproducing circuit of the professional digital VTR adopting the 20-bit mode recording shown in FIG. 17 and the reproducing circuit of the professional digital VTR adopting the mixed mode recording shown in FIG. As can be seen, since these professional digital VTRs share many signal processing circuits, the user can select either 20-bit mode recording or mixed mode recording in one professional digital VTR. Also, it can be easily realized by adding a few signal processing circuits and switching circuits.

[0213]

Industrial Applicability A digital VTR for consumer use and a digital VTR for business which are compatible with each other can be constructed by slightly changing the configuration. In recording / reproducing audio in a commercial VTR, the same error code as that used in the processing system of the reproduced signal from the channel in which the lower bit component of the audio data is recorded is used. Error processing using an error code is possible.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing an audio track when audio recording is performed in a 20-bit mode.

FIG. 2 is a diagram showing how audio data is recorded in a SYNC block of each track in 20-bit mode recording.

FIG. 3 Digital V for professional use of 1125/60 system
It is a figure which shows the shuffling pattern type | formula at the time of recording audio | voice in 20 bit mode in TR.

FIG. 4 is a schematic diagram when a tape recorded in a 20-bit mode by a commercial digital VTR is reproduced by a consumer digital VTR.

FIG. 5 is a diagram illustrating an operation when reproducing a tape in which audio recording modes are different between the first half and the second half of a frame.

FIG. 6 is a digital V for commercial use of the 1250/50 system.
It is a figure which shows the shuffling pattern type | formula at the time of recording audio | voice in 20 bit mode in TR.

FIG. 7 is a schematic diagram showing an audio track when mixed mode recording is performed in an HD type professional digital VTR.

FIG. 8: SYN of each track in mixed mode recording
It is a figure which shows a mode that audio | voice data is recorded on C block.

FIG. 9: Digital V for professional use of 1125/60 system
It is a figure which shows the shuffling pattern type | formula at the time of performing audio | voice recording of mixed mode in TR.

FIG. 10 is a diagram showing a shuffling pattern formula when voice recording in a mixed mode is performed in a commercial digital VTR of a 1250/50 system.

FIG. 11 is a diagram showing a main part of a recording circuit for performing audio recording in 16-bit mode in a consumer digital VTR of 1125/60 system.

FIG. 12 is a diagram showing a main part of an audio reproducing circuit in a consumer digital VTR of the 1125/60 system.

FIG. 13 is a diagram showing a configuration of a propagation error processing circuit.

FIG. 14 is a timing chart illustrating a propagation error processing operation.

FIG. 15 is a diagram showing a main part of a recording circuit for performing voice recording in a 20-bit mode in a commercial digital VTR of 1125/60 system.

FIG. 16 is a diagram showing a main part of a circuit for reproducing voice recorded in a 20-bit mode in a commercial digital VTR of 1125/60 system.

FIG. 17 is a circuit configuration in the case where a propagation error process is not performed in the reproduction process of the lower 4 bit components in the reproduction circuit of the audio recorded in the 20-bit mode in the same VTR.

FIG. 18 is a diagram showing a configuration of an error processing circuit in the circuit configuration.

FIG. 19 is a timing chart illustrating the operation of the error processing circuit.

FIG. 20 is a diagram showing a main part of a recording circuit in the case of performing voice recording by mixed mode recording in a commercial digital VTR of 1125/60 system.

FIG. 21 is a diagram showing a main part of a circuit for reproducing audio recorded in mixed mode in a commercial digital VTR of 1125/60 system.

FIG. 22 is a diagram showing a configuration of an error processing circuit in the reproducing circuit.

FIG. 23 is a timing chart illustrating the operation of the error processing circuit.

FIG. 24 is a diagram showing a recording format of one track of a digital VTR.

FIG. 25 is a pre-sync block and a post-sync.
It is a figure which shows the structure of a block.

[Fig. 26] Fig. 26 is a diagram illustrating the framing format of AUDIO and the structure of a 1SYNC block.

FIG. 27 is a diagram illustrating blocking of image data for one frame.

FIG. 28 is a diagram showing a VIDEO framing format to which an error correction code is added.

[Fig. 29] Fig. 29 is a diagram illustrating the configurations of a VIDEO buffering unit and a 1SYNC block.

FIG. 30 is a diagram illustrating the structure of a SUBCODE area for one track.

FIG. 31 is a diagram illustrating a structure of an ID part of a SYNC block in an AUDIO area and a VIDEO area.

FIG. 32 is a diagram illustrating a structure of an ID part of a SYNC block in a SUBCODE area.

FIG. 33 is a diagram showing the basic structure of a pack.

FIG. 34: Definition of a group of packs with large items,
And AAUX SOURCE pack and VAUX SOU
It is a figure which shows the detail of an RCE pack.

FIG. 35: VAUX SOURCE CONTROL pack, VAUX REC DATE pack, VAUX
REC TIME pack, VAUX REC TIME
BINARY GROUP pack and CLOSED
It is a figure which shows the detail of a CAPTION pack.

FIG. 36 is a diagram illustrating a structure of an AAUX area for one frame.

FIG. 37 is a diagram illustrating the structure of a VAUX area for one track.

FIG. 38 is a diagram illustrating a pack structure of a VAUX area for one frame.

FIG. 39 is a diagram illustrating multiple writing of pack data in a SUBCODE area in a digital VTR of a 525/60 system.

FIG. 40 is a diagram illustrating multiple writing of pack data in a SUBCODE area in a digital VTR of a 625/50 system.

FIG. 41 is a diagram illustrating a memory map of a memory-in cassette.

FIG. 42 is a diagram showing a recording circuit of a digital VTR.

FIG. 43 is a diagram illustrating generation of pack data in a recording circuit of a digital VTR.

FIG. 44 is a diagram illustrating a main area on a recording track.

FIG. 45 is a diagram illustrating generation of pack data in a mode processing microcomputer.

FIG. 46 is a diagram showing a partial configuration of a reproducing circuit of a digital VTR.

FIG. 47 is a diagram showing the configuration of another portion of the playback circuit of the digital VTR.

[Fig. 48] Fig. 48 is a diagram for describing processing of reproduction pack data in the VAUX IC.

[Fig. 49] Fig. 49 is a diagram for describing processing of reproduction pack data in the signal processing microcomputer.

FIG. 50 is a diagram illustrating definition of a track format by APT.

FIG. 51 is a diagram illustrating a hierarchical structure of application IDs.

FIG. 52 is a diagram illustrating a format on a track when the application ID is “000”.

[Fig. 53] Fig. 53 is a diagram for explaining a track format in the case where an ATV signal can be recorded by setting an application ID.

FIG. 54 is a diagram illustrating a packet structure in an ATV signal.

FIG. 55 is a diagram showing an example of a configuration of an ATV signal.

FIG. 56 is a diagram showing an example of a recording circuit for recording an ATV signal on a digital VTR.

FIG. 57 is a diagram showing an example of a reproduction circuit in the case of reproducing an ATV signal from a digital VTR.

Figure 58: 1125/60 system and 1250/50
It is a schematic diagram which shows the mode of the conventional audio | voice recording track in the digital VTR of a system.

FIG. 59 1125/60 system and 1250/50
It is a figure which shows the shuffling pattern type | formula in the case of the conventional audio | voice recording in the digital VTR of a system.

FIG. 60: Digital VTR of 1125/60 system
FIG. 7 is a diagram showing a shuffling pattern on a SYNC block in the case of the conventional voice recording in FIG.

FIG. 61: Digital VTR of 1255/50 system
FIG. 7 is a diagram showing a shuffling pattern on a SYNC block in the case of the conventional voice recording in FIG.

[Explanation of symbols]

1-4, 35-37 ... AD conversion circuit, 5-8 ... Shuffling circuit, 23-26 ... Deshuffling circuit,
29 ... Error identification circuit, 30 ... Error interpolation circuit,
31-34, 38-40 ... DA conversion circuit, 82 ... Mode processing microcomputer, 107 ... Deframing circuit, 315 ... Propagation error processing circuit, 322, 34
1 ... error processing circuit,

─────────────────────────────────────────────────── ─── Continuation of front page (58) Fields surveyed (Int.Cl. ⁷ , DB name) G11B 20/10

Claims (5)

(57) [Claims] 1. Encoded audio data of each channel obtained by encoding audio signals of a plurality of channels is provided with item data for defining a format of subsequent data.
Each area in units of packs with fixed length bytes
An audio area, an AAUX area, and
Video area, VAUX area, and SUBCODE
A recording medium and rear is used, an audio signal recording method for recording, as well as to select arbitrarily the number of quantization bits at the time of the encoding from among a plurality of quantization bits, each The encoded audio data of each channel is recorded independently in each channel in the recording area of each channel provided on the recording medium, and is obtained by encoding the audio signal in accordance with the selected quantization bit number. When the data amount of the encoded audio data to be recorded exceeds the recording capacity of the recording area of the encoded audio data of each channel configured in the pack, the audio signal of a specific channel among the audio signals of a plurality of channels The recording is stopped, and the coded audio data of the channels other than the specific channel is recorded as the bit component of the coded audio data. Of the minutes, only the data portion consisting of the higher-order bit components within the range that does not exceed the recording capacity of the recording area of the encoded audio data is used as a unit for each pack of the audio signal of the other channel.
And recorded in the configured recording area, a data portion consisting of lower bits components other than said upper bit component in the encoded audio data of the audio signal of the specific channel path
A sound signal recording method characterized by recording in a recording area constituted by units of blocks . 2. An item for defining the format of subsequent data.
In units of packs with fixed length bytes containing
Audio area and AAU
X area, video area, VAUX area, SU
The BCODE area is provided on the recording medium used.
In the recording area of each channel, the encoded audio data of each channel obtained by encoding the audio signals of a plurality of channels is independently recorded for each channel, and the number of quantization bits at the time of the encoding is recorded. Is selected from a plurality of quantization bit numbers, a code representing the selected quantization bit number is recorded on the recording medium as ancillary data, and according to the selected quantization bit number, When the data amount of the encoded audio data obtained by encoding the audio signal exceeds the recording capacity of the recording area of the encoded audio data of each channel configured in the pack, the audio signals of a plurality of channels Recording of the audio signal of a specific channel among them, and encoded audio data of a channel other than the specific channel. Regarding, regarding the bit components constituting the encoded audio data, only the data portion consisting of the upper bit component in a range not exceeding the recording capacity of the recording area of the encoded audio data is used for each of the audio signals of the other channels. Unit of pack
A recording area in which a data portion consisting of lower bit components other than the upper bit component of the encoded audio data is recorded in a unit of a pack of audio signals of the specific channel. In an audio signal reproducing device for reproducing an audio signal from a recording medium recorded according to the audio signal recording method for recording
There are a DA converter for DA converting the encoded audio data reproduced from the recording medium, path having a fixed length byte AAUX area of the recording medium
A quantized bit number identifying circuit for identifying the quantized bit number of the reproduced encoded audio data based on the accompanying data reproduced from the audio data, and further identified by the quantized bit number identifying circuit. When the number of quantized bits is larger than the number of quantized bits of the DA conversion circuit, only bits corresponding to the number of quantized bits of the DA conversion circuit are selected from the bit components forming the reproduced encoded audio data. An audio signal reproducing apparatus, characterized in that the audio signal is reproduced by extracting the upper bit component of the extracted encoded audio data into the DA conversion circuit. 3. When the quantization bit number identified by the quantization bit number identifying circuit is larger than the quantization bit number of the DA converting circuit, the data portion consisting of the lower bit component is reproduced from the recording area in which the data portion is recorded. 3. The audio signal reproducing device according to claim 2, further comprising means for stopping the operation of the circuit for processing the data. 4. An item for defining a format of subsequent data.
In units of packs with fixed length bytes containing
Audio area and AAU
X area, video area, VAUX area, SU
The BCODE area is provided on the recording medium used.
In the recording area of each channel, the encoded audio data of each channel obtained by encoding the audio signals of a plurality of channels is independently recorded for each channel, and the number of quantization bits at the time of the encoding is recorded. Is selected from a plurality of quantization bit numbers, a code representing the selected quantization bit number is recorded on the recording medium as ancillary data, and according to the selected quantization bit number, When the data amount of the encoded audio data obtained by encoding the audio signal exceeds the recording capacity of the recording area of the encoded audio data of each channel configured by the pack as described above , encoding of a plurality of channels is performed. Recording of the encoded audio data of a specific channel of the audio data is stopped, and at the same time other than the specific channel is recorded. Regarding the encoded voice data, among the bit components forming the encoded voice data, only the data portion consisting of the upper bit component within the range not exceeding the recording capacity of the recording area of the encoded voice data is used for the other channels. The encoded audio data is recorded in a recording area formed by using each pack as a unit , and further, a data portion including lower bit components other than the upper bit component in the encoded audio data is encoded audio of the specific channel. Unit of data pack
Is an audio signal reproducing device for reproducing an audio signal from a recording medium recorded according to an audio signal recording method for recording in a recording area constituted by a DA converter for DA converting a path having a fixed length byte AAUX area of the recording medium
A quantized bit number identifying circuit for identifying the quantized bit number of the reproduced encoded audio data based on the accompanying data reproduced from the clock, and the quantum identified by the quantized bit number identifying circuit. When the number of encoded bits is smaller than the number of quantized bits of the DA conversion circuit, the reproduced encoded audio data is set on the input side of the DA conversion circuit as the upper bit component of the input data to the DA conversion circuit. At the same time, a voice signal reproduced from the DA conversion circuit is taken out by setting predetermined dummy data as the remaining lower bit component of the input data. 5. The encoded audio data of each channel obtained by encoding the audio signals of a plurality of channels according to the number of quantization bits arbitrarily selected from a plurality of quantization bit numbers, Each of them is independently recorded in the recording area of each channel provided on the recording medium, and after performing the process of replacing the error part of the encoded audio data reproduced from the recording medium with a predetermined error code, In the audio signal recording / reproducing method for performing the decoding process for extracting the audio signal of, the data amount of the encoded audio data obtained by encoding the audio signal according to the selected quantization bit number is When the recording capacity of the recording area of the encoded audio data of each channel is exceeded, a specific channel of the audio signals of multiple channels is For recording the audio signal of the channel other than the specific channel after stopping the recording of the audio signal of the channel, the recording capacity of the recording area of the audio signal among the bit components that make up the encoded audio data is set. Only the data part consisting of the high-order bit component in the range that does not exceed is recorded in each recording area of the audio signal of the other channel, and the data part consisting of the low-order bit component other than the high-order bit component in the encoded audio data is recorded. In the recording area of the audio signal of the specific channel, further, in the recording of the data portion including the lower bit component, predetermined dummy data is recorded in the remaining empty area in which the lower bit component is recorded. As for the value of the data, the data reproduced from the recording area of the audio signal of the specific channel is the error code. Audio signal recording and reproducing method characterized by being set to a different possible value serving.