JP3651060B2 - Television signal recording device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to an apparatus for recording a television signal, and more particularly to a television signal recording apparatus capable of recording various accompanying data in addition to image data and audio data.
[0002]
[Prior art]
Currently, as a recording and playback device for efficiently recording and reproducing NTSC television signals with high quality, the image signal is sampled in a 4: 1: 1 format and digitized, and then subjected to DCT conversion, variable length coding, etc. An image compression recording type digital VTR that performs recording by compressing data by the above process has been proposed and will be put into practical use soon. The digital VTR employs a configuration in which data for one frame is recorded using 10 tracks.
[0003]
Also, a digital VTR for recording / reproducing a SECAM television signal has been proposed in which the same processing is performed for recording. In this image compression recording digital VTR for the SECAM system, the image signal is sampled in 4: 2: 0 format and then AD converted, and one frame of data is recorded using 12 tracks. Many of the specific data formats are made common with the data format in the above-mentioned NTSC digital VTR.
[0004]
One of the features of each digital VTR as described above is the recording of accompanying data. That is, in these digital VTRs, an audio data recording area and a video data recording area on the recording track of the tape are provided with an area for recording audio accompanying data and an area for recording video accompanying data, respectively. In addition to the recording area, a subcode area for recording accompanying data for search is provided. The accompanying data recorded in these areas has a common structure whose basic structure is in units of 5 bytes, and in each 5 bytes unit, header data representing the contents of data stored therein is included. By incorporating it, it is possible to record a wide variety of accompanying data.
[0005]
[Problems to be solved by the invention]
As described above, the digital VTR is configured to be able to record a wide variety of accompanying data. In particular, the video data recording area has a large recording capacity so that a sufficient amount of accompanying data can be recorded. Is provided. By the way, when such an area having a large recording capacity is provided, a large amount of accompanying data can be recorded, but the circuit configuration for recording and reproducing the accompanying data must be large. There is a problem that it is not possible.
In consideration of the above points, the present invention enables recording / reproduction of accompanying data using a smaller recording circuit and reproducing circuit.
[0006]
[Means for Solving the Problems]
The present invention is a television signal recording apparatus for recording a television signal using a recording medium, a generating means for generating image data from an input television signal, and accompanying data relating to the image data, A plurality of recording tracks per frame of the television signal are formed on the recording medium by scanning the recording medium with accompanying data generating means for generating the accompanying data composed of basic data and additional data; and The image data, basic data, and additional data are recorded in an image data recording area, a basic data recording area, and an additional data recording area provided in each recording track of the plurality of recording tracks, respectively. And an additional data recording area provided in one recording track. Each additional data recording area in a recording track that constitutes a track pair is recorded by repeatedly recording additional data having a data amount equal to the recording capacity in each additional data recording area of a plurality of recording tracks in one frame. In this case, additional data having the same data content is recorded, and the amount of additional data recorded repeatedly in the additional data recording area is recorded for each track. If there is less, the additional data is recorded in the leading direction of the additional data recording area, the dummy pack is recorded in the remaining additional data recording area, and the accompanying data includes a certain amount of bytes having an item code. Additional data configured in packs and recorded in an additional data recording area in one recording track , Including a pack representing a content of additional data to be recorded and a dummy pack, and the dummy pack has values in all data portions other than the data portion in which the item code is stored so as to invalidate all operations. It is a pack in which “1” is stored.
[0007]
Here, when the data amount of the additional data repeatedly recorded in the additional data recording area is smaller than the recording capacity of the additional data recording area formed for each track, the recording unit adds the additional data. As a dummy pack in the additional data recording area, the code indicating the common optional data is stored in the data section where the item code is stored, and other than the item code. A code indicating manufacturer's optional data is stored in the data part in which the value “1” is stored in the data part and / or the data part in which the item code is stored, and the value “1” is stored in the data part other than the item code. It is desirable to record the second pack that is stored.
The present invention also relates to an image data generating step for generating image data from an input television signal and ancillary data relating to the image data in a television signal recording method for recording a television signal using a recording medium. In addition, an incidental data generation step for generating incidental data composed of basic data and additional data, and a plurality of recording tracks per frame of a television signal are formed on the recording medium by scanning the recording medium. And the image data recording area, the basic data recording area, and the additional data recording area provided in each recording track of the plurality of recording tracks, respectively, are generated in the image data generating step. Record to record image data and basic data and additional data generated in the accompanying data generation process In the recording step, additional data having a data amount equal to the recording capacity of an additional data recording area provided in one recording track is added to each of a plurality of recording tracks in one frame. Repetitively record in the additional data recording area, record additional data consisting of the same data contents in each additional data recording area in the recording track constituting the track pair, and repeat in the additional data recording area. When the amount of additional data to be recorded is smaller than the recording capacity of the additional data recording area formed for each track, the additional data is recorded in the leading direction of the additional data recording area, and the remainder is recorded. A dummy pack is recorded in the additional data recording area, and the accompanying data is composed of a pack of a certain amount of bytes having an item code as a unit. The additional data recorded in the additional data recording area in one recording track includes a pack representing the contents of the additional data to be recorded and a dummy pack. A pack in which the value “1” is stored in all data portions other than the data portion in which the item code is stored so as to invalidate the operation.
Here, in the recording step, when the amount of additional data recorded repeatedly in the additional data recording area is smaller than the recording capacity of the additional data recording area formed for each track, the additional data As a dummy pack in the additional data recording area, the code indicating the common optional data is stored in the data section where the item code is stored, and other than the item code. A code indicating manufacturer's optional data is stored in the data part in which the value “1” is stored in the data part and / or the data part in which the item code is stored, and the value “1” is stored in the data part other than the item code. It is desirable to record the second pack that is stored.
[0008]
[Action]
Additional data of the accompanying data configured in units of packs is repeatedly recorded in each additional data recording area in a plurality of tracks constituting one frame at a cycle of one track.
A dummy pack is recorded in an additional data recording area in one track remaining after recording additional data.
[0009]
【Example】
Embodiments of a digital VTR to which the present invention is applied will be described in order according to the following items, particularly focusing on an NTSC digital VTR.
1. Digital VTR recording format
(1) ITI area
(2) AUDIO area
(3) VIDEO area
(4) SUBCODE area
(5) ID part structure
(6) Pack structure and type
(7) Structure of incidental information recording area
(8) Application ID system
2. Digital VTR recording circuit
3. Digital VTR playback circuit
4). Recording and playback of accompanying data
(1) Recording VAUX pack data
(2) AAUX pack data recording
(3) Recording SUBCODE data
(4) Pack data playback processing
[0010]
1. Digital VTR recording format
FIG. 13 shows a recording format on the tape in the NTSC digital VTR.
In this figure, margins are provided at both ends of the track. In addition, an ITI area for performing after-recording, an AUDIO area for recording audio signals, a VIDEO area for recording image signals, and a SUBCODE area for recording secondary data are provided on the inner side from the recording start side. It is done. An inter block gap (IBG) is provided between the areas to secure the area.
[0011]
Next, details of signals recorded in each of the above areas will be described.
(1) ITI area
As shown in the enlarged portion of FIG. 13, the ITI area is composed of a 1400-bit preamble, an 1830-bit SSA (Start-Sync Block Area), a 90-bit TIA (Track Information Area), and a 280-bit postamble. Has been.
[0012]
Here, the preamble has a function such as run-in of the PLL at the time of reproduction, and the postamble has a role for earning a margin. SSA and TIA are configured in units of 30-bit block data, and a predetermined SYNC pattern (ITI-SYNC) is recorded in the first 10 bits of each block data.
[0013]
In the 20-bit portion following this SYNC pattern, the SYNC block number (0 to 60) is recorded mainly in SSA, and the 3-bit APT information (APT2 to APO) and the recording mode are mainly recorded in TIA. An SP / LP flag to be identified and a PF flag indicating a reference frame of the servo system are recorded. APT is ID data that defines the data structure on the track, and takes the value “000” in this digital VTR.
[0014]
As can be seen from the above explanation, since many sync blocks with a short code length are recorded at fixed positions on the magnetic tape in the ITI area, for example, the 61st SYNC pattern of SSA was detected from the reproduction data. By using the position as a reference for defining the post-recording position on the track, the position to be rewritten at the time of post-recording can be defined with high accuracy, and good post-recording can be performed. This digital VTR is designed so that the product can be easily developed to various other digital signal recording / reproducing apparatuses as will be described later. Since rewriting is necessary, the ITI area on the track entrance side is always provided.
[0015]
(2) AUDIO area
As shown in the enlarged portion of FIG. 13, the audio area has a preamble and a postamble before and after the preamble, and the preamble includes a run-up for PLL pull-in and a pre-SYNC for pre-detection of the audio SYNC block. It is configured. The postamble is composed of a post SYNC for confirming the end of the audio area and a guard area for protecting the audio area during video data after-recording.
[0016]
Here, each SYNC block of the pre-SYNC and the post-SYNC is configured as shown in (1) and (2) of FIG. 14, the pre-SYNC is composed of two SYNC blocks, and the post-SYNC is composed of one SYNC block. ing. Then, the SP / LP identification byte is recorded in the sixth byte of the pre-SYNC. This is SP for FFh and LP for 00h. When the SP / LP flag recorded in the ITI area is unreadable, the SP / LP identification byte value of this pre-sync is adopted.
[0017]
The audio data recorded in the area sandwiched between the amble areas as described above is generated as follows.
First, an audio signal for one track to be recorded is subjected to AD conversion and shuffling, then subjected to framing, and further added with parity. A format in which parity is added by performing this framing is shown in (1) of FIG. In this figure, 5 bytes of audio data (this is called AAUX data) is added to the beginning of 72 bytes of audio data to form 1 block of 77 bytes of data, and 9 blocks are stacked vertically to form a frame. To this, an 8-bit horizontal parity C1 and a vertical parity C2 corresponding to 5 blocks are added.
[0018]
The data to which these parities are added is read out in units of blocks, a 3-byte ID is added to the head of each block, and a 2-byte SYNC signal is further inserted in the recording modulation circuit. The signal is formed into a signal of 1 SYNC block having a data length of 90 bytes as shown in (2) of FIG. This signal is recorded on the tape.
[0019]
(3) VIDEO area
The video area has the same preamble and postamble as the audio area as shown in the enlarged portion of FIG. However, it differs from that of the audio area in that the guard area is formed longer. The video data sandwiched between these amble areas is generated as follows.
[0020]
That is, in the case of an NTSC digital VTR, the Y signal is AD converted at a sampling frequency of 13.5 MHz and the color difference signal is 1/4 of the frequency, and effective scanning for one frame is performed from this AD conversion output. Extract area data. The extracted data for one frame is composed of 720 samples in the horizontal direction and 480 lines in the vertical direction for the AD conversion output (DY) of the Y signal, and the AD conversion output (DR) of the RY signal and B- The AD conversion output (DB) of the Y signal is composed of 180 samples in the horizontal direction and 480 lines in the vertical direction. These extracted data are divided into blocks of 8 samples in the horizontal direction and 8 lines in the vertical direction. When this blocking process is shown for DY for one frame, it is as shown in (1) of FIG.
[0021]
The same operation is performed on the color difference signals DR and DB to obtain blocked data for one frame as shown in FIG. However, in the case of a chrominance signal, the rightmost block in this figure has only 4 samples in the horizontal direction, so two adjacent blocks in the vertical direction are combined into one block. By the above blocking process, a total of 8100 blocks of 8 samples × 8 lines are formed with DY, DR, and DB per frame. A block composed of 8 samples in the horizontal direction and 8 lines in the vertical direction is called a DCT block.
[0022]
Next, after the blocked data is shuffled according to a predetermined shuffling pattern, DCT conversion is performed in units of DCT blocks, and then quantization and variable length coding are performed. Here, the quantization step is set for every 30 DCT blocks, and the value of this quantization step is set so that the total amount of output data obtained by quantizing 30 DCT blocks and variable-length coding is below a predetermined value. The That is, the video data is fixedly lengthened every 30 DCT blocks. The data for 30 DCT blocks is called a buffering unit.
[0023]
The data fixed as described above is subjected to framing together with video-accompanying data (this is called VAUX data) for each track of data, and then an error correction code is added.
FIG. 17 shows a format in which the framing is performed and an error correction code is added.
[0024]
In this figure, each of BUF0 to BUF26 represents one buffering unit. One buffering unit has a structure divided into five blocks in the vertical direction as shown in FIG. 18 (1), and each block has a data amount of 77 bytes. Also, an area Q for storing parameters relating to quantization is provided in the first byte of each block.
[0025]
Video data is stored in a 76-byte area following the quantized data. As shown in FIG. 17, VAUX data α and β corresponding to two blocks in the buffering unit are arranged above the 27 buffering units arranged in the vertical direction. At the bottom, VAUX data γ corresponding to one block is arranged, and 8-byte horizontal parity C1 and vertical parity C2 corresponding to 11 blocks are added to the framed data. Is done.
[0026]
The signal to which the parity is added in this manner is read out in units of blocks, and a 3-byte ID signal is added to the head side of each block. Further, a 2-byte SYNC signal is inserted in the recording modulation circuit. As a result, a signal of 1 SYNC block having a data amount of 90 bytes as shown in (2) of FIG. 18 is formed for the block of video data, and (3) of FIG. 18 is shown for the block of VAUX data. Such a signal of one SYNC block is formed. The signal for each SYNC block is sequentially recorded on the tape.
[0027]
In the framing format described above, since 27 buffering units representing video data for one track have data for 810 DCT blocks, data for one frame (8100 DCT blocks) has 10 data. It will be recorded in separate tracks.
[0028]
(4) SUBCODE area
The SUBCODE area is an area mainly provided for recording information for high-speed search, and an enlarged view thereof is shown in FIG. As shown in this figure, the SUBCODE area includes 12 SYNC blocks having a data length of 12 bytes, and a preamble and a postamble are provided before and after the SYNC block. However, the pre-SYNC and post-SYNC are not provided like the audio area and the video area. Each of the twelve SYNC blocks is provided with a data portion for recording 5-byte accompanying data (AUX data). Further, only the 2-byte horizontal parity C1 is used as the parity for protecting the 5-byte accompanying data, and the vertical parity is not used.
[0029]
Each SYNC block constituting the AUDIO area, the VIDEO area, and the SUBCODE area described above is subjected to 24/25 conversion during recording modulation (by converting the data of every 24 bits of the recording signal to 25 bits). Therefore, the recording data amount in each area is the number of bits as shown in FIG. 13.
[0030]
(5) ID part structure
As is clear from the configuration of each SYNC block shown in FIGS. 14, 15, 18, and 19, the SYNC block recorded in the AUDIO area, the VIDEO area, and the SUBCODE area is 2 bytes. It has a common structure in that a 3-byte ID portion including ID0, ID1, and IDP (parity protecting ID0 and ID1) is provided after the SYNC signal. In the ID area, ID0 and ID1 have a data structure defined in the audio area and the video area as shown in FIG.
[0031]
That is, ID1 stores the in-track SYNC number from the pre-SYNC in the audio area to the post-SYNC in the video area in binary.
Then, the track pair number in one frame is stored in the lower 4 bits of ID0. For example, in the case of an NTSC digital VTR, as will be described later, track numbers 0 and 1, track numbers 2 and 3, track numbers 4 and 5, track numbers 6 and 7, and track numbers 8 and 9 are track pairs. And track pair numbers 0 to 4 are assigned. As will be described later, a track having an even track number is recorded with a minus azimuth head, and a track having an odd track number is recorded with a plus azimuth head. It is possible to know immediately based on the track pair number and the azimuth of the head.
In the upper 4 bits of ID0, a 4-bit sequence number is stored in each SYNC block of AAUX + audio data and video data as shown in (1) of this figure.
[0032]
On the other hand, in the pre-SYNC block and post-SYNC block of the audio area and the SYNC block of parity C2, 3-bit ID data AP1 defining the data structure of the audio area is stored, and the pre-SYNC block and post-SYNC block of the video area are stored. In the SYNC block of parity C2, 3-bit ID data AP2 that defines the data structure of the video area is stored (see (2) in this figure). Note that these values of AP1 and AP2 are “000” in the digital VTR.
[0033]
The above sequence numbers are recorded as 12 different numbers from “0000” to “1011” for each frame. By looking at this sequence number, the data obtained at the time of variable speed reproduction is the same frame. It can be judged whether it is inside.
On the other hand, the structure of the ID part of the SYNC block in the SUBCODE area is defined as shown in FIG.
[0034]
This figure shows the structure of each ID part of SYNC block numbers 0 to 11 for one track in the SUBCODE area, and an FR flag is provided in the most significant bit of ID0. This flag indicates whether or not there are 5 tracks in the first half of the frame, and takes a value of “1” in the first 5 tracks and “0” in the second 5 tracks. In the next 3 bits, ID data AP3 defining the data structure of the SUBCODE area is recorded in the SYNC block having the SYNC block numbers “0” and “6”, and the SYNC of the SYNC block number “11” is recorded. In the block, ID data APT defining the data structure on the track is recorded, and in the other SYNC block, a TAG code is recorded. The value of AP3 is “000” in this digital VTR.
[0035]
Further, the TAG code shows unnecessary scenes such as three types of ID signals for search, that is, INDEX ID for commercial INDEX search, commercials, etc., as shown in an enlarged manner in FIG. It consists of a SKIP ID for cutting and a PP ID (Photo / Picture ID) for still image search. Also, the absolute number of the track (the track number from the beginning of the tape) is recorded using the lower 4 bits of ID0 and the upper 4 bits of ID1. However, as shown in this figure, one absolute track number is recorded using a total of 24 bits for three SYNC blocks. In the lower 4 bits of ID1, the SYNC block number of the SUBCODE area is recorded.
[0036]
In the digital VTR, as described above, incidental data is recorded in each area defined on the tape. In addition, a circuit board provided with a memory IC is mounted on a cassette in which the tape is stored. It is mounted and the accompanying data is recorded also in this memory IC. When the cassette is mounted on the digital VTR, the accompanying data written in the memory IC is read to assist the operation / operation of the digital VTR. Although this memory IC is called MIC (Memory In Cassette) in the present application, the details of the data structure are not directly related to the problem of the present invention, and thus the description thereof is omitted.
[0037]
(6) Pack structure and type
As described above, in the digital VTR, the accompanying data is recorded in the AAUX area of the audio area on the tape, the VAUX area of the video area, the AUX data recording area of the SUBCODE area, and the accompanying data in the recording area of the MIC. Each of these areas is configured with a pack having a fixed length of 5 bytes as a unit.
[0038]
Next, the structure and type of these packs will be described.
The pack has a basic structure of 5 bytes shown in FIG. Of these 5 bytes, the first byte (PC0) is used as item data (also referred to as a pack header) indicating the data content. Then, the format of the subsequent 4 bytes (PC1 to PC4) is determined corresponding to the item data, and arbitrary data is provided according to this format.
[0039]
This item data is divided into upper and lower 4 bits, and the upper 4 bits are called a large item and the lower 4 bits are called a small item. The upper 4-bit large item is, for example, data indicating the use of subsequent data, and the lower 4-bit small item is, for example, data indicating the specific content of the subsequent data. A maximum of 256 types of packs are defined by these item data. For reference, the types of packs defined by these item data are shown in FIGS.
[0040]
As can be seen from these figures, the type of pack depends on the value of the large item, control “0000”, title “0001”, chapter “0010”, part “0011”, program “0100”, audio auxiliary data ( AAUX) “0101”, image auxiliary data (VAUX) “0110”, camera “0111”, line “1000”, and soft mode “1111”.
[0041]
In these drawings, packs with “RSV” written represent undefined packs, and in particular, pack areas of large items “1001” to “1110” represent undefined areas. Therefore, new data can be recorded arbitrarily in the future by defining new item data (header) using a code of item data not yet defined. Further, since the contents of the data stored in the pack can be grasped by reading the header, the position on the tape on which the pack is recorded can be arbitrarily set.
[0042]
Next, a specific example of the pack will be described with reference to FIGS.
The packs shown in (1) to (5) of FIG. 25 and (1) of FIG. 26 belong to the AAUX group in FIG. 24 and are used for recording accompanying data related to audio, as can be seen from the item data. The contents of the recorded data are as follows.
[0043]
That is, the AAUX SOURCE pack shown in (1) of FIG. 25 includes a flag (LF) indicating whether or not the audio sample frequency is locked with the video signal, the number of audio samples per frame (AF SIZE), Number of audio channels (CH), stereo / monaural mode information of each audio channel (PA and AUDIO MODE), information on television system (50/60 and TYPE), presence / absence of emphasis (EF), time constant of emphasis (TC), sample frequency (SMP), and quantization information (QU) are recorded.
[0044]
The AAUX SOURCE CONTROL pack shown in (2) of the figure has SCMS data (the upper bit indicates whether there is a copyright and the lower bit indicates whether the original tape is used), copy source data (analog signal source or not) A digital signal source), copy generation data, an SS code indicating whether a signal to be recorded is scrambled or child-locked, and a flag indicating whether it is a recording start frame (R.S.), flag indicating whether it is a recording last frame (R.E.), recording mode data (REC MODE) such as original recording / post-recording recording / insert recording, flag (DRF) indicating tape running direction , Reproduction speed data, and genre category of recorded contents are recorded.
[0045]
In the pack of AAUX REC DATE shown in (3) of the figure, a flag “DS” indicating whether or not daylight saving time is present, a flag “TM” indicating whether or not there is a time difference of 30 minutes, data “TIME ZONE” indicating time difference, In addition, date, day, month, and year data are recorded.
In the AAUX REC TIME pack shown in (4) of the figure, data of recording time of ** hour ** minute ** second ** frame is recorded in SMPTE time code display. AAUX REC TIME BINARY shown in (5) of the figure
In the GROUP pack, binary group data of SMPTE time code is recorded.
[0046]
The AAUX CLOSED CAPTION pack shown in (1) of FIG. 26 stores EDS (Extended Data Service) data related to the language and type of the main voice and the second voice. The contents of these data are as follows.
MAIN and 2ND AUDIO LANGUAGE:
000 = Unknown
001 = English
010 = Spanish
011 = French
100 = German
101 = Italian
110 = Others
111 = None
MAIN AUDIO TYPE:
000 = Unknown
001 = Mono
010 = Simulated Stereo
011 = True Stereo
100 = Stereo
101 = Data Service
110 = Others
111 = None
2ND AUDIO TYPE:
000 = Unknown
001 = Mono
010 = Descriptive Video Service
011 = Non-program Audio
100 = Special Effects
101 = Data Service
110 = Others
111 = None
[0047]
Here, when a CLOSED CAPTION pack is recorded in an AAUX main area which will be described later, the types of the main sound and the second sound follow information in the pack. If a CLOSED CAPTION pack is not recorded in the AAUX main area and a pack without information (details of this pack will be described later) is recorded instead, the type of the main sound and the second sound Follows the AUDIO MODE information in the AAUXSOURCE pack.
Each pack shown in (2) to (5) in FIG. 26 and [1] to [3] in FIG. 27 belongs to the VAUX group in FIG. 24 as can be seen from the value of the item data. Used to record accompanying data related to images.
[0048]
The recording contents of these packs will be described. In the VAUX SOURCE pack shown in FIG. 26 (2), the channel number of the recording signal source and a flag (B / W) indicating whether or not the recording signal is a monochrome signal. , A code (CFL) indicating color framing, a flag (EN) indicating whether the CFL is valid, a code (SOURCE) indicating whether the recording signal source is a camera / line / cable / tuner / soft tape or the like. CODE), data relating to television signal systems (50/60 and TYPE), and data relating to identification such as UV broadcasting / satellite broadcasting (TUNER CATEGORY).
[0049]
In the VAUX SOURCE CONTROL pack shown in (3) of the figure, SCMS data (the upper bit indicates whether there is a copyright and the lower bit indicates whether the original tape is used), ISR data (recording performed immediately before) Indicating whether the signal is from an analog signal source), CMP data (representing the number of compressions), SS data (representing information such as whether the recording signal is scrambled), recording A flag (REC ST) indicating whether or not the frame is a start frame, an HH flag indicating whether or not a recorded signal has a high frequency HH signal component (when “0”, there is an HH signal component, “1”) Recording mode data (REC MODE) such as original recording / post-recording recording / insert recording is recorded. Further, data relating to aspect ratio (BCSYS and DISP), a flag (FF) relating to whether or not only the signal of one of the odd / even fields is to be output twice, and the field 1 in the period of field 1 A flag (FS) regarding whether to output a signal or a field 2 signal, a flag (FC) regarding whether the image data of the frame is different from the image data of the previous frame, and a flag regarding whether the image data is interlaced (IL), a flag (ST) regarding whether or not the recorded image is a still image, a flag (SC) indicating whether or not the recorded image is recorded in the still camera mode, and the genre of the recorded content are recorded Is done.
[0050]
Also, data related to the recording date is recorded in the VAUX REC DATE pack shown in (4) of the figure, and data related to the recording time is recorded in the VAUX REC TIME pack shown in (5) of the figure. The binary group data of the time code is recorded in the BINARY GROUP pack shown in [1] of FIG. In the CLOSED CAPTION pack shown in [2] of the figure, closed caption information transmitted during the vertical blanking period of the television signal is recorded.
[0051]
The system data transmitted mainly during the vertical blanking period is stored in the VAUX TR pack [3] in FIG. The type of system data to be recorded is defined as follows according to the value of DATA TYPE of the lower 4 bits of PC1.
0000 = Video ID data
0001 = WSS data
0010 = EDTV-2 ID in 22 line
0011 = EDTV-2 ID in 285 line
1111 = No information
Other = Reserved
[0052]
Further, the pack shown in [4] in the figure belongs to the TITLE group in FIG. 23, and is used when a time code is recorded on the tape.
The pack shown in [5] in the figure belongs to the CHAPTER group in FIG. 23 and records the absolute track number of the chapter start position on the tape.
[0053]
The pack shown in [1] of FIG. 28 stores the recording start / end time when timer timer recording is performed, and is recorded in the MIC and used. Also, the pack shown in [2] in the figure belongs to the SOFT MODE group in FIG. 24, and is used when the manufacturer independently records the accompanying data. Then, following this pack, an arbitrary pack of the small items “0001” to “1110” in the group is recorded, thereby recording desired accompanying data of the manufacturer.
[0054]
In addition, the specific data format of the pack of the small items “0001” to “1110” and the specific data format after the third bit of PC3 of the MAKER CODE pack are open to each manufacturer. Desired data can be recorded by arbitrarily setting these formats.
[0055]
The pack shown in [3] in the figure is used for recording character information. In particular, in this digital VTR, two types of character information recording modes of a full mode and a simple mode are prepared. This TP HEADER pack is used for full mode recording. This full mode recording is mainly used when a large amount of character data is recorded on a soft tape, and the character data is recorded by recording the TEXT HEADER pack and the TEXT pack after the TP HEADER pack.
[0056]
In this TP HEADER pack, as shown in the figure, LANGAGE TAG indicating the language type of the character information to be recorded, TOPIC TAG indicating the type of character information (TOC, MENU, cast, staff, lyrics, etc.), Content update flag (RE), last page unit number of character data (TENS / UNITSOF LPU), page unit number (TENS / UNITS OF PU NO.), DM code indicating maximum number of display characters per page, scroll display SCRL flag indicating whether or not, H / V flag indicating scroll direction, INIT flag indicating whether or not to initialize the display screen, and RASTER COLOR code indicating the color of the raster are recorded.
[0057]
In character recording in the simple mode, the TP HEADER pack is not used, and the TEXT pack is recorded after the TEXT HEADER pack. These packs are provided in small items “1000” and “1001” in each group of large items “0000” to “1000” as shown in FIG. 23 and FIG. 24, and an example of the TEXT HEADER pack This is shown in [4] of FIG. This pack includes the total number of TEXT packs following this pack (TDP), character data attributes (TEXT TYPE), character code type (TEXT CODE), definition of TOPIC TAG used in TP HEADER (TOPIC TAG), tape In the upper area, AREA NO. Is recorded.
[0058]
[5] in FIG. 28 shows an example of the TEXT pack, and character data is recorded in PC1 to PC4.
Although detailed description is omitted, as a pack for recording character information, there is a TELETEXT pack for recording the TELETEXT data of the item “01100111” in FIG. 24 in addition to the above packs.
[0059]
The LINE HEADER pack shown in (1) of FIG. 29 is mainly for AD-converting and recording data of a desired line in a vertical blanking period in a television signal. Stores various conditions for recording data of a desired line. That is, a code LINES (binary number) indicating a sampled horizontal period number, a code fr indicating a sampling frequency, a code QU indicating the number of quantization bits, and an optional code B / indicating whether the recording signal is a monochrome signal W, a code CLF representing a color frame, a flag EN indicating whether the color frame code CLF is valid or invalid, and line data stored in the line data pack are the first field line and the second field line. And a flag CM indicating whether the data is common, and the total number of samples TDS (binary number) of the line data recorded following the line header.
[0060]
Subsequent to this pack, the desired line data subjected to AD conversion is stored in the desired pack among the packs of items “10000001” to “10000111” in FIG. 24 to record the line data. As an example of a pack in which the desired line data is stored, a LINE Y pack in which AD converted Y data is stored is shown in FIG. Four bytes of Y data are stored in PC1 to PC4 of this pack.
As a special example of the pack, a pack whose item code is all 1 is defined as a no-information pack (No Information pack), and FFh is stored in all of PC1 to PC4 (see (3) in FIG. 29). .
[0061]
As can be seen from the above description, in the digital VTR, the structure of the accompanying data is a pack structure common to each area as described above. Therefore, the software for recording and reproducing these data can be shared, Becomes easier.
In addition, since the timing at the time of recording and reproduction is constant, it is not necessary to provide an extra memory such as a RAM for time adjustment, and the software can be easily developed even when developing a new model. be able to.
Further, by adopting the pack structure, for example, when an error occurs during reproduction, the next pack can be easily taken out. Therefore, a large amount of data is not destroyed due to error propagation or the like.
[0062]
(7) Structure of incidental information recording area
Next, a specific structure of the AAUX area, VAUX area, and SUBCODE data area in which a variety of associated data is recorded using a pack will be described.
▲ 1 AAUX area
In the AAUX area, one pack is composed of a 5-byte AAUX area in the format of the 1SYNC block shown in (2) of FIG. Therefore, the AAUX area is composed of 9 packs per track. In the NTSC digital VTR, one frame of data is recorded in 10 tracks, so an AAUX area for one frame is expressed as shown in FIG.
[0063]
In this figure, one section represents one pack. The letters A to F written in the sections represent the six packs shown in (1) to (5) of FIG. 25 and (1) of FIG. 26, respectively. Called the main pack. An area in which these main packs are recorded is called an AAUX main area. The area other than this is called an AAUX optional area, and an arbitrary pack can be selected from various packs and recorded.
[0064]
▲ 2 ▼ VAUX area
As for the VAUX area, the VAUX area in one track is composed of three SYNC blocks α, β and γ as shown in FIG. 17, and the number of packs is 15 per SYNC block as shown in FIG. There are 45 tracks per track. The 2-byte area immediately before the error code C1 in one SYNC block is used as a preliminary recording area.
[0065]
FIG. 32 shows the pack configuration of the VAUX area for one frame. The packs indicated by letters A to E in this figure represent the five packs indicated by (2) to (5) in FIG. 26 and [1] in FIG. 27, and are indicated by F1 to F5. As shown in FIG. 27, either pack [2] or [3] in FIG. 27 is recorded. These packs A to E and F1 to F5 constitute a VAUX main area. As shown in this figure, the main area has track numbers 0, 1, 2, 3, 4, 5, 5, 6 and 7, In each track pair of 8 and 9, the same main pack is recorded. The other area constitutes the VAUX optional area.
[0066]
(3) SUBCODE data area
In the SUBCODE data area, as shown in FIG. 19, 5 bytes are written in each SYNC block of SYNC block numbers 0 to 11, and each pack constitutes one pack. That is, twelve packs are recorded in one track, among which packs with SYNC block numbers 3 to 5 and 9 to 11 constitute a main area, and the other packs constitute an optional area.
[0067]
Data for one frame in the SUBCODE data area is repeatedly recorded in a format as shown in FIG. In this figure, the upper case alphabet represents the main area pack, A is the TITLE TIME CODE pack, B is the TITLE TIME CODE pack or its BINARY GROPE pack, and C is the TITLE TIME CODE pack (however, in the case of soft tape) CHAPTER START pack), D represents a RECDATE pack (for example, VAUX REC DATE pack), and E represents a RECTIME pack (for example, VAUX REC TIME pack).
[0068]
The lower case alphabet represents an optional area pack, and arbitrary data can be recorded by selecting an arbitrary pack in this area. However, the packs a to m in the optional area are also characterized by being repeatedly recorded with regularity as shown in the figure.
[0069]
This figure shows the SUBCODE pack structure of the NTSC digital VTR. In the case of the SECAM digital VTR, one frame is composed of 12 tracks, and the SUBCODE pack structure is as shown in FIG. Become. That is, only the number of repeated recordings is increased.
[0070]
The main area in each area described above is characterized in that a pack storing incidental information related to basic data items common to all tapes is recorded. On the other hand, any additional accompanying data can be freely written in the optional area by a soft tape manufacturer or a user.
Various rules are provided for recording / reproducing the accompanying data in the accompanying data recording area as described above. The conventions are listed below.
[0071]
1) The content written in the optional area must not exceed one video frame. However, this is not the case only in the case of full mode recording of character information.
2) In the optional area, not only general users can optionally record accompanying data, but also the manufacturer can record desired accompanying data. The area where the accompanying data by the general user is recorded is called the common optional area, and the area where the accompanying data by the manufacturer is recorded is called the manufacturer's optional area. The common optional area is always provided before the manufacturer's optional area in one video frame . In other words, when the Maker CODE PACK is recorded in the optional area, the maker's optional area is secured until the end of one video frame thereafter.
Note that what is written in the optional area is arbitrary, but the number of times of writing the same pack is defined only in the case of SUBCODE having a low error correction capability.
[0072]
3) The compatibility of the contents of the main area and common optional area must be guaranteed between each manufacturer and VTR set.
4) Digital VTRs are classified into option-compatible VTRs and option non-competing VTRs.
5) All digital VTRs must write data in all main and optional areas.
6) Non-option VTRs must write NO INFO packs in all optional areas.
[0073]
7) The optional VTR can record desired data in the optional area while satisfying the following recording requirements.
a. Common Optional Area Recording Requirements
(1) At the time of original recording, the NO INFO pack is recorded on the front without being sandwiched. A NO INFO pack is recorded in the remaining area.
(2) Each manufacturer can freely set the contents, position, number of times, and order of recording.
{Circle around (3)} Data that records the same pack continuously, such as TEXT and TELETEXT, is recorded without losing continuity (other types of packs are not sandwiched).
[0074]
b. Maker's Optional Area Recording Requirements
(1) When providing the manufacturer's optional area, use only the pack with the header of the packer FXh (where X = 0, 1, 2,..., E), starting with the MAKER CODE pack.
(2) A manufacturer must not record more than one manufacturer's option. For example, as shown in [1] of FIG. 35, it is not a violation of the rules to record the same recorded contents repeatedly, but the manufacturer uses the same Maker CODE pack as shown in [2] of FIG. Recording different optional data is illegal and is not allowed. It is to be noted that recording different optional data using different MAKER CODE packs as shown in [3] in this figure does not violate the rules.
[0075]
8) All VTRs must read all the contents of the main area and perform necessary processing during playback.
9) The non-option VTR outputs the contents of the optional area at the time of playback without knowing.
10) The option-compatible VTR must read all the contents of the optional area during playback. (To ensure compatibility, it is prohibited to read only some areas)
[0076]
11) An optional VTR must perform the necessary processing for optional data that can be recorded by the VTR among the data read from the optional area at the time of reproduction, but when reproducing optional data that cannot be recorded by the VTR. The processing in is a set matter.
For example, in the case of a VTR that records and reproduces only pack A in the common optional area, all common optional areas are searched during reproduction to search for pack A.
At this time, considerable processing is also performed for multiple writing, and data is determined at the end of one video frame.
When a pack other than pack A and NO INFO pack is found, how to handle it is a set matter.
In addition, regarding the processing of reproduction data in the manufacturer's optional area, how to handle the manufacturer's option of its own manufacturer code and the manufacturer's option other than its own manufacturer code is a set matter.
[0077]
(8) Application ID system
Although the recording format of the digital VTR has been described above, this format is basically designed so that products can be easily developed as various digital signal recording / reproducing apparatuses other than the digital VTR. The ID data APT, AP1 to AP3 appearing in the above description of the format and the ID data APM recorded in the MIC enable the development to such various digital signal recording devices. These ID data are collectively called application IDs.
[0078]
Therefore, a supplementary explanation of this application ID system will be given next.
Note that the above application ID is not an ID that determines an application example of a digital VTR, but merely an ID that determines the data structure of the area of the recording medium. As described above, APT and APM have the following meanings: Yes.
APT ... Determines the data structure on the track.
APM: Determines the data structure of the MIC.
[0079]
That is, first, the data structure on the track in this digital signal recording / reproducing apparatus is defined by the value of APT. That is, the track after the ITI area is divided into several areas according to the value of APT, as shown in FIG. 36, the position on these tracks, the SYNC block configuration, the ECC configuration for protecting data from errors, etc. The data structure is uniquely determined. Further, each area has an application ID that determines the data structure of the area. The meaning is as follows.
Application ID of area n... Determines the data structure of area n.
[0080]
The application ID on the tape has a hierarchical structure as shown in FIG. That is, the area on the track is defined by the APT which is the original application ID, and AP1 to APn are further defined in each area. The number of areas is defined by APT. In FIG. 37, it is written in two layers, but if necessary, a layer may be further provided thereunder. By designating the values of APT, AP1 to APn in this way, the specific signal processing configuration of the digital signal recording / reproducing apparatus and the use of the apparatus are specified.
[0081]
The APM which is the application ID in the MIC has only one layer, and the same value as the APT is written by the digital signal recording / reproducing apparatus.
With this application ID system, the above-mentioned digital VTR can be used as it is with its cassette, mechanism, servo system, ITI area generation and detection circuit, etc., and completely different product groups such as data streamers and multi-track digital audio tape recorders. It is possible to make something like In addition, even if one area is decided, the contents can be further defined by the application ID of the area, so that when the value is a certain application ID, it is video data, and when it is another value, video / audio data, or computer data. Thus, a very wide range of product development is possible.
[0082]
Next, a specific example when the value of the application ID is designated will be described.
First, FIG. 38 shows the situation when APT = 000. At this time, area 1, area 2, and area 3 are defined on the track. The position on the track, the SYNC block configuration, the ECC configuration for protecting data from errors, the gap for guaranteeing each area, and the overwrite margin for guaranteeing overwriting are determined. Further, each area has an application ID that determines the data structure of the area. The meaning is as follows.
[0083]
AP1... The data structure of area 1 is determined.
AP2... The data structure of area 2 is determined.
AP3... The data structure of area 3 is determined.
Then, when the application ID of each area is 000, it is defined as follows.
[0084]
AP1 = 000: Image compression recording method Consumer digital VTR audio, AAUX data structure
AP2 = 000: Image compression recording method Consumer digital VTR audio, AAUX data structure
AP3 = 000 ... Image compression recording system Consumer digital VTR subcode, ID data structure
That is, when an image compression recording system consumer digital VTR is realized, APT, AP1, AP2, AP3 = 000. At this time, naturally, APM is also 000.
[0085]
2. Digital VTR recording circuit
In the digital VTR, recording on a tape is performed in accordance with the recording format described above. Next, a specific configuration and operation of a recording circuit that performs such recording will be described.
The configuration of such a recording circuit is shown in FIG.
[0086]
In this figure, the input Y, RY, and RY component signals are supplied to the A / D converter 42, and the Y signal is also supplied to the sync separation circuit 44, where it is separated. The synchronized signal is supplied to the clock generator 45. The clock generator 45 generates a clock signal for the A / D converter 42 and the blocking shuffling circuit 43.
[0087]
The component signal input to the A / D converter 42 is A / D converted at a sampling frequency of 13.5 MHz for the Y signal and 13.5 / 4 MHz for the color difference signal. Of these A / D conversion outputs, only the data DY, DR and DB in the effective scanning period are supplied to the blocking and shuffling circuit 43.
[0088]
In the blocking / shuffling circuit 43, as described above, the effective data DY, DR, DB is converted into a block composed of 8 samples in the horizontal direction and 8 lines in the vertical direction, and further 4 blocks of DY, DR and DB. Each block is divided into a total of 6 blocks to increase the compression efficiency of image data and perform shuffling to distribute errors during reproduction, and then supplied to the compression encoding unit. .
[0089]
The compression encoding unit performs a DCT (Discrete Cosine Transform) on the input block data of 8 samples in the horizontal direction and 8 lines in the vertical direction, and estimates to estimate whether the result can be compressed to a predetermined data amount. 48 and a quantizer 47 that finally determines a quantization step based on the determination result and performs data compression using variable length coding. The output of the quantizer 47 is framed in the format described in FIG.
[0090]
The mode processing microcomputer 67 in FIG. 39 is a microcomputer having a man-machine interface with a human and operates in synchronization with the vertical synchronization frequency of the television signal. The signal processing microcomputer 55 operates closer to the machine and operates in synchronization with the drum rotation speed of 9000 rpm and 150 Hz.
[0091]
The pack data of each area of VAUX, AAUX, and SUBCODE is basically generated by the mode processing microcomputer, and the absolute track number stored in the “title end” pack or the like is generated by the signal processing microcomputer 55. Then, the process of fitting into a predetermined position is executed. The time code data stored in the SUBCODE is also generated by the signal processing microcomputer 55.
[0092]
These results are given to the interface VAUX IC 56, the SUBCODE IC 57, and the AAUX IC 58 that handle the microcomputer and the hardware. The VAUX IC 56 is combined with the output of the framing circuit 49 by the combiner 50 in a timely manner. The SUBCODE IC 57 generates AP3, the SID that is the ID of the SUBCODE, and the SUBCODE pack data SDATA.
[0093]
On the other hand, the input audio signal is converted into a digital audio signal by the A / D converter 51. Note that, when AD conversion of the video signal and the audio signal is performed, it is necessary to provide an LPF corresponding to the sampling frequency before the sampling circuit, although not shown in this figure. The A / D converted audio data is subjected to data distribution processing by the shuffling circuit 52 and then framed into the format described in FIG. At this time, the AAUX IC 58 generates AAUX pack data, estimates the timing, and packs them in a predetermined place in the audio SYNC block by the synthesis circuit 54.
[0094]
The generator 59 generates each ID part of AV (Audio / Video), pre-SYNC, and post-SYNC. Here, AP1 and AP2 are also generated and inserted into a predetermined ID part. The output of the generator 59 and ADDATA (AUDIO DATA), VDATA (VIDEO DATA), SID (SUBCODE ID), and SDATA (SUBCODE DATA) are switched by the first switching circuit SW1 with timing.
[0095]
The output of the first switching circuit SW1 is added with a predetermined parity in the parity generation circuit 60 and supplied to the random number conversion circuit 61 and the 24/25 conversion circuit 62. Here, the randomizing circuit 61 randomizes the input data in order to eliminate the DC component of the data. Further, the 24/25 conversion circuit 62 performs processing for adding a pilot signal component by adding 1 bit for every 24 bits of data, and precoding processing (partial response class IV) suitable for digital recording.
[0096]
The data thus obtained is supplied to the synthesizer 63, where the audio, video and SUBCODE SYNC patterns generated by the A / V SYNC and SUBCODE SYNC generator 64 are synthesized. The output of the synthesizer 63 is supplied to the second switching circuit SW2. The ITI data output from the ITI generator 65 and the amble pattern output from the amble pattern generator 66 are also supplied to the second switching circuit SW2. These random number generating circuit 61, 24/25 conversion circuit 62, synthesizer 63, and switch SW2 constitute a channel encoder.
[0097]
The ITI generator 65 is supplied with APT, SP / LP, and PF data from the mode processing microcomputer 67. The ITI generator 65 fits these data in a predetermined position of the TIA and supplies the data to the second switching circuit SW2. Therefore, the amble pattern and ITI data are added to the output of the synthesizer 63 by switching the switching circuit SW2 at a predetermined timing. The output of the second switching circuit SW2 is amplified by recording amplifiers 201 and 204, and recorded on a magnetic tape (not shown) by a minus azimuth recording head 202 and a plus azimuth recording head 203.
[0098]
The mode processing microcomputer 67 performs mode management of the entire digital VTR. The third switching circuit SW3 connected to the microcomputer is an external switch of the VTR main body, and is a group of switches for instructing various operations other than the recording operation and the reproducing operation. A recording mode setting switch is also included. The setting result by the switch group is detected by the mode processing microcomputer 67 and is given to the signal processing microcomputer 55, the MIC microcomputer 69, and the mechanical control microcomputer by communication between microcomputers.
[0099]
The series of recording operations described above are performed in cooperation with the mechanical control microcomputer or signal processing microcomputer 55 and the ICs in charge of each part, with the mode processing microcomputer 67 as the center.
The MIC microcomputer 69 is a microcomputer for MIC processing. Here, pack data, APM, and the like in the MIC are generated and supplied to the MIC 68 in the cassette with the MIC (not shown) via the MIC contact (not shown).
[0100]
3. Digital VTR playback circuit
Next, details of the reproduction circuit of the digital VTR will be described with reference to FIGS. 40 and 41. FIG.
In FIG. 40, the weak signal reproduced from the magnetic tape (not shown) by the reproducing heads 991 and 994 is amplified by the head amplifiers 992 and 993 and applied to the equalizer circuit 71. The equalizer circuit 71 performs reverse processing of emphasis processing (for example, partial response class IV) performed to improve electromagnetic conversion characteristics between the magnetic tape and the magnetic head during recording.
[0101]
The clock extraction circuit 72 extracts the clock CK from the output of the equalizer circuit 71. This clock CK is supplied to the A / D converter 73, and the output of the equalizer circuit 71 is converted into a digital value. The 1-bit data thus obtained is written into the FIFO 74 using the clock CK.
This clock CK is a temporally unstable signal including a jitter component of the rotary head drum. However, since the data itself before A / D conversion also includes a jitter component, there is no problem in sampling itself. However, when extracting image data or the like from this time, the time axis is adjusted using the FIFO 74 because it cannot be extracted unless the data is stable in time. That is, writing is performed with an unstable clock, but reading is performed with a stable clock SCK from a self-excited oscillator (not shown) using a crystal oscillator or the like. The depth of the FIFO 74 is set so as not to be read faster than the input speed of input data.
[0102]
The output of each stage of the FIFO 74 is applied to the SYNC pattern detection circuit 75. Here, the SYNC pattern of each area is switched by the timing circuit 79 by the fifth switching circuit SW5. The SYNC pattern detection circuit 75 has a flywheel configuration. Once the SYNC pattern is detected, it is checked whether or not the same SYNC pattern comes again after a predetermined SYNC block length. For example, if it is correct three times or more, it is regarded as true so that false detection is prevented. The depth of the FIFO 74 needs to be several minutes.
[0103]
When the SYNC pattern is detected in this manner, the shift amount is determined as to which part of the FIFO 74 can be extracted from the output of each stage, so that the shift amount is determined. Based on this, the fourth switching circuit SW4 is closed. Then, necessary bits are taken into the SYNC block determination latch 77. Thereby, the fetched SYNC number is taken out by the SYNC number extracting circuit 78 and supplied to the timing circuit 79. Since the read SYNC number indicates which position on the track the head is scanning, the fifth switching circuit SW5 and the sixth switching circuit SW6 are switched accordingly.
The circuits 72 to 75 and 77 to 79 constitute a so-called time base collector (TBC).
[0104]
The sixth switching circuit SW6 is switched to the lower side when the head is scanning the ITI area, and the ITISYNC pattern is removed by the subtractor 80 and applied to the ITI decoder 81. Since the ITI area is coded and recorded, the APT, SP / LP, and PF data can be extracted by decoding the ITI area. These data are given to the mode processing microcomputer 82. The mode processing microcomputer 82 is connected to a seventh switching circuit SW7 which is a switch group for inputting various commands such as the SP / LP mode. The mode processing microcomputer 82 determines the operation mode and the like of the entire digital VTR, and performs system control of the entire set in cooperation with the mechanical control microcomputer 85 and the signal processing microcomputer 100 in FIG.
[0105]
The mode processing microcomputer 82 is connected to an MIC microcomputer 83 that manages APM and the like. Information from the MIC 84 in the cassette with MIC (not shown) is given to the MIC microcomputer 83 via the MIC contact switch (not shown), and performs the MIC processing while sharing the role with the mode processing microcomputer 82. . Depending on the set, the MIC microcomputer 83 may be omitted and the mode processing microcomputer 82 may perform the MIC process.
[0106]
When the head is scanning the audio area, the video area, or the SUBCODE area, the sixth switching circuit SW6 is switched to the upper side. After the SYNC pattern of each area is extracted by the subtracter 86, it is passed through the 24/25 reverse conversion circuit 87, and further added to the reverse random number conversion circuit 88 to return to the original data string. The data thus extracted is added to the error correction circuit 89.
[0107]
In the error correction circuit 89, error data is detected and corrected using the parity added on the recording side, but the data that could not be removed is attached with an ERROR flag and output. Each data is switched and output by the eighth switching circuit SW8. The AV ID, pre-SYNC, and post-SYNC extraction circuit 90 extracts the A / V area, SYNC number and track number stored in the pre-SYNC and post SYNC, and SP / LP signals stored in the pre-SYNC. . These are given to the timing circuit 79 and used to generate various timings. In the extraction circuit 90, AP1 and AP2 are also extracted and supplied to the mode processing microcomputer 82 for checking. When AP1 and AP2 = 000, the operation is performed normally, but when the value is other than that, a warning operation such as warning processing is performed.
[0108]
For SP / LP, the mode processing microcomputer 82 performs a comparative study with that obtained from ITI. In the ITI area, SP / LP information is written three times in the TIA area, and the majority is taken only there to improve reliability. Pre-SYNC has 2 SYNCs for audio and video respectively, and a total of 4 SP / LP information is written. Here, too, take the majority vote and improve reliability. If they do not match, the ITI area is preferentially adopted.
[0109]
VDATA output from the eighth switching circuit SW8 is divided into video data and video-accompanying data by the ninth switching circuit SW9 shown in FIG. The video data is given to the deframing circuit 94 together with an error flag.
The deframing circuit 94 performs reverse conversion of the framing on the recording side, and grasps the nature of the data packed therein. Then, when there is an error that cannot be captured in a certain data, it understands how it affects other data, so propagation error processing is performed here. As a result, the ERROR flag becomes a VERROR flag that newly includes a propagation error. In addition, even if there is an error in the data which is not important for image reproduction, the deframing circuit 94 also performs a process for deleting the error flag by performing a work on the image data.
[0110]
The video data is returned to the data before compression through the inverse quantization circuit 95 and the inverse compression circuit 96. Next, the deshuffling / deblocking circuit 97 returns the data to the original image space arrangement. Only after the data is returned to the real image space, the image can be repaired based on the VERROR flag. That is, for example, processing is performed in which image data one frame before is always stored in the memory, and the image block in error is substituted with the previous image data.
[0111]
Now, after deshuffling, the data is divided into three systems, DY, DR, and DB. The D / A converters 101 to 103 return the analog components to Y, RY, and BY. The clock at this time is 13.5MH for Y _Z , RY, BY about 3.375MH _Z It is.
The three signal components obtained in this way are synthesized by the Y / C synthesis circuit 104, and further synthesized by the synthesizer 105 with the composite sync signal from the sync signal generation circuit 93, and output from the terminal 106 as a composite video signal.
[0112]
ADATA output from the eighth switching circuit SW8 is divided into audio data and audio-accompanying data by the tenth switching circuit SW10 shown in FIG. The audio data is given to the deframing circuit 107 together with the ERROR flag.
[0113]
The deframing circuit 107 performs reverse conversion of framing on the recording side, and grasps the nature of data packed therein. And when there is an error that cannot be captured in a certain data, it understands how it affects other data, so propagation error processing is performed here. For example, in the case of 16-bit sampling, since one data is a unit of 8 bits, one ERROR flag becomes an AERROR flag newly including a propagation error.
[0114]
The audio data is returned to the original time axis by the next deshuffling circuit 108. At this time, the audio data is repaired based on the previous AERROR flag. That is, processing such as holding a previous value that substitutes the sound immediately before the error is performed. If the error period is too long and the repair is not effective, the sound itself is stopped by taking a measure such as muting.
[0115]
After such treatment, the analog value is returned to the analog value by the D / A converter 109 and output from the analog audio output terminal 110 while taking a timing such as lip sync with the image data.
The VAUX and AAUX data separated by the ninth switching circuit SW9 and the tenth switching circuit SW10 are subjected to preprocessing such as majority processing while referring to error flags in the VAUX IC 98 and AAUX IC 111, respectively. .
[0116]
The SUBCODE area ID data SID and pack data SDATA output from the eighth switching circuit SW8 are provided to the SUBCODE IC 112, and here, preprocessing such as majority processing is performed with reference to the error flag. The preprocessed data is then given to the signal processing microcomputer 100 to perform a final reading operation. Errors that could not be removed in the preprocessing are given to the signal processing microcomputer 100 as VAUXER, SUBER, and AAUXER, respectively.
[0117]
Here, the SUBCODE IC 112 extracts AP3 and APT, passes them to the mode processing microcomputer 82 via the signal processing microcomputer 100, and checks them. The mode processing microcomputer 82 determines the APT value based on the APT from the ITI and the APT from the SUBCODE, and performs an operation such as warning processing when the value is not “000”. When AP3 = 000, the operation is performed as usual, but when the value is other than that, a warning operation such as a warning process is performed.
[0118]
4). Recording and playback of accompanying data
Finally, the recording and reproduction of the accompanying data in the digital VTR as the subject of the present invention will be described in detail by dividing the recording process of VAUX pack data, recording of AAUX pack data, recording of SUBCODE data, and reproduction of pack data. To do.
[0119]
(1) Recording VAUX pack data
First, the VAUX pack data recording circuit in FIG. 39 will be described. The overall flow will be described with reference to FIG. First, pack data to be stored in the VAUX is generated by the mode processing microcomputer 67. It is converted into serial data by the P / S conversion circuit 118 and sent to the signal processing microcomputer 55 according to the communication protocol between the microcomputers. Here, the S / P conversion circuit 119 returns the parallel data to the buffer memory 123 via the switch 122.
[0120]
The header part at the beginning of every 5 bytes of the sent pack data is extracted by the pack header detection circuit 120, and it is checked whether the pack requires an absolute track number. If necessary, the switch 122 is switched to store 23-bit absolute track number data from the absolute track number generation circuit 121.
[0121]
Here, the circuit 119 is a serial I / O in the microcomputer, the circuits 120, 121, and 122 are configured by a microcomputer program, and the circuit 123 is a RAM in the microcomputer. In this way, the processing of the pack structure uses a microcomputer that is advantageous in terms of cost because the processing time of the microcomputer can be met in time even if it is not bothered by hardware.
The data stored in the buffer memory 123 in this manner is sequentially read in accordance with an instruction from the write side timing controller 125 of the VAUX IC 56. At this time, the switch 124 is switched so that the first six packs are for the main area and the subsequent 390 packs are for the optional area.
Here, the FIFO 126 for the main area has a storage capacity of 30 bytes (for 6 packs), and the FIFO 127 for the optional area has a storage capacity of 1950 bytes (for 390 packs).
[0122]
VAUX is stored in the in-track SYNC numbers 19, 20, and 156 as shown in [1] of FIG. When the track number in the frame is 1, 3, 5, 7, 9 and + azimuth, the main area is in the first half of the SYNC number 19, and the track number in the frame is 0, 2, 4, 6, 8, -There is a main area in the second half of SYNC number 156 in azimuth. FIG. 43 [2] depicts this in a single video frame. Thus, the timing signal nMAIN = “L” is the main area. Such a signal is generated by the read side timing controller 129, the switch 128 is switched, and the output is passed to the synthesis circuit 50.
[0123]
When only one type of VAUXTR pack or Closed Caption pack is recorded in the sixth pack of each main area, the main pack is written into the FIFO memory 126 once per frame, and when nMAIN = “L” The data in the main area FIFO 126 is repeatedly read 10 times (525/60) or 12 times (625/50).
VAUX TR pack and Closed in the 6th pack of each main area
When recording a plurality of types of Caption packs, six main packs are written in the main area FIFO 126 for each track pair. That is, writing to the FIFO memory 126 is performed five times per frame. When nMAIN = “L”, the data in the main area FIFO 126 is read twice. This is because, as shown in FIG. 32, the VAUX main area always has the same value for each track pair. When nMAIN = “H”, the optional area FIFO 127 is read. This is read only once per video frame.
[0124]
Actually, since a plurality of TR packs and Closed Caption packs are often recorded, normally, six main pack data for each track pair are written in the FIFO 126 for the main area. Each track pair is an actual track pair writing time, and data for one track is written once in that time. This is because the time required for processing by the signal processing microcomputer 55 and the mode processing microcomputer 67 is not enough to write just one track, so that the time for two tracks is ensured as described above.
[0125]
By using the VAUX IC 56 described above, 60 main packs and 390 optional packs can be recorded per frame. In particular, such a large number of packs can be recorded for optional data. Is limited to, for example, the case where a large amount of character information is recorded using the TEXT pack or the TELETEXT pack described above, or the case where data of a desired line is recorded using a line pack. In some cases, it can be considered that there is almost no need to record such a large number of optional packs. That is, in the case of a set for a normal user, as an optional data amount to be recorded in one frame, about 39 packs for one track are sufficient, and as many as 390 packs like the VAUX IC 56 shown in FIG. Use of a large-capacity optional area FIFO memory is not desirable in terms of cost.
[0126]
Therefore, an embodiment of the VAUX data recording circuit according to the present invention which is configured to record a maximum of 39 packs of common optional data or manufacturer's optional data for each frame as VAUX optional data will be described below. In this VAUX data recording circuit, optional data recorded in one track is repeatedly recorded as it is in other tracks, thereby recording optional data for one frame period.
[0127]
In this case, in the above-mentioned regulations concerning recording of optional data, the a. (1) stipulates that packs to be recorded in the optional area should be packed in the leading direction and recorded in the middle, such as NO INFO packs, and not divided. For this reason, for example, 30 optional packs are recorded, the remaining 9 packs are filled with NO INFO packs to form optional data for one track, and the optional data for 39 packs are repeatedly recorded on each track. Cannot be adopted. Therefore, in this embodiment, instead of this NO INFO pack, among the packs disclosed in FIG. 23 and FIG. 24, all the data portions other than the item portion of the specific pack are invalidated (all 1). The configuration is such that recording is performed in an area of one track optional space. Thereby, it is possible to repeatedly record optional data without violating the above-mentioned rules. Further, even if the VTR set is a VTR that performs processing corresponding to the pack, the contents of the pack are invalid, so no operation is performed and no malfunction occurs. That is, this pack functions as a dummy pack.
[0128]
As such a dummy pack, when the optional data to be recorded is common optional data, a pack in which a large item falls within the range of “0000” to “1110” is used. For example, a pack shown in [1] in FIG. 44 is used. This is the TIMER shown in [1] of FIG.
The ACT S / S pack has all 1 contents, and this pack is originally recorded in the MIC and is not necessarily recorded on the tape, so it can be used as a dummy pack. Is preferred. Even if there is a VTR set that performs processing corresponding to the TIMER ACT S / S pack recorded on the tape, the contents are regarded as no information, so that no malfunction occurs.
[0129]
If the optional data to be recorded is manufacturer's optional data, use a pack whose major item is “1111” (excluding the MAKER CODE pack and NO INFO pack) (therefore, the optional data recording described above). (1) of the recording requirements for the manufacturer's optional area in the regulations regarding As a specific example, for example, as shown in [2] of FIG. 44, a pack in which the item is FEh and the data is all 1 is used.
[0130]
Based on the above thinking, a recording pattern of VAUX data when a memory having a storage capacity of 39 packs is adopted as the optional area FIFO 127 in FIG. 42 will be described with reference to FIGS. 45 and 1 to 3. To do.
First, FIG. 45 shows an example of a recording pattern when the optional data to be recorded is only common optional data. In this figure, only the recording of 34 common optional packs is instructed by the user. Based on this instruction, the PACK NO. 34 common optional packs of 0 to 33 are generated, and as the remaining 5 common optional packs, the dummy pack whose pack header is 03h is automatically generated, and a total of 39 dummy packs are generated. After the common optional pack is written in the FIFO memory 127, the VAUX optional data for one frame is recorded by being read repeatedly 10 times.
[0131]
Next, an example in which the optional data to be recorded consists of both common optional data and manufacturer's optional data will be described with reference to FIG.
This figure shows a recording pack in the case where the recording of 36 common optional packs is instructed by the user and the recording of 34 manufacturer's optional packs is also instructed by the manufacturer.
[0132]
That is, in this figure, the pack recording on each track numbered from 0 to 5 is performed in the same manner as in FIG. 45, but immediately before the optional data recording operation on the track number 6 track, the FIFO memory 127 The contents are rewritten with 39-pack maker's optional data. The manufacturer's optional data for 39 packs includes the five dummy whose header is FEh in addition to the 34 manufacturer's optional packs starting with the MAKER CODE pack (MP) specified by the manufacturer. The pack is automatically generated in the mode processing microcomputer.
As is clear from this figure, the optional data is recorded in a track pair unit so that the same data is recorded in a track pair so that the main pack and the optional pack for one track can be transmitted at the same timing in the microcomputer. Can be processed easily.
[0133]
FIG. 2 shows an example of a recording pattern when the optional data to be recorded is only manufacturer's optional data. This figure is an example of a recording pattern in the case where the user does not input the recording instruction of the common optional pack and only the recording of the manufacturer's optional data for 31 packs is instructed by the manufacturer. A manufacturer's optional pack is generated, and 8 dummy packs are automatically generated. A total of 39 manufacturer's optional packs are repeatedly recorded over 10 tracks.
[0134]
Finally, FIG. 3 shows a recording pattern when there is no optional data to be recorded. In this case, as shown in this figure, 39 NO INFO packs are automatically generated in the mode processing microcomputer and repeatedly recorded over 10 tracks.
45 and FIGS. 1 to 3, the packs A to E and F1 to F5 are all represented as having input data, but the main pack portion to which no input data is actually given, that is, In some cases, a main area portion in which the main pack is not recorded is generated, and a NO INFO pack is automatically generated and recorded in such a portion by the mode processing microcomputer.
[0135]
In the embodiment described above, when both the common optional data and the manufacturer's optional data exist as optional data to be recorded, the manufacturer's optional data is stored in the FIFO before recording the optional data in the track of track number 6. 42, the mode operation microcomputer 67 determines whether or not both common optional data and manufacturer's optional data exist in FIG. 42, and this determination output is used as the VAUX IC 56. This is realized by supplying to the WRITE side timing controller 125.
[0136]
In the embodiment described above, the TIMER ACT S / S pack is used as a dummy pack used in the common optional area. However, other packs can be used as a matter of course. For example, in the pack table shown in FIG. 23 and FIG. 24, in the packs of the large items “000” to “1110”, if the packs are not shaded, the data of the data parts PC1 to PC4 is stored. Of course, it is possible to use all 1 no information as a dummy pack, but it does not cause any trouble even if it is used as it is as a dummy pack as it is without correct information.
[0137]
In these figures, a half-dotted pack can be used as a dummy pack if its data portions PC1 to PC4 are replaced with no information. However, for the TEXT pack of the small item “1001”, it is necessary that the TEXT HEADER pack is not recorded in the common optional area, and each line of the small items “0001” to “0110” in the large item of LINE. For the pack, it is necessary that the LINE HEADER pack is not recorded in the common optional area.
In addition, as a dummy pack used in the manufacturer's optional area, a pack obtained by replacing the data portion of an arbitrary pack of small items “0001” to “1110” in the large item of SOFT MODE with all 1s may be adopted as a dummy pack. it can.
[0138]
By recording the VAUX optional data by the method as described above, the capacity of the optional data memory can be reduced. However, since the pack data amount handled by the mode processing microcomputer is also reduced, the circuit scale of the microcomputer is reduced. It can be reduced, and communication line control between microcomputers can be done easily.
In this embodiment, a dummy pack and a NO INFO pack necessary for the mode processing microcomputer are generated. Instead of using such a generation method, a main pack memory and an optional pack in the VAUX IC are used. It is possible to further reduce the circuit scale of the mode processing microcomputer by generating these packs in the reset circuit for resetting the pack memory.
[0139]
Next, an embodiment of a VAUX data recording circuit configured based on this idea will be described with reference to FIGS.
In the configuration of FIG. 4, the VAUX data is input to the VAUX pack memory 726 in the VAUX IC 56 via the buffer memory 626 in the signal processing microcomputer 55, where it is stored in the buffer memory 627 in the signal processing microcomputer. Writing is performed by the write control circuit 625 controlled by the detection output G (pack header data) of the pack header detection circuit 120. Prior to this writing operation, the contents of the memory 726 are reset by the reset circuit 721. The reset circuit 721 is controlled by a control circuit 628 to which the detection output G of the pack header detection circuit 120 is input. Further, the read operation from the memory 726 is executed by the output of the read control circuit 629 which is controlled according to the pack header data in the buffer memory 627.
[0140]
The operation of the VAUX IC 56 will be described with reference to the detailed circuit configuration of FIG.
As shown in FIG. 5, the VAUX pack memory 726 includes a main pack memory 727, a common optional data FIFO memory 728, and a manufacturer's optional data FIFO memory 729. The input pack data from the signal processing microcomputer 55 is a switch. It is stored in these memories 727 to 729 via 124.
[0141]
The main pack memory 727 includes a FIFO memory for storing the main packs A to E and a memory for storing the main packs F1 to F5 in FIG. 32. The common optional data FIFO memory 728 and the manufacturer's optional data FIFO 729 are each 1 It has a storage capacity of 39 packs so that track data can be stored. The pack data input from the signal processing microcomputer is first input to the switch 124, and the data J indicating the header of the input pack is also input from the buffer memory 627 to the write control circuit 625 at the same time. The circuit supplies a switch control signal corresponding to the pack header data J to the switch 124. By this switching control signal, the pack data input is separated into a main pack, a common optional pack, and a manufacturer's optional pack according to the value of the pack header, and written into the memories 727 to 729.
[0142]
In the writing operation of these packs, the main pack is rewritten every frame, and the optional pack is rewritten whenever new optional pack data is input.
Prior to these write operations, the memories 727 to 729 are reset in advance by reset signals (7) to (9) from the reset circuit 721. In this case, the NO INFO pack output from the NO INFO pack generation circuit 730 in the reset circuit 721 is used as the reset signal (7) to the main pack memory 727, and the reset signal ▲ to the FIFO memory for the manufacturer's optional data 729 For 9 ▼, a dummy pack using the pack of the item FEh output from the dummy pack generation circuit 724 in the reset circuit 721 is used.
[0143]
Further, as a reset signal to the common optional data FIFO memory 728, when no optional pack exists in the pack data input to the VAUX pack memory 726, the NO INFO pack from the NO INFO pack generation circuit 730 is used. When an optional pack exists, a dummy pack using the above-described TIMER ACT S / S pack output from the dummy pack generation circuit 725 in the reset circuit 721 is used.
[0144]
That is, among the packs A to E and F1 to F5 in the main pack memory 727, the contents of the pack storage area in which no data is input from the signal processing microcomputer remain the NO INFO pack, and the manufacturer's optional data FIFO memory 729 In FIG. 5, the pack storage area in which no data is input from the signal processing microcomputer remains the dummy pack of the pack header FEh. Further, in the common optional data FIFO memory 728, when no optional pack is input to the VAUX pack memory 726, the NO INFO pack remains stored in all areas, and when any optional pack is input. The pack storage area of the FIFO memory 728 where no data is input from the signal processing microcomputer remains the dummy pack of the pack header 03h.
[0145]
The operation of switching the reset signal supplied to the FIFO memory 728 described above based on the presence / absence of optional data is performed by the determination output K of the determination circuit 628 to which the pack header data G in the signal processing microcomputer in FIG. 4 is input. Is done by.
[0146]
The pack data read operation from the memories 727 to 729 in which the pack data is stored as described above is performed in accordance with the data format described with reference to FIG. 32 and the read control signals (4) to (6) and switches from the read control circuit 629. This is executed by 128 switching control signals. In this case, the pack header data J is input to the read control circuit 129, and the read control circuit 129 determines whether the common optional data and the manufacturer's optional data exist in the VAUX pack memory 726 based on the data J. And a read operation according to the determination result is performed.
[0147]
That is, when the manufacturer's optional data is not included in the pack data input to the VAUX pack memory 726 from the signal processing microcomputer, the pack data is only tracked from the main pack memory 727 and the common optional data FIFO memory 728 for each track. Reading is repeated, for example, a reading output for one frame as shown in FIG. 45 is obtained. However, when not only the manufacturer's optional data but also the common optional data is included, as is clear from the above description, all the optional areas are filled with NO INFO packs (see FIG. 3).
[0148]
Next, a description will be given of the read operation when both the common optional data and the manufacturer's optional data are included in the input pack data from the signal processing microcomputer. In this case, the read control circuit 129 converts the data J into the data J described above. Based on this, the presence of both of these optional data is recognized. At this time, the read control circuit 129 executes the read control operation similar to that shown in FIG. In each track, a control operation is performed so that only the data in the main pack memory 727 and the data in the manufacturer's optional data FIFO memory 729 are repeatedly read out for each track.
[0149]
Thereby, for example, read data for one frame as shown in FIG. 1 is obtained.
If the optional data input from the signal processing microcomputer is composed only of the manufacturer's optional data, the read control circuit 129 recognizes this based on the above-mentioned data J, and based on this recognition, the 1 frame period Then, repeated reading is executed for each track from only the main pack memory 727 and the FIFO memory for manufacturer's optional data 729. Thereby, for example, read data for one frame as shown in FIG. 2 is obtained.
[0150]
In the circuit configuration shown in FIG. 5, the read control circuit 629 determines whether the common optional data FIFO memory 728 and the maker's optional data as shown in FIGS. 45 and 1 to 3 according to the presence / absence of the common optional data and the maker's optional data. The read operation from the data FIFO memory 729 is switched as appropriate, but instead of this, as shown in FIG. 1, the track numbers 0 to 5 are always used regardless of the presence or absence of these two types of optional data. May be configured to read the optional data from the common optional data FIFO memory 728 and to read the optional data from the manufacturer's optional data FIFO memory 729 at track numbers 6 to 9. However, in this case, when there is no optional pack to be input to the VAUX pack memory 726, the reset signal input to the FIFO memory 729 is also switched to the NO INFO pack similarly to the FIFO memory 728.
[0151]
Further, the timing for switching the optional pack read operation by the read control circuit 129 from the memory 728 to the memory 729 is not limited to the position of the track number 6 as shown in FIG. You may make it switch by a position.
[0152]
Next, generation of VAUX pack data in the mode processing microcomputer will be described.
FIG. 6 shows a VAUX pack data generation unit in the mode processing microcomputer. First, the circuit is roughly divided into a main area and an optional area. The circuit 131 is a main area data collection and generation circuit. Data as shown in the figure is received from the digital bus or tuner, and a data group as shown at 139 is generated internally. This is assembled into a bit byte structure of the main pack, a pack header is added by the switch 132, and input to the P / S conversion circuit 118 via the switch 136.
[0153]
The optional area data collection and generation circuit 133 receives, for example, TELETEXT data and a program title from a tuner, and generates pack data storing these. The VTR set individually determines which optional area is recorded. The pack header is set by the circuit 134, added by the switch 135, and input to the P / S conversion circuit 138 via the switch 136. These timings are performed by a timing adjustment circuit 137.
Again, as described above, the circuit 118 is a serial I / O in the microcomputer, and the circuits 131 to 137 are configured by a microcomputer program.
[0154]
As described above, when the VAUX data recording circuit is configured using a memory having a storage capacity of 39 packs as the FIFO 127 in the VAUX IC 56 in FIG. 42, the main pack and the common optional pack instructed by the user. In the mode processing microcomputer, dummy packs and NO INFO packs are generated in the mode processing microcomputer according to the number of each and the number of manufacturer's optional packs, and these packs are also passed through the P / S conversion circuit 138 together with the main pack and optional pack. Is output.
[0155]
(2) AAUX pack data recording
Next, the generation and recording operation of AAUX pack data will be described. The AAUX pack data generation unit in the mode processing microcomputer is configured as shown in the figure, and the generation of AAUX pack data in this circuit is the generation of the VAUX pack data described above. Done in the same way. The AAUX data generated by the AAUX pack data generation unit is supplied to the AAUX IC 58 in the drawing via the signal processing microcomputer 55.
[0156]
The AAUX IC 58 is configured as shown in FIG. 8. Of the AAUX pack data input from the signal processing microcomputer, 6 main packs are sent to the main area FIFO 602 and 30 optional packs are sent to the optional area FIFO 601. Written by the side timing controller 605. Thereafter, according to the format shown in FIG. 30 by the READ side timing controller 604, six main packs are repeatedly read out from the FIFO 602 ten times, and optional packs are sequentially read out from the FIFO 601 in three packs per track. In this AAUX IC, the storage capacity of the optional area FIFO 601 is set to 1/10 (that is, 3 packs in this case) as in the case of the VAUX IC, and 3 packs of AAUX optional data are stored. The circuit scale may be reduced by repeatedly recording data in each of the ten tracks.
[0157]
(3) Recording SUBCODE data
Next, recording of SUBCODE data, in particular, the SUBCODE IC 57 in FIG. 39 will be described.
FIG. 9 shows a circuit of the SUBCODE IC 57. In this figure, reference numerals 630 to 636 denote circuit configurations for generating the SUBCODE ID section SID, and reference numerals 637 to 640 denote circuit configurations for generating the SUBCODE pack data SDATA.
[0158]
As shown in the figure, the generation of the SID includes a counter 630 for generating an FR code, an INDEX ID generation circuit 631, an SKIP ID generation circuit 632, and a PP for generating AP3, APT, and TAG codes as application IDs. The configuration includes an ID generation circuit 633, an absolute track number generation circuit 634, a SYNC block number generation circuit 635, switches S1 to S3, and a timing circuit 636 that controls switching of these switches.
[0159]
The counter 630 is set to a value of 1 at the head position of the frame by a frame pulse input, and a value of 0 is obtained when the value obtained by counting the track switching signal supplied from the mechanical control microcomputer becomes a value indicating the track of track number 6. Is output. The switching terminal of the switch S1 is switched according to the value of the SYNC block number, 0,1-4,5,6-10,11.
Also, from the absolute track number generation circuit 634, the upper, middle, and lower 8-bit data of the 24-bit absolute track number code are sequentially extracted for each SYNC block via the switch S2.
Then, by switching the switching terminal of the switch S3 according to the bit position in the SYNC block, the SID shown in FIG. 21 is generated and output.
[0160]
Further, in the generation of the SUBCODE pack data SDATA, the main pack and the optional pack are sent from the signal processing microcomputer to the FIFOs 637 and 638 via the switch S4 as shown in the figure at the start timing of the frame and the start timing of the track of track number 6. Is written. Then, these FIFO memories are alternately read for each track according to the pattern shown in FIG.
Note that the memory capacity can be reduced by using the circuit configuration for generating SDATA shown in FIG. In FIG. 10, FIFOs 641 to 643 having a storage capacity for three packs are provided, and after writing the main pack and the optional pack as shown in the figure, the target SDATA is read by reading according to the pattern shown in FIG. Can be obtained.
[0161]
(4) Pack data playback processing
Next, pack data reproduction processing in FIGS. 40 and 41 will be described.
In the VAUX IC 98, AAUX IC 111, and SUBCODE IC 112 in FIG. 41, the same pack data is recorded a plurality of times for the main pack, so that the error part is supplemented with other non-error data. The part of the ERROR flag is no longer an error. However, since optional packs other than SUBCODE are recorded once, they cannot be supplemented, and errors remain as VAUXER and AAUXER. The output pack data from each of these ICs is further subjected to propagation error processing, data repair processing, and the like by analogizing the correct value of the error portion from the context of each data pack in the signal processing microcomputer 100. The determination result is given to the mode processing microcomputer 82 and used as a material for determining the behavior of the entire set.
[0162]
Next, a VAUX IC 98 and a pack data reproduction circuit in the signal processing microcomputer 100 will be described by taking VAUX as an example. Here, a configuration example using a simple processing method in which the preprocessing performed in the IC 98 is not majority processing but is not written in a memory in the case of an error will be described. FIG. 11 shows a circuit example of the VAUX IC 98. First, the VAUX pack data from the switching circuit SW9 is distributed to the main area memory 145 and the optional area FIFO 148 by switching the switch 141 at the timing of nMAIN = “L” in FIG.
[0163]
The pack data in the main area is read by the pack header detection circuit 143 and the switch 144 is switched. Then, data is written into the main area memory only when it is not ERROR. This memory has a 9-bit configuration, and the shaded portions in the figure are error flag storage bits.
As an initial setting of the main area memory, the value of the sixth main pack data storage area is set to all 1 (= no information) for every two tracks, and the first to fifth main pack data storage areas All the contents are set to all 1 (= no information) for each video frame. If it is ERROR, nothing is done. If it is not ERROR, the data is written and 0 is written in the error flag. Since the same data is recorded in units of two tracks in the sixth pack of the main area, the place where the error flag is set to 1 at the end of the two tracks is finally recognized as an error. For the first to fifth main packs, an error flag = 1 is recognized as an error at the end of one video frame.
[0164]
Since the optional area is basically written once, the ERROR flag is directly written in the optional area FIFO 148 together with the data. These are sent to the signal processing microcomputer 100 via switches 146 and 147 switched by the read side timing controller 149.
However, as described above, in the recording of VAUX data, in the VTR set adopting the method in which the optional data of one track for 39 packs is repeatedly recorded in other track periods, the optional pack data is also recorded in the main pack. Error correction based on multiple writing similar to data is possible. That is, an optional data memory having a recording capacity of 39 packs is used instead of the optional area FIFO 148, and all the contents are cleared to all 1 for each video frame. And when the optional data is composed only of common optional data or only manufacturer's optional data, as with the first to fifth main packs described above, when 10 repetitive writing over one frame period is completed. The error-corrected optional pack data is output to the signal processing microcomputer.
[0165]
If the optional data is composed of both common optional data and manufacturer's optional data (this is recognized from the header of the optional pack in each track number 0 and track number 6), the track number 5 When the optional data in the track has been written into the optional data memory, the error-corrected common optional pack data is output to the signal processing microcomputer, and the contents of the memory are immediately cleared to track numbers 6-9. Prepare for the writing of the truck manufacturer's optional pack. Then, when the writing of the pack data in the track of track number 9 is finished, the manufacturer's optional pack data with the error corrected is output to the signal processing microcomputer.
[0166]
The signal processing microcomputer 100 performs analysis from the received pack data and error flag. The processing operation in the signal processing microcomputer 100 will be described with reference to FIG. In this figure, the pack header identification circuit 150 sorts pack data (VAUXDT) sent from the VAUX IC 98 and stores it in the memory 151. This does not distinguish between the main area and the optional area.
In the case of a pack in the main area, like the VAUX IC 98, when the error flag “1” is set in VAUXER, the writing process is not performed. As a result, the repair can be made with a value at least one video frame before. Since the content of the main area is considered to be very correlated with the value one video frame before, there is no particular problem even if this processing is substituted.
[0167]
On the other hand, in the case of an optional area pack, since it is considered that there is no correlation with the value of one video frame before, error propagation processing is performed for each pack.
This method is basically performed by changing to "no information pack" in which all data is FFh if there is an error in the pack data of 5 bytes fixed length. However, individual pack correspondence is also required. . For example, in the case of a “teletext” pack in which teletext data is stored, it can be easily replaced with a telext pack header even if there is an error in the pack header between the packs because of the continued relationship of the packs. Even if there is an error in the data part, if there is no error in the pack header, the pack is not changed to “pack without information”. This is because the restoration of the teletext data is left to the parity check of the teletext decoder, so that the data is left as it is even if it is recognized as an error.
[0168]
That is, in the digital VTR, although the description is omitted in the reproduction circuit of FIG. 41, the pack data having a large amount of data such as text data, teletext data, etc. Each of the signals is transferred from the signal processing microcomputer 100 to a dedicated data processing circuit to perform more efficient error correction and reduce the load on the mode processing microcomputer 82.
[0169]
The data prepared by the processing in the signal processing microcomputer 100 as described above no longer has an error flag. These are converted into serial data by the P / S conversion circuit 152 and sent to the mode processing microcomputer 82 according to the communication protocol between the microcomputers. Here, the S / P conversion circuit 153 returns the data to parallel data and performs pack data decomposition analysis.
Here, the circuits 150 and 155 and the switch 154 are configured by a microcomputer program, the memory 151 is a memory inside the microcomputer, and the circuits 152 and 153 are serial I / Os inside the microcomputer.
[0170]
The AAUX pack data and the SUBCODE pack data are also reproduced in the same manner as the above VAUX pack data. However, error correction based on multiple writing is performed for the optional pack of SUBCODE.
In the decomposition analysis of the pack data in the mode processing microcomputer 82, the pack data is analyzed based on the determined pack header, and various control information, display information, etc. obtained as an analysis result are displayed in the respective control circuits, display Supply to circuit etc.
[0171]
【The invention's effect】
The capacity of the memory used for the optional pack processing circuit can be saved, and the circuit scale of the microcomputer for processing the optional pack can be reduced.
In the optional pack reproduction process, error processing based on multiple writing can be performed to restore data more accurately.
[Brief description of the drawings]
FIG. 1 is a diagram showing an example of a recording pattern of a VAUX recording area in which common optional data and manufacturer's optional data are recorded in an embodiment of the present invention.
FIG. 2 is an example of a recording pattern when only manufacturer's optional data is recorded in a VAUX recording area in the same embodiment.
FIG. 3 is a diagram showing a VAUX recording area when optional data is not recorded.
FIG. 4 is a diagram showing a VAUX data recording circuit according to another embodiment of the present invention.
FIG. 5 is a diagram showing details of a VAUX IC in the VAUX data recording circuit.
FIG. 6 is a diagram showing a VAUX data generation circuit in the mode processing microcomputer.
FIG. 7 is a diagram showing an AAUX data generation circuit in the mode processing microcomputer.
FIG. 8 is a diagram showing a configuration of an AAUX IC for a recording system.
FIG. 9 is a diagram illustrating a configuration of a recording system SUBCODE IC.
FIG. 10 is a diagram showing another configuration example of the pack data processing circuit in the SUBCODE IC.
FIG. 11 is a diagram showing a configuration of a reproduction-system VAUX IC.
FIG. 12 is a diagram showing a VAUX data processing circuit in a reproduction-system signal processing microcomputer;
FIG. 13 is a diagram showing a recording format of one track of a digital VTR.
FIG. 14 is a diagram illustrating a structure of a pre-SYNC block and a post-SYNC block.
FIG. 15 is a diagram for explaining the framing format of AUDIO and the structure of one SYNC block;
FIG. 16 is a diagram illustrating blocking of image data for one frame.
FIG. 17 is a diagram illustrating a VIDEO framing format to which an error correction code is added.
FIG. 18 is a diagram illustrating a configuration of a VIDEO buffering unit and a 1SYNC block;
FIG. 19 is a diagram illustrating the structure of a SUBCODE area for one track.
FIG. 20 is a diagram illustrating the structure of an ID part of a SYNC block in an AUDIO area and a VIDEO area.
FIG. 21 is a diagram illustrating the structure of an ID part of a SYNC block in a SUBCODE area.
FIG. 22 is a diagram showing a basic structure of a pack.
FIG. 23 is a diagram illustrating types of packs having large items “0000” to “0100”.
FIG. 24 is a diagram illustrating types of packs having large items “0101” to “1111”.
FIG. 25 is a diagram illustrating details of an AAUX SOURCE pack, an AAUX SOURCE CONTROL pack, an AAUX REC DATE pack, an AAUX REC TIME PACK, and an AAUX REC TIME BINARY GROUP pack.
FIG. 26 is a diagram showing details of an AAUX CLOSED CAPTION pack, a VAUX SOURCE pack, a VAUX SOURCE CONTROL pack, a VAUX REC DATE pack, and a VAUX REC TIME pack.
FIG. 27 is a diagram showing details of a VAUX REC TIME BINARY GROUP pack, a CLOSED CAPTION pack, a VAUX TR pack, a TITLE TIME CODE pack, and a CHAPTER START pack.
FIG. 28 is a diagram showing details of a TIMER ACT S / S pack, a Maker CODE pack, a TP HEADER pack, a CONTROL TEXT HEADER pack, and a CONTROL TEXT pack.
FIG. 29 is a diagram showing details of a LINE HEADER pack, a LINE Y pack, and a NO INFORMATION pack.
FIG. 30 is a diagram illustrating the structure of an AAUX area for one frame.
FIG. 31 is a diagram illustrating the structure of a VAUX area for one track.
FIG. 32 is a diagram illustrating a pack structure of a VAUX area for one frame.
FIG. 33 is a diagram for describing multiple writing of pack data in a SUBCODE area.
FIG. 34 is a diagram for describing multiple writing of pack data in a SUBCODE area in a SECAM digital VTR.
FIG. 35 is a diagram for explaining a rule regarding recording of optional data.
FIG. 36 is a diagram for describing definition of a track format by APT.
FIG. 37 is a diagram illustrating a hierarchical structure of application IDs.
FIG. 38 is a diagram illustrating a format on a track when an application ID is “000”.
FIG. 39 is a diagram showing a recording circuit of a digital VTR.
FIG. 40 is a diagram showing a configuration of a part of a digital VTR reproducing circuit.
FIG. 41 is a diagram showing the configuration of another part of the digital VTR playback circuit.
42 is a diagram for explaining a VAUX pack data generation circuit of the recording system of the VTR. FIG.
FIG. 43 is a diagram for explaining a main area on a recording track.
FIG. 44 is a diagram illustrating a structure of a DUMMY PACK.
FIG. 45 is a diagram showing an example of a recording pattern in a VAUX recording area in which only common optional data is recorded in the embodiment of the present invention.
[Explanation of symbols]
55, 100 ... signal processing microcomputer, 56, 98 ... VAUX IC,
57, 112 ... SUBCODE IC, 58, 111 ... AAUX IC,
67, 82 ... mode processing microcomputer,
125,605 ... WRITE side timing controller,
126,602 ... FIFO for main area,
127, 148, 601 ... FIFO for optional area,
129, 604 ... READ side timing controller,
721 ... Reset circuit, 724, 725 ... Dummy pack generation circuit,
726 ... VAUX pack memory, 727 ... Main pack memory,
728 ... FIFO for common optional data,
729 ... FIFO for manufacturer's optional data,
730 ... NO INFO pack generation circuit,

Claims (4)

In a television signal recording apparatus for recording a television signal using a recording medium,
Generating means for generating image data from the input television signal;
Ancillary data relating to the image data, the ancillary data generating means for generating the ancillary data consisting of basic data and additional data;
By scanning the recording medium, a plurality of recording tracks per frame of the television signal is formed on the recording medium, and an image data recording area provided in each recording track of the plurality of recording tracks, basic A recording means for recording the image data, the basic data, and the additional data, respectively, in an additional data recording area and an additional data recording area,
The recording means repeats additional data having a data amount equal to the recording capacity of an additional data recording area provided in one recording track in each additional data recording area of a plurality of recording tracks in one frame. Additional data consisting of the same data content is recorded in each additional data recording area in the recording track constituting the track pair and repeatedly recorded in the additional data recording area. When the amount of data is less than the recording capacity of the additional data recording area formed for each track, the additional data is recorded in the leading direction of the additional data recording area, and the remaining additional data recording area Record the dummy pack in
The accompanying data is configured in units of packs of a certain amount of bytes having item codes, and the additional data recorded in the additional data recording area in one recording track is the additional data to be recorded. Including a pack representing the contents and a dummy pack,
The dummy pack is a pack in which the value “1” is stored in all data portions other than the data portion in which the item code is stored so as to invalidate all operations. Recording device.   The recording means adds additional data when the amount of additional data recorded repeatedly in the additional data recording area is smaller than the recording capacity of the additional data recording area formed for each track. The code indicating common optional data is stored in the data part where the item code is stored as a dummy pack in the additional data recording area in the leading direction of the target data recording area, and the data part other than the item code A code indicating manufacturer's optional data is stored in the data portion in which the value “1” is stored in the first pack and / or the item code, and the value “1” is stored in the data portion other than the item code. The television signal recording apparatus according to claim 1, wherein the second pack is recorded. In a television signal recording method for recording a television signal using a recording medium,
An image data generation step of generating image data from the input television signal;
Ancillary data relating to the image data, the ancillary data generating step for generating the ancillary data composed of basic data and additional data;
By scanning the recording medium, a plurality of recording tracks per frame of the television signal is formed on the recording medium, and an image data recording area provided in each recording track of the plurality of recording tracks Recording step for recording the image data generated in the image data generation step and the basic data and additional data generated in the accompanying data generation step, respectively in the automatic data recording area and the additional data recording area And
In the recording process, additional data having a data amount equal to the recording capacity of an additional data recording area provided in one recording track is repeated in each additional data recording area of a plurality of recording tracks in one frame. Additional data consisting of the same data content is recorded in each additional data recording area in the recording track constituting the track pair and repeatedly recorded in the additional data recording area. If the amount of data is less than the recording capacity of the additional data recording area formed for each track, the additional data is recorded in the front of the additional data recording area in the front direction, and the remaining additional data recording area is recorded. Record the dummy pack,
The accompanying data is configured in units of packs of a certain amount of bytes having item codes, and the additional data recorded in the additional data recording area in one recording track is the additional data to be recorded. Including a pack representing the contents and a dummy pack,
The dummy pack is a pack in which the value “1” is stored in all data portions other than the data portion in which the item code is stored so as to invalidate all operations. Recording method.   The recording step adds additional data when the amount of additional data recorded repeatedly in the additional data recording area is less than the recording capacity of the additional data recording area formed for each track. The code indicating common optional data is stored in the data part where the item code is stored as a dummy pack in the additional data recording area in the leading direction of the target data recording area, and the data part other than the item code A code indicating the manufacturer's optional data is stored in the data portion in which the value “1” is stored in the first pack and / or the item code, and the value “1” is stored in the data portion other than the item code. 4. The television signal recording method according to claim 3, wherein the second pack is recorded.

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