JPH0821228B2 - Level detector peak detection circuit - Google Patents

Description

The present invention relates to a digital audio tape recorder (DA).
The present invention relates to a peak detection circuit of a level decoder which is applied to a recording / reproducing apparatus such as T) and which generates level data representing the size of a data string and detects the maximum value (peak value) thereof.

2. Description of the Related Art In a recording / reproducing apparatus, level data is used as an index indicating the size of data to be handled. For example, in the case of DAT, a circuit (hereinafter referred to as a level decoder) for decoding the level of 16-bit PCM data generated for each L / R channel per sample is shown in FIGS. 4 and 5. There is something like the one shown. FIG. 4 is an example of a level decoder that generates 15-bit level data, and FIG. 5 is a level that generates 8-bit level data from 16-bit PCM data using the conversion rule shown in FIG. It is an example of a decoder.

Here, the operation of FIG. 4 will be described. In FIG. 4, the 16-bit PCM data loaded in the shift register 401 is serially output in order from the most significant bit (MSB) by the shift clock 32Fs. Here, Fs is a sampling period of PCM data, and 32Fs is a bit rate of 32 bits / Fs. The data serially output is the absolute value generating means 402.
Is converted into 15-bit absolute value data by exclusive OR of the most significant bit which is a sign bit and the subsequent bits. This absolute value data is the shift register 403
In the serial / parallel conversion in the update control means 40
It is held in the flip-flops 405 and 406 for each of the L and R channels according to the output of 4. The selector 407 selects one of the held data having the same channel as the output of the absolute value generating means 402 by the select signal SL. The selected data is loaded into the shift register 408 at a predetermined timing by the load signal LD2 and serially output to the update control means 404 at the bit rate of the shift lock 32Fs. On the other hand, the update control means 404 compares the output of the absolute value generating means 402 with the output of the shift register 408, and when the output of the absolute value generating means 402 is larger than the output of the shift register 408, the flip-flop corresponding to the channel of the data. Latch clock CK1 or C
It outputs K2 and updates the data held in the flip-flop. As a result, the latches 405 and 406 always hold the maximum value (peak value) of the level data of the L and R channels. The held peak value is output to the microcomputer bus according to the request from the system microcomputer, and then reset by the clear signal CLR. The input level data is generated as described above, and the peak value thereof is detected.

Next, the operation of FIG. 5 will be described. In FIG. 5, the 16-bit PCM data loaded in the shift register 501 is
Serial output is performed from the least significant bit (LSB) by the shift clock 64Fs. At that time, the most significant bit (MSB), which is a sign bit, is re-input from the serial input SI into the shift register 501 to add 16 more sign bits to the 16-bit PCM data from the output QF.
2-bit serial data is output. The serially output data is converted into absolute value data by taking an exclusive OR with the most significant bit which is a sign bit in the absolute value generating means 502. This absolute value data is serial / parallel converted in the shift register 503,
The lower 4 bits are input to the latch 507, and the upper 11 bits are input to the latch signal generating means (LGN) 505. On the other hand, the binary counter 504 is initialized by the reset signal RST at a predetermined timing and then counts up in synchronization with the shift of the data in the shift register 503. The latch signal generation means 505 detects the timing when the upper 10 bits have the same sign (“0” or “1”) from the input data and outputs the latch signal Gu. As a result, the upper 4 bits of the 8-bit level data in FIG. 6 are latched.
Holds at 6. Further, the latch signal generation means 505 outputs the latch signal Gl by detecting the timing when the upper 11 bits of the input data have the same sign. This gives 8
The lower 4 bits (“ABCD” in FIG. 6) of the bit level data are held in the latch 506. The 8-bit level data generated as described above is a flip-flop.
According to the output of the update control means 508, L.
R is held for each channel. The selector 511 selects and outputs to the flip-flops 509 and 510, among the held data, those of the same channel as the data held in the latches 506 and 507. The update control means 508 is a latch 506, 507.
Of the latch 50 and the output of the selector 511 are compared.
When the output of 6,507 is larger, the latch clock CK1 or CK2 is output to the flip-flop 509 or 510 holding the data of the corresponding channel to update the data held in the flip-flop. As a result, the flip-flops 509 and 510 always hold the maximum value (peak value) of each of the L and R channels. The held peak value is output to the microcomputer bus according to the request from the system microcomputer, and then reset by the clear signal CLR. The input level data is generated as described above, and the peak value thereof is detected.

As described above, in the configuration of the conventional level decoder shown in FIG. 4 and FIG. 5, the absolute value of the input is shifted by the shift register, and serial / parallel conversion is performed to obtain 15-bit level data or continuous data from the upper level. Level data compressed to 8 bits is generated according to the length of "0".

However, in the conventional configuration shown in FIG. 4, since the level decoder has 15 bits, a large amount of data is transferred to the system microcomputer, and it takes a long time to transfer the data to the system microcomputer. It has become a burden on the user and requires a large memory area for data conversion. Further, in the conventional configuration shown in FIG. 5, since the level data is 8 bits, the problem that the conventional configuration shown in FIG. 4 has is solved, but as shown in FIG. There was a problem that the resolution of the data became low, and the level near 0 dB, which requires high resolution especially for recording and editing, cannot be expressed sufficiently.

The present invention solves the above-mentioned conventional problems. The peak of a level decoder capable of generating 8-bit level data that has a sufficiently high resolution in the vicinity of 0 dB and does not burden the processing and memory of the system microcomputer. It is intended to provide a detection circuit.

In order to solve this problem, a peak detection circuit of a level decoder according to claim 1 of the present invention converts N-bit parallel data into serial data and outputs the serial data in order from the least significant bit (LSB). And a first shift register that re-inputs and holds the most significant bit (MSB) output to the serial input until the next parallel data is loaded, and a second shift register that converts the serial data to parallel data An absolute value generating means for converting the output of the second shift register into an absolute value; a counter for counting the number of shifts of the data in the second shift register; and an output of the counter and an output of the absolute value generating means. Selector means for selecting according to the output of the counter, latch means for holding the output of the absolute value generating means and the output of the selector means, and the absolute value generating Latch signal generation means for generating the latch signal of the latch means according to the output of the means, flip-flop means for holding the output of the latch means, and the outputs of the latch means and the flip-flop means are compared in magnitude, and the result is compared. Accordingly, there is provided update control means for performing update control of the data held in the flip-flop means.

Further, the peak detection circuit of the level decoder according to claim 2 of the present invention converts the N-bit parallel data into serial data and outputs the serial data in order from the least significant bit (LSB), and
At that time, the first shift register that re-inputs and holds the least significant bit (MSB) output to the serial input until the next parallel data is loaded, and the absolute value that converts the output of the first shift register to the absolute value Generating means, a second shift register for performing serial / parallel conversion on the output of the absolute value generating means, a counter for counting the number of shifts of data in the second shift register, an output of the counter and the second shift register. Selector means for selecting the output according to the output of the counter, latch means for holding the output of the second shift register and the output of the selector means, and the latch of the latch means according to the output of the second shift register. Latch signal generating means for generating a signal, flip-flop means for holding the output of the latch means, latch means and flip-flop means The outputs compares, in which a update control means for updating control data held in the flip-flop means in accordance with the result.

Action The present invention has the above-described configuration, and N input from the outside is input.
Bit data is shifted in the LSB direction at a bit rate of at least 1.5 times N, and the absolute value of the input data is converted into 8 bits by serial / parallel conversion by adding the most significant bit that is the sign bit in advance. Generate a compressed version. When the absolute value is larger than the specified value, the compression conversion rule is changed to generate level data with a fine resolution for data near 0 dB, and in other cases, the absolute value is continuous from the upper level. The data compressed according to the length of “0” is used as the level data.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the configuration when the peak detection circuit of the level decoder according to the first embodiment of the present invention is applied to a DAT, and FIG. 2 is the level decoder according to the second embodiment of the present invention. It is a block diagram which shows the structure when a peak detection circuit is applied to DAT. Also, Figure 3 shows a 16-bit PC.
FIG. 9 is a schematic diagram showing a conversion rule for generating 8-bit level data with high resolution near 0 dB from M data.

In FIG. 1, 101 is a first shift register, 102 is a signal processing unit, 103 is a second shift register, 104 is an absolute value generating means, 105 is a counter, 106 is a latch signal generating means,
107 and 108 are latch means, 109 is update control means, 110 and 111 are flip-flop means, and 112 and 113 are selector means.

Next, the operation of FIG. 1 will be described. The 16-bit 2-channel PCM data input from the outside is loaded into the first shift register 101 by the load signal LOAD, and then the shift clock of 64Fs (Fs is a sampling frequency, that is, 64Fs is a 64-bit sampling period). The bit rate is shifted downward. At that time, the first
By re-inputting the most significant bit corresponding to the sign bit output to the output Q0 of the shift register 101 of the serial input SI to 16 bits per loaded channel
After the PCM data, 16 more sign bits are the first
The output QF of the shift register 101 is serially output. Per channel with sign bit added in this way
The 32-bit PCM data is input together with the PCM data in the signal processing unit 102. Validity flag VFLG (PCM
Interpolation processing is performed based on the data indicating the validity of the data). The output is converted into parallel data by the second shift register 103 and input to the absolute value generating means 104. The absolute value generation means 104 generates a 15-bit absolute value by exclusive OR of the most significant bit of the input data and the other bits. Of the 15-bit absolute value data, the upper 3 bits are input to the input B of the selector 113, the upper 11 bits are input to the latch signal generating means (LGN) 106, and the lower 4 bits are input to the latch 108. The latch signal generation means 106 generates the latch signal Gl of the latch 108 at the timing when the upper 10 bits of the input have the same sign, and generates the latch signal Gu of the latch 107 at the timing when the upper 11 bits of the input have the same sign. Binary counter 105 reset signal R
After being initialized by the ST at a predetermined timing, it counts up in synchronization with the shift of the data in the shift register 103. The selector 113 outputs Q0 to Q3 (input A) of the binary counter 105 according to the most significant bit Q3 of the output of the binary counter 105 input to the select signal SEL, the upper 3 bits of the absolute value generating means 104 and the output of the binary counter 105. Select one of the combined Q3 (input B). That is, the input A is selected when the output Q3 is "0", and the input B is selected when the output Q3 is "1". As a result, the latch 107 holds the upper 4 bits of the 8-bit level data in FIG. 3, and the latch 108 holds the lower 4 bits of the 8-bit level data (“ABCD” in FIG. 3).
The 8-bit level data generated as described above is held in the flip-flops 110 and 111 for each of the L and R channels according to the output of the update control means 508. The selector 112 selects one of the data held in the flip-flops 110, 111 from the same channel as the data held in the latches 107, 108 by the select signal SEL and outputs it. The update control means 109 is the output of the latches 107 and 108 and the selector.
If the output of the latch 107 or 108 is larger than the output of the 112, the latch clock CK1 or CK2 is output to the flip-flop 110 or 112 that holds the data of the corresponding channel, and the data held in the flip-flop is output. To update. As a result, the flip-flops 110 and 112
Always holds the maximum value (peak value) of each L / R channel. The held peak value is output to the system bus in response to a request from the system microcomputer and then reset by the clear signal CLR. The input level data is generated as described above, and the peak value thereof is detected. Further, in FIG. 2, 201 is a first shift register, 202 is an absolute value generating means, 204 and 212 are selector means, 205 is a counter, 206 is a latch signal generating means, 20
7, 208 is a latch means, 209 is an update control means, and 210, 211 are flip-flop means.

Next, the operation of FIG. 2 will be described. Two-channel PCM data of 16 bits per channel input from the outside is loaded into the first shift register 201 by the load signal LOAD, and then shifted in the lower direction at the bit rate of the shift clock 64Fs. At that time, the first shift register
By re-inputting the most significant bit corresponding to the sign bit output to the output Q0 of 201 to the serial input SI as in the case of Fig. 1, additional 16 bits are added after the 16-bit PCM data loaded per channel. Is added and the serial bit is output from the output QF of the first shift register 201. The absolute value generating means 202 is the shift register 2
Level data is generated using the serial input from 01 and the most significant bit (MSB), and this is serial / parallel converted by the shift register 203. Operation of generating 8-bit level data using the parallel-converted absolute value data and the output of the binary counter 205 that counts the number of shifts of the data in the shift register 203, and holding the peak value for each L / R channel Are omitted because they are the same as those described in the embodiment of FIG.

As described above, according to claim 1 of the present invention, N-bit parallel data is converted into serial data and output from the least significant bit (LSB), and at that time, the most significant data is loaded. A first shift register that re-inputs and holds the bit (MSB) output to the serial input, a second shift register that converts serial data to parallel data, and an output of the second shift register to an absolute value Absolute value generating means, a counter for counting the number of shifts of data in the second shift register, selector means for selecting the output of the counter and the output of the absolute value generating means according to the output of the counter, and the absolute value Latch means for holding the output of the generating means and the output of the selector means, and a latch means for generating the latch signal of the latch means according to the output of the absolute value generating means. H signal generation means, flip-flop means for holding the output of the latch means, and comparison of the outputs of the latch means and the flip-flop means, and update control for updating the data held in the flip-flop means according to the result. By including the control means, the level data can be generated by selecting a part of the absolute value or the counter value according to the magnitude of the absolute value of the PCM data. That is,
As shown in FIG. 3, the upper 7 bits of the absolute value are adopted as the level data only when the PCM data is larger than the predetermined value, and in other cases, the level data is obtained by using the counter value and a part of the absolute value. By generating it, 8-bit level data with high resolution near 0 dB can be generated. As a result, the amount of data transferred to the system microcomputer is small, the processing and memory load of the system microcomputer are reduced, and it is possible to detect the level in the vicinity of 0 dB, which requires high resolution, more finely. Furthermore, the shift register that performs serial / parallel conversion of PCM data that has undergone signal processing can also be used for format conversion for outputting the data to the D / A converter or the output signal generation unit of the digital audio interface standard. As a result, the cost can be reduced.

According to claim 2 of the present invention, the N-bit parallel data is converted into serial data to convert the least significant bit (LS
A first shift register for outputting in sequence from B) and re-inputting and holding the most significant bit (MSB) output to the serial input until the next parallel data is loaded;
The absolute value generating means for converting the output of the first shift register into an absolute value, the second shift register for performing serial / parallel conversion of the output of the absolute value generating means, and the shift number of the data in the second shift register A counter to count,
Selector means for selecting the output of the counter and the output of the second shift register according to the output of the counter;
Latch means for holding the output of the shift register and the output of the selector means, a latch signal generating means for generating the latch signal of the latch means according to the output of the second shift register, and a flip-flop for holding the output of the latch means. The absolute value generation means 202, by providing a comparison means for comparing the outputs of the latch means and the flip-flop means, and updating control of the data held in the flip-flop means according to the result. Since the absolute value of the PCM data can be generated by the exclusive-OR of the serial data output from the shift register and its sign bit, the circuit is smaller than the absolute value generating means 104 in claim 1 of the present invention. The same effect can be achieved on a scale. Further, as a part of the function of the signal processing unit 102 according to the first aspect of the present invention, a combination of configurations such as generating absolute value of PCM data as in the second aspect of the present invention is possible.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration when the peak detection circuit of the level decoder according to the first embodiment of the present invention is applied to a DAT, and FIG. 2 is the peak detection of the level decoder according to the second embodiment of the present invention. FIG. 4 is a block diagram showing a configuration when the circuit is applied to a DAT, and FIG. 3 is a schematic diagram showing a conversion rule for generating 8-bit level data with high resolution near 0 dB from 16-bit PCM data. The figure is a block diagram showing the configuration of a peak detection circuit of a conventional level decoder that generates 15-bit level data from the absolute value of 16-bit PCM data. FIG. 6 is a block diagram showing the configuration of a peak detection circuit of a conventional level decoder for generating level data, and FIG. 6 is a schematic diagram showing a conventional conversion rule for generating 8-bit level data from 16-bit PCM data. FIG. 101 ... First shift register, 102 ... Signal processing unit, 103 ...
Second shift register, 104 ... Absolute value generating means, 105 ... Counter, 106 ... Latch signal generating means, 107, 108 ... Latch means, 109 ... Update control means, 110, 111 ... Flip-flop means, 112, 113 ... Selector means, 201 ... First Shift register, 202 ... absolute value generation means, 203 ... second shift register, 204, 212 ... selector means, 205 ... counter, 206 ... latch signal generation means, 207, 208 ... latch means, 209 ... update control means, 210, 211 ... flip-flop means

Claims (2)

[Claims] 1. N-bit parallel data is converted into serial data and output in order from the least significant bit (LSB), and at that time, the most significant bit (MSB) output is serially input until the next parallel data is loaded. A first shift register for re-inputting and holding the same, a second shift register for converting the serial data into parallel data, and an absolute value generating means for converting the output of the second shift register into an absolute value, A counter for counting the number of shifts of the data in the second shift register; a selector means for selecting the output of the counter and the output of the absolute value generating means according to the output of the counter; and the absolute value generating means. Latch means for holding the output and the output of the selector means, and a latch signal of the latch means according to the output of the absolute value generation means. Latch signal generation means, flip-flop means for holding the output of the latch means, and comparison of the outputs of the latch means and the flip-flop means, and update control of the data held in the flip-flop means according to the result is compared. A peak detection circuit of a level decoder having update control means for performing. 2. N-bit parallel data is converted into serial data and is output in order from the least significant bit (LSB), and the most significant bit (MSB) output is serialized until the next parallel data is loaded. A first shift register for re-inputting and holding the input, an absolute value generation means for converting the output of the first shift register into an absolute value, and a second serial / parallel conversion for the output of the absolute value generation means Shift register, a counter for counting the number of shifts of the data in the second shift register, and selector means for selecting the output of the counter and the output of the second shift register according to the output of the counter. Latch means for holding the output of the second shift register and the output of the selector means, and the latch according to the output of the second shift register. Latch signal generating means for generating the latch signal of the latch means, flip-flop means for holding the output of the latch means, and the outputs of the latch means and the flip-flop means are compared in magnitude, and the flip-flop means is used according to the result. And a peak detection circuit of a level decoder, which comprises update control means for controlling the update of the data held in.