JPH01314023A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain a circuit corresponding to the 16-bit mode and the 12-bit mode with a comparatively small scale by using a shift register required also for the 16-bit mode in common with the compression of the 12-bit mode. CONSTITUTION:The circuit consists of a shift register 1 converting serially a 1-word 16-bit parallel data, a data conversion circuit 2 generating a 4-bit from a high-order 8-bit in a 16-bit data and a shift control circuit 7 controlling the shift clock of the shift register 1. In case of the 16-bit mode, the data of the shift register 1 is outputted as it is and in case of the 12-bit mode, after the 16-bit data is shifted so that the highest-order bit among bits different from the most significant bit comes to specific bit location of the shift register 1, the 4-bit of the output of the data conversion circuit 2 and a prescribed 8-bit of the shift register 1 are synthesized to generate and output the 12-bit data. Thus, a circuit corresponding to both the 16-bit and 12-bit modes is obtained with a comparatively small circuit scale.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital signal processing circuit applied to a rotary head type digital audio tape recorder (hereinafter referred to as DAT), and in particular to a 16-bit mode and a 12-bit mode.
The present invention relates to a digital signal processing circuit configured to realize both bit modes.

[Conventional technology]

Conventionally, in a general DAT, when writing the output of an analog-to-digital conversion circuit (hereinafter referred to as A/D conversion circuit) to memory, the 16-bit serial output of the A/D conversion circuit is converted to 8-bit parallel data. ing. Third
The figure shows a circuit (hereinafter referred to as an A/D interface circuit) that converts this 16-bit serial data into 8-bit parallel data. In the figure, l is a 16-bit shift register (hereinafter referred to as shift register) with serial/parallel output, 41.42.43.44 is a 4-bit D type latch (hereinafter referred to as latch), and 51.52 is a buffer. , 6 is a memory data bus.

Next, the operation will be explained. The 16-bit serial data output from the A/D conversion circuit is held in the shift register l, converted into parallel data, and transferred to latches 41, 42, 43, .
The data stored in the 0th order 44 is outputted to the data bus 6 in 8-bit units. Control for outputting data to the data bus 6 in 8-bit units is performed by buffers 51 and 52, and by alternately setting BCKI and BCK2 to 01 (passing data), latches 41 and 42 are controlled, respectively.
, the data stored in latches 43 and 44 is output in units of 8 bits.

[Problem to be solved by the invention]

As described above, the conventional circuit supports only the 16-bit mode, but not the 12-bit mode.

Therefore, the present invention has been made to solve the above-mentioned problems, and is a digital signal processing circuit that supports both 16-bit mode and 12-bit mode and has a common circuit. The purpose is to obtain an A/D interface circuit.

[Means to solve the problem]

The digital signal processing circuit according to the present invention has 16 words per word.
It is equipped with a shift register that converts bit serial data into parallel data, a data conversion circuit that generates 4 bits from the upper 8 bits of 16-bit data, and a shift control circuit that controls the shift clock of the shift register. The data in the register is output as is, and in the 12-bit mode, the 16-bit data is shifted so that the most significant bit of the bits with a different value from the MSB is at a specific bit position in the shift register, and then the data conversion circuit 12-bit data is generated and output by combining the 4-bit output from the shift register with the predetermined 8-bit data from the shift register.

[Effect]

Since the digital signal processing circuit according to the present invention uses a shift register necessary for 16-bit mode as well as 12-bit compression, it is possible to realize a circuit compatible with 16-bit and 12-bit modes with a small circuit scale.

〔Example〕

Here, we will discuss the rules for compressing 16-bit data into 12-bit data standardized by DAT and the conversion of 12-bit audio data words (hereinafter referred to as words) into 8-bit audio data symbols (hereinafter referred to as symbols). Explain the rules.

First, the rules for compressing 16-bit data to 12 bits are shown in Fig. 4, and an explanatory diagram especially for positive polarity is shown in Fig. 5. Here, the compression rules will be explained along Fig. 5. . In Figure 5, "0" and "1" represent each bit of data, and the numbers shown indicate the bit positions of 16-bit data, with the least significant bit (hereinafter referred to as LSB) expressed as ■. Yes, the value is “0” in both cases
or l''.

The compression rule starts with the number of consecutive MSHs starting from the upper 8 bits of 16-bit data (1 to 1 for a% h)
8), the upper 4 bits of the 12-bit data are uniquely determined. Next, 8 bits are taken from the next bit whose polarity is inverted from the MSB, and these are taken as the lower 8 bits of the 12-bit data.

In this way, 16 bit data is compressed to 12 bits.

Next, the rules for converting 12-bit words into 8-bit symbols will be explained. The said rules are shown in FIG. In FIG. 6, one of the first two channel words is set to Al and the other to Bi, three symbols are created from the two channel words, and the upper 8 bits of each word are treated as one symbol. Shikaku Aiu,
Btu), and the lower 4 bits of each word are combined to generate one symbol (ABiffi).

Hereinafter, one embodiment of the present invention will be described based on the drawings.

In Fig. 1, l is a shift register, 2 is an encoder (data conversion circuit), and determines the upper 4 bits 82 to eO of 12-bit data from the number of O's excluding the MSB of the upper 8 bits of 16-bit data. . 31, 32.
33 and 34 are selectors for switching between 12-bit mode and 16-bit mode. 41, 42, 43, and 44 are latches, and 6 is a data bus connected to the memory. Buffers 51 and 52 control the output of the latch.

7 is a shift control circuit, EOR71, 0R72°AND
It consists of 73. Figure 2 shows a timing chart of the clock that operates this circuit. CHCK is the channel clock, "01 is the A channel, '1"
represents the B channel.

Next, the operation of the circuit having the above configuration will be explained.

First, the 16-bit serial data output from the A/D conversion circuit is transferred to shift register 1 using CLKl as a clock.
to hold. Here, the MSB of the 16-bit data is d
15, the next bit is held in d14, and so on, and the LSB is held in do.

In the case of 16-bit mode, selectors 31, 32, 33.
Select the B side with 35 and latch 16 bit data 41
, 42, 43, and 44, and buffer 51 for each 8 bits.
．． 52 to the data bus 6.

In addition, in the case of 12-bit mode, selector 31.32
, 33. Select side A at 34. First shift register l
Top 8 pits of A channel held in ) (d15~d
B) is input to the data conversion circuit 2, from which the upper 4 bits e3 to eO of 12-bit data are generated, and 1. is stored in latch 41.

Next, 8 bits from the bit next to the bit where the MSB is discontinuous
The bit is always at the same position (d13) in the shift register 1.
~d6), the data in shift register 1 is shifted upward using 5FCK as a clock, that is, the data in shift register 1 is shifted upward,
Shifting is stopped when the values of outputs d15 and d14 of shift register 1 are different. This operation is performed in Game) 71.72. If the values of d15 and d14 are different, gate 7
The output of 1 becomes "1", the gate 72 stops outputting 5FCK, and no clock is supplied to the shift register I, that is, the operation stops.For example, 16-bit data is ( Taking the case of C) as an example, after the shift is performed twice as shown in FIG. 7, the outputs d15 and d14 of the shift register I are inverted, so the shift is stopped here. The data from d13 to d6 at this time becomes the lower 8 bits of the 12-bit data. However, if the MSB occurs 8 or more times in a row (fh in Figure 5)
In the case of 1), the shift stops after 6 times. Then d1 at tt
3 to dlO are stored in the latch 42 and d9 to d6 are stored in the latch 43. Then, the upper 8 bits of the A channel stored in the latches 41 and 42 are outputted to the data bus 6 through the buffer 51 at t.

Next, in the case of the B channel, the upper 4 bits e3 to eQ of the 12-bit data are stored in the latch 41 at t, and shifted in the same way as in the case of the A channel.
Lo is stored in the latch 42 and d9 to d6 are stored in the latch 44. Therefore, the lower 4 bits of the A channel stored in the latch 43 and the lower 4 bits of the B channel stored in the latch 44, a total of 8 bits, are outputted to the data bus 6 through the buffer 52 in 1 hour. And B stored in latches 41 and 42
The upper 8 bits of the channel are output to the data bus 6 through the buffer 51 at t7.

[Effects of the Invention] As described above, according to the present invention, in a digital signal processing circuit applied to a DAT, etc., 16-bit 12
Since the shift register required for the 16-bit mode is also used for compression to bits, the circuit configuration can be reduced.
This has the effect of realizing a circuit compatible with both 16-bit mode and 12-bit mode.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an A/D interface circuit of a digital signal processing circuit according to an embodiment of the present invention, FIG. 2 is a timing chart of a clock that operates the circuit of FIG. 1, and FIG. Block diagram of conventional circuit,
Figure 4 is a diagram showing the data compression rules standardized in DAT, Figure 5 is an explanatory diagram of the data compression rules, and Figure 6 is a diagram showing the data compression rules standardized in DAT.
The figure shows the rules for converting words into symbols, and FIG. 7 shows the contents of the shift register in the case of (C1) in FIG. 6. ■...Shift register, 2...Data conversion circuit ,7
...Shift control circuit. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) Take m (m is a positive integer) bit data as input, and use it as m bits or compress p (m bits)
In a digital signal processing circuit that outputs data as bit data (a positive integer where p<m), there are two components: m positive integer) bits as input,
a data conversion circuit that outputs l (l is a positive integer such that l<n) bit data corresponding to the value of the n bits, and a bit having a different value from the most significant bit (hereinafter referred to as MSB) of the m bit data If present in the upper n bits, the most significant bit among the bits having a value different from the MSB is located at a predetermined bit of the shift register;
and a shift control circuit that shifts the data stored in the shift register so that the least significant bit of the upper n bits is located at a predetermined bit of the shift register if the data does not exist among the upper n bits, m When outputting bit data, the data stored in the shift register is output as is, and when outputting p-bit data, the l-bit of the data conversion circuit and the input m-bit data are controlled by the shift control circuit. A digital signal processing circuit characterized in that the lower (pl) bits following the predetermined bit of the shift register when shifted as described above are output as p-bit data.