JPH03198143A - Bus interface device and read-modified-write control system - Google Patents

Abstract

PURPOSE:To output data via an output latch at a higher speed than conventional by setting the output latch to a specific bit for each byte without changing the value of the data while this data fetched via a 1st data bus is outputted to a 2nd data bus. CONSTITUTION:In a read-modified-write operation state, an encoder 14, a decod er 11, and an 8-bit external code correction data bus 17 have the extended functions to correct the codes of a 64-bit external data bus 16. When data are outputted to the bus 16, the encoder 14 calculates the correction data on an 8-bit code and outputs this corrected data to the bus 17. Meanwhile the decoder 11 inputs the 8-bit code correction data via the bus 17 concurrently with the data inputted via the bus 16 of 64-bit and outputs the data to an input latch 12 after decoding. Thus the code is corrected for the bus 16. As a result, the data can be outputted via the latch 12 at a higher speed than conventional.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a bus interface device and a read-modify-write control system.Prior art Figure 4 shows a bus interface used in a conventional microprocessor. Although the configuration of the device is shown in FIG. 4, the bus interface device 30 is the decoder 11.
, input latch 12. , an output latch 33 . with an enable signal 18 . Encoder 14. Internal data bus 1 consisting of eight 8-bit data buses and external data bus 18 likewise consisting of eight 8-bit data buses. It consists of an external code correction data bus 17, and even if modules 19 other than the bus interface device 30 are connected to the internal data bus, the bus interface device 30 shown in FIGS. Although the data length is 64 bits and is divided into groups of 8 bits, each bit of the data is numbered in order from 0 to 63 (0th bit, 1st bit 1).
The 8 bits from the 63rd bit to the 56th bit are called the first group, and the 8 bits from the 55th bit to the 48th bit are called the second group 1660410901, and the 7th bit to the 0th bit. In this conventional example, the above 64-bit data is read from the external data bus 16, all 8 bits of the first group are rewritten to 1, and then the data is read from the external data bus 16 again. Let us consider the read/modify/write operation to write data to the external data bus 16 using the bus interface device shown in Fig. 4. Even if it indicates a read/modify/write operation in which all 8 bits in the first group of It is a reverse phase lock, and every half clock from the beginning, stage 1, stage 2, etc.

It is assumed that the external code correction data is prepared at least in stage 5.The operation shown in Fig. 6 will be explained below.
In stage 3, the module 19 other than the bus interface device reads data from the internal data bus 15. In the first half of stage 4, the module (9) rewrites all 8 bits of the first group of data to 1 and writes it to the internal data bus 15, and at the same time, the output latch 33 writes the data to the internal data bus 1.
Import from 5. Further, in the second half of stage 4, the data is encoded by the encoder 14, and as a result, code correction data is generated.Finally, in stage 5, the code correction data is output to the external code correction data bus 17. Problems to be Solved by the Invention Conventional Example Is it because modules other than the bus interface device 19 and the output latch 33 of the bus interface device share the internal data bus 15? - Since the module 19 is reading all 64-bit data, it is impossible for the module 19 to have already rewritten all 8 bits of the first group to 1. It is impossible to output that data to the internal data bus 15. For this reason, data in which all 8 bits of the first group are rewritten to 1 is written from the internal data bus 15 to the output latch 33 and is output. It will be l clocks later.

In order to use most of stage 4 for encoding, for convenience, the time required for encoding is ts, and the period from the rise of clock φ1 to the rise of clock φ2 is designated as tt. In FIG. 6, the time ts required for encoding is performed during tt. (ts<tt). Therefore, if the time required for encoding calculations is critical for circuit operation, the frequency at which tt equals ts is the upper limit operating frequency. In an interface device, the calculation time required for encoding becomes critical and there is a risk of deteriorating performance.However, the present invention enables output from the output latch to be performed quickly during the read/modify/write operations described above. It is an object of the present invention to provide a bus interface device and a read-modify-write control method that can avoid deterioration in system performance. ), an L enable signal, a first data bus consisting of m n-bit data buses, a second data bus consisting of m n-bit data paths, an m-bit set signal, and an n-bit data bus. m storage means for storing m-th (1
≦ 5m) Content capacity of the storage means When the bit-th set signal is set to the FL outputted to the k-th n-bit data bus of the second data bus, all bits are specified. ik of the first data bus when the enable signal is set.
This bus interface device is characterized in that the main port is replaced with n-bit data.

The present invention (2) also provides the bus interface device according to the above (1), wherein the enable signal is set at the same time as the data read from the second data bus is output to the first data bus. A read method characterized in that, after loading data from the first data bus into the storage means and resetting the enable signal, if the set signal is set, the contents of the storage means are set to a specific bit. Modify write control method works according to the present invention 1. The output latch can be set to a specific bit in byte units without changing the value while the data fetched from the first data bus is being output to the second data bus. Embodiment FIG. 1 shows the configuration of a bus interface device of the present invention. Bus interface device 404 according to the invention; t
,, Decoder 11. Input latch 1 & enable signal 18. Output latch 1 & encoder 14 with set signal 20. m n-bit data buses, e.g. 8
Internal data bus 15 consisting of two 8-bit data buses.
Similarly, the external data bus 16 is composed of eight 8-bit (64-bit) data buses, and the external code correction data bus 17 is composed of 8-bit data buses.Modules other than the bus interface device 40 are connected to the internal data bus 15. a encoder 14. Decoder 1
1. External code correction data bus 17ii Has an expanded function for code correction of the 64-bit external data bus 16. Outputs data to the external data bus 16. 8-bit code correction data is calculated by the encoder 14. The decoder 11 inputs data from the external data bus 16 and at the same time inputs 8-bit code correction data from the external code correction data bus 17, decodes it, and outputs it to the external code correction data bus 17. In this way, the code of the 64-bit external data bus 16 is corrected.

FIG. 5 shows the bus interface device 4 shown in FIG.
0 shows the structure of data used internally. The data length is 64 bits, and even though it is divided into groups of 8 bits, each bit of the data is numbered in order from 0 to 63. Oth bit, 1st bit 1181101
The 8 bits from the 63rd bit to the 56th bit are in the first group, the 8 bits from the 55th bit to the 48th bit are in the second group 1000601100, and the 7th bit to O In this embodiment, the above 64-bit data is transferred to the external data bus 1.
Let us consider a read-modify-write operation in which all 8 bits of the first group are rewritten to a specific bit, for example, 1, and written to the external data bus 16.4 Figure 22 shows an example of the output latch circuit. Output latch 13
consists of 64 latch circuits having a common enable signal 18. The latch circuit that captures the 0th bit of the 64 bits of data shown in FIG. 5 is the 0th latch L30Q.
The latch circuit that takes in the first bit of the 64 bits of data shown in FIG. 5 is the first latch L301100.
03101, the latch circuit that takes in the 63rd bit of the 64 bits of data shown in FIG. 5 is the 63rd latch L.
I will call it 363 from the 0th latch L300 to the 7th latch.
The 8 set signals up to latch L307 are set signal 2.
Connected to 0-8 00660066, 56th latch L
Eight set signals from L356 to 63rd latch L363 can be connected to set signal 20-1, and each latch circuit can set the content to 1 using set signals 20-1 to 20-8. The figure shows data read from the external data bus 16 and output to the internal data bus 15 using the bus interface device shown in FIG.
Even if it shows a read/modify/write operation in which all bits are rewritten to 1 and code correction data is calculated by the encoder 14 and output to the external code correction data bus 17, the clock φ is not yet clock φ4 and the clock φ4 is in reverse phase with each other and is locked. Stage 1 every half clock from the beginning. stage 2
．． I will call it ,,,,. It is assumed that the external code correction data is prepared at least in stage 5.The operation shown in Fig. 3 will be explained below.Internal data is prepared in stage 2.
At the same time, the enable signal 18 in stage 2 is output to the internal data bus 15 by the input latch 12, and the output latch 13 takes in the data on the internal data bus 15, and the module 19 also takes in this data.
In the first half of , the set signal 20-1 is output and the 63rd latch L
The contents of the eight latches (group number 1) from 363 to 56th latch L356 are set to 1. In the second half of stage 3 and stage 4, the internal data is encoded by encoder 14, and finally in stage 5, the external code correction data bus is encoded. 17, the time required for encoding is tl, the period from the rising edge of clock φ3 to the rising edge of clock φ4 in the present invention is tl, and the period from the rising edge of clock φ1 to the rising edge of clock φ2 in the conventional example is t2.According to the conventional example Internal data needs to be encoded in stage 4 and output in stage 5 (t s < t *)
. However, in the present invention, it is only necessary to encode at stages 3 and 4 and output at stage 5 (ts<t+X2)
. If the encoding is operationally critical ζ
Friend: The present invention can operate at double the frequency compared to the conventional example (t2=t+x2). Therefore, the present invention is extremely effective for microprocessors that require high-speed operation. In this embodiment, all 8 bits are designated as specific bits.
It goes without saying that the same effect can be obtained even if rewritten to a specific bit other than 1, such as IJ< o or (-1). In read/modify/write operations, in which the module references data, sets specific bits of the data in bytes, and outputs them to the external data bus, data can be output from the output latch faster than before, and high-speed operation is required. The effect on microprocessors is enormous.

[Brief explanation of drawings]

FIG. 1 shows a configuration diagram of a bus interface device according to an embodiment of the present invention. FIG. 2 shows a circuit diagram showing an example of an output latch of a bus interface device according to the present invention. FIG. 3 shows an embodiment of a bus interface device according to the present invention. Figure 4 shows the structure of a conventional bus interface device. Figure 5 shows the data structure. Figure 6 shows the read-modify-write operation of a conventional bus interface device. Operation diagram Amo 11
...Decoder, 12...Input latch, 13.33.
...Output latch, 14...Encoder, 15...Internal data buff, 16...External data bus 17...
External code correction data bus 18...enable signal q
19...module) L< 20.20-1°,,,
, 20-8...Set signal B300-B363...
・Latch, B500 to B563...Input data storage A3
00-A363...Output data.

Claims (2)

[Claims] (1) An enable signal, a first data bus consisting of m n-bit data buses, a second data bus consisting of m n-bit data buses, an m-bit set signal, and n-bit data m storage means for storing m storage means, the content of the k-th (1≦k≦m) storage means is
is output to the k-th n-bit data bus of the data bus, and when the k-th bit set signal is set, all bits are set to a specific bit, and when the enable signal is set, A bus interface device characterized in that the k-th n-bit data of the first data bus replaces the data. (2) In the bus interface device described above, the enable signal is set at the same time that the data read from the second data bus is output to the first data bus, and the data is stored in the storage means. The read-modify-write control method is characterized in that, after data is taken in from one data bus and the enable signal is reset, the contents of the storage means are set to a specific bit if the set signal is set.