JPH08195736A - Communication system - Google Patents

Abstract

PURPOSE: To improve line efficiency without provision of a special field to select data into an information bit. CONSTITUTION: A transmission station sends data as they are to invert data inputted to a transmission CRC arithmetic means 15 at an optional bit location and to differentiate the CRC value obtained by the transmission data thereby sending CRC information. A reception station receives reception data as they are, a reception packet invert means 24 inverts only the information used for CRC at an optional bit location and a reception CRC arithmetic means 25 executes the CRC arithmetic operation. The transmission station and the reception station set the bit location of the data so as to be the same or different from each other to use an error correction capability of the CRC code thereby selecting abort of data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication system, and more particularly to data of different characteristics such as program reception function data and normal data, broadcast data and point-to-point data from a transmitting station via a broadcast line. The present invention relates to a communication system in which each of a plurality of receiving stations selectively receives desired data from the transmitted data.

[0002]

2. Description of the Related Art FIG. 13 is a schematic block diagram of an example of a communication system. As shown in the figure, the communication system includes a plurality of secondary stations (slave stations) 402 to one primary station (master station) 401.
404 is connected, and transmission data from the primary station 401 is received by all the secondary stations 402 to 404 through a broadcast line from the primary station 401 to the secondary stations 402 to 404. Therefore, each of the secondary stations 402 to 404 performs a selection process of fetching only the data addressed to itself and discarding the other data.

Here, as a method for the secondary stations 402 to 404 to receive only specific data among the data transmitted by the primary station 401 via the broadcast line, Japanese Industrial Standard X5104.
High-level data link control (H
DLC: High Level Data Link
The normal response mode (NRM) of the Control procedure is conventionally known. In this HDLC procedure, data is divided into chunks called packets to be transmitted and received.

This packet (frame) is defined in a frame format as shown in FIG. 14, and the beginning and the end are surrounded by 8-bit fixed pattern flag sequences (F) 501 and 506, respectively. Between these flag sequences 501 and 506, an 8-bit address section (A) 502, an 8-bit control section (C) 503, an information section 504 with an arbitrary number of bits N, a 16-bit or 32-bit frame check. The sequence (FCS) 505 has a configuration in which they are sequentially combined.

In the communication system shown in FIG. 13, each secondary station 4 receives packet data transmitted on the broadcast line.
02 to 404 are the address part 5 of the received packet data
Whether or not 02 is an address unique to the own station is discriminated and judged, and when it matches the address of the own station, the data is error-corrected by using the FCS 505, and when it does not match the address of the own station, the data is discarded.

[0006]

However, in the above conventional communication system, the address section 502 is used as a special field for selecting only the data necessary for the own station among the packet data transmitted by the broadcast line. Since it has it, there is a drawback that the line efficiency drops.

[0007] The present invention has been made in view of the above points,
An object of the present invention is to provide a communication system capable of improving line efficiency by not providing a special field for selecting data in information bits.

Another object of the present invention is to provide a communication system capable of transmitting and receiving divided transmission data to a desired receiving station via a broadcast line.

Still another object of the present invention is that the receiving station can selectively receive only a transmission packet of a desired type of data without providing a special field indicating the type of data in the transmission packet. To provide a communication system.

[0010]

In order to achieve the above-mentioned object, in the invention described in claim 1, it comprises one transmitting station and a plurality of receiving stations, and the transmitting station adds an error correction code to divided transmission data. Generated transmission packet and transmit it simultaneously to multiple receiving stations on the broadcast line.Each of the multiple receiving stations performs error correction calculation on the received packet. When there is no error, the received packet is fetched and when there is an error, the received packet is received. In a communication system that discards packets, a transmission station includes a transmission data reversing unit that inverts a value of a prespecified bit position of divided transmission data, and a transmission error that creates an error correction code based on output data of the transmission data reversing unit. The correction code calculation means, the input divided transmission data and the output error correction code of the transmission error correction code calculation means are respectively combined and output as a transmission packet. The receiving station receives the transmission packet and reverses the received packet at the bit position designated by the receiving station, and the error correction is performed based on the output packet of the reception packet inverting means. It is configured to have a reception error correction code calculation means for performing a calculation.

According to the second aspect of the invention, the transmitting station further comprises second inverting means for inverting the bit position defined by the output error correction code of the transmission error correction code calculating means of the first aspect of the invention. The input division transmission data and the output error correction code of the second inverting means are combined by the combining means and output as a transmission packet.

Further, in the third aspect of the present invention, the predetermined bit position of the packet obtained by synthesizing the input divided transmission data and the output error correction code of the transmission error correction code calculating means is transmitted packet inversion. It is configured to be inverted by the means and output as a transmission packet.

[0013]

According to the first aspect of the invention, the error correction code calculated by the transmission error correction code calculation means is added to the divided transmission data based on the divided transmission data in which a bit position is inverted by the transmission data inverting means. To send. Further, in the invention according to claim 2, based on the divided transmission data in which a certain bit position is inverted by the first inversion means,
The bit position having the error correction code calculated by the transmission error correction code calculating means is further inverted by the second inverting means and then added to the divided transmission data and transmitted. Further, claim 3
In the invention described above, the bit position of the transmission packet is inverted by the transmission packet inverting means and then transmitted.

Therefore, in any of the above-mentioned inventions of claims 1 to 3, when the receiving station performs the bit inversion processing on the received packet at the same bit inversion position as the transmitting station,
It is determined that there is no error based on the operation result based on the error correction code, and when the bits are inverted at different bit inversion positions or when bit inversion is not performed, it is normally determined that there is an error based on the operation result based on the error correction code. .

Here, the bit inversion position in the transmission packet transmitted from the above-mentioned transmitting station is a bit position uniquely assigned to each of the plurality of receiving stations, or according to the kind of divided transmission data to be transmitted. It is a bit position defined by.

[0016]

Next, an embodiment of the present invention will be described. FIG. 1 shows a block diagram of a first embodiment of the present invention. The communication system of this embodiment includes one transmitting station (master station) shown in the block diagram of FIG. 9A and a plurality of receiving stations (slave stations) having the configurations shown in the block diagram of FIG. Become.

As shown in FIG. 1A, the transmitting station includes a transmitting data inverting means 14, a transmitting CRC calculating means 15, a parallel / serial converting means 16 and a transmitting timing generating means 1.
7 and selector 18. The transmission data inverting means 14 inverts the divided transmission data from the input terminal 11. Further, the transmission data inversion means 14, the transmission CRC calculation means 15, and the parallel / serial conversion means 16 are supplied with the transmission clock from the input terminal 12 in common and operate in synchronization.

The transmission timing generation means 17 generates a transmission timing signal generated based on the divided data start / end signal from the input terminal 13 and the transmission clock from the input terminal 12, the transmission data inverting means 14 and the transmission CRC calculation means. 15, parallel / serial conversion means 16 and selector 1
Supply to 8. The selector 18 selects one of the divided transmission data from the input terminal 11 and the output serial data of the parallel / serial conversion means 16 based on the transmission timing signal and outputs it to the output terminal 19.

Further, the transmission CRC calculating means 15 has a conventionally known cyclic redundancy check (CRC: Cyclic Red).
An unchecked check code is a circuit that calculates and generates, for example, a 6-bit shift register 3 as shown in FIG.
2, 33, 4-bit shift register 34, and adders 35, 36 and 37 by exclusive OR circuits. The adder 37 receives the input data from the input terminal 31 (see FIG.
(The output data of the transmission data inverting means 14 of (A)) and the output serial data of the shift register 34 are added,
The addition result is added to the adders 35 and 36 and the shift register 3.
Enter in 2 respectively.

The adder 35 adds the output addition result of the adder 37 and the output serial data of the shift register 32 and supplies the result to the shift register 33. The adder 36 adds the output addition result of the adder 37 and the output serial data of the shift register 33 and outputs the result to the shift register 34. The shift registers 32, 33 and 34 are respectively shown in FIG.
The shift operation is performed based on the transmission clock shown in (A).

On the other hand, the receiving station, as shown in FIG.
The reception packet inverting means 24, the reception CRC calculation means 25, and the reception timing generation means 26 are included. The received packet inverting means 24 inverts the received packet from the input terminal 21. The reception CRC calculation means 25 is a transmission CRC
For example, it has the same circuit configuration as that of the calculation means 15 shown in FIG.

The reception timing generation means 26 is based on the reception clock from the input terminal 22 and the reception packet start / end signal from the input terminal 23, which are commonly supplied to the reception packet inverting means 24 and the reception CRC calculation means 25. To generate a reception timing signal and supply the reception timing signal to the reception packet inverting means 24 and the reception CRC calculation means 25. The received packet from the input terminal 21 is output to the output terminal 27. The output CRC calculation result of the reception CRC calculation means 25 is output to the output terminal 28.

In this embodiment, the transmitting station transmits the inputted divided transmission data as it is, while inverting the divided transmission data at an arbitrary bit position and then inputting it to the transmission CRC calculating means 15 to transmit the divided transmission data. C that is different from the original CRC value obtained by the divided transmission data
Send RC information. The receiving station takes in the received data as it is and inverts only the information used for the CRC calculation at an arbitrary bit position.

Therefore, by setting the bit inversion positions of the above divided transmission data to be the same or different at the transmitting station and the receiving station, it is possible to select data by utilizing the error correction capability of the CRC code. it can. This can be explained using formulas as follows.

The input data is DATA, the transmission side inversion conversion is RT (), the reception side inversion conversion is RR (), and the CRC operation is C.
It shall be expressed as RC (). However, RT (R
T ()) = 1 and RR (RR ()) = 1. In this embodiment, the transmission packet transmitted from the transmission station can be expressed by the following equation.

DATA + CRC (RT (DATA)) On the other hand, since the reception CRC calculation means 25 performs the CRC calculation on the data portion of the reception packet, the reception CRC calculation value can be expressed by the following equation.

CRC (RR (DATA)) Therefore, in general, when RT () and RR () are the same, that is, when the inverted bit positions are the same in the transmitting station and the receiving station, the CRC results match and when they are different. The CRC results also do not match.

Next, the operation of this embodiment will be described with reference to FIGS. First, to explain the operation of the transmitting station, the transmission timing generating means 1 shown in FIG.
Reference numeral 7 generates a timing signal necessary for CRC calculation and a packet with a CRC bit based on the transmission clock from the input terminal 12 and the divided data start / end signal from the input terminal 13, and outputs this timing signal. The data is supplied to the transmission data inverting means 14, the transmission CRC calculation means 15, the parallel / serial conversion means 16 and the selector 18, respectively.

On the other hand, input through the input terminal 11,
The divided transmission data divided into units to add CRC,
The data is supplied to the transmission data inverting means 14 which constitutes the main part of the present embodiment, and the bit at the position designated by the user is inverted here and then supplied to the transmission CRC calculating means 15.

The transmission CRC calculation means 15 applies to the divided data RT (DATA) in which the input predetermined bits are inverted, to the International Telecommunication Union (ITU-T: Old International Telegraph and Telephone) as shown in the flowchart of FIG. Advisory Committee (CCI
TT)) The CRC calculation is performed by the general method as shown in the recommendation, and the 16-bit CRC calculation result is passed to the parallel / serial conversion means 16 when one unit of divided data is input.

That is, the transmission CRC calculation means 15 of the configuration shown in FIG. 2 includes all shift registers (CRC registers).
All bits of 32, 33, and 34 are initialized to "1" (step 41 in FIG. 3), serial data is input from the input terminal 31, and the addition output of the adder 37 is added.
5, 36 and the shift register 32, respectively, and the shift operation of the shift registers 32 to 34 is performed on 16 bits of the input data (step 4 in FIG. 3).
2).

Subsequently, all the bits of all the shift registers (CRC registers) 32, 33 and 34 described above are inverted (step 43 in FIG. 3), and all 16-bit outputs of these shift registers 32 to 34 are parallelized. Each bit is shifted from the bit from the most adder 37 of the shift register 34 (this becomes the least significant bit (LSB) of the CRC code) via a parallel / serial conversion means (not shown) (corresponding to 16 in FIG. 1A). The output values of the registers 32-34 are sequentially taken out (step 44 in FIG. 3).

This is the result of 16-bit CRC calculation (CR
The C code is supplied to the selector 18 of FIG. The selector 18 normally selects and outputs the divided transmission data from the input terminal 11 based on the transmission timing signal, and the parallel / serial operation is performed for the time corresponding to the CRC code length after the output of one unit of the divided transmission data is completed. The serial output CRC code from the conversion means 16 is selected and output to the output terminal 19. As a result, the transmission data represented by DATA + CRC (RT (DATA)) and the CRC calculation result are serially output to the output terminal 19.

Next, to explain the operation of the receiving station,
The receiving station receives the transmission data and the CRC calculation result and supplies them to the reception packet inverting means 24 from the input terminal 21 shown in FIG. 1 (B) through a known receiving section (not shown), while outputting the output terminal. Output to 27 as it is. Further, the reception clock from the input terminal 22 and the reception packet start / end signal from the input terminal 23 are supplied to the reception timing generation means 26 and used as timing signals necessary for CRC calculation.

The reception packet inverting means 24 inverts the input reception packet at the position designated by the user with reference to the timing signal from the reception timing generating means 26 and supplies the reception packet to the reception CRC calculating means 25. Receive C
The RC calculation means 25 performs a CRC calculation on the input received packet, and outputs a CRC calculation result indicating either match / mismatch to the output terminal 28 based on the CRC calculation result.

The reception CRC calculation means 25 performs the ITU-T as shown in the flowchart of FIG. 4 on the input divided data RR (DATA) in which the predetermined bits are inverted.
The CRC calculation is performed by the general method as shown in the (old CCITT) recommendation, and the CRC calculation result is output at the time when one unit of divided data is input.

That is, the reception CRC calculation means 25 of the configuration shown in FIG. 2 includes all shift registers (CRC registers).
All bits of 32, 33, and 34 are initialized to "1" (step 51 in FIG. 4), and then the data and the CRC operation result from the input terminal 31 are input and the addition output of the adder 37 is added to the adder 35, 36 and the shift register 32, respectively, and shift operations of the shift registers 32 to 34 are performed (step 52 in FIG. 4).

Next, the values of all the bits of all the shift registers (CRC registers) 32, 33 and 34 described above are the predetermined value "11110000 10111000" (the bit from the adder 37 most of the shift register 34 is CR.
It is determined whether or not it is the LSB of the C code), and the determination result (CRC calculation result) determined to be the CRC match when the above predetermined value is output (step 53 in FIG. 4).

Here, the probability that the CRC value matches the above predetermined value is small even though the bit inversion positions are different between the transmitting station and the receiving station, and it is equal to the probability that different data show the same CRC value. In the receiving station data receiving process, the data is fetched only when the CRC values match, and the receiving data is discarded when the CRC values do not match. Therefore, when the inverted bit position different from that of the transmitting station is specified, the data is erroneously fetched. Since the reception probabilities can be lowered to the probabilities that different data show the same CRC value, data at different inversion positions can be efficiently discarded.

Therefore, in the present embodiment, the transmitting station allocates a unique bit inverting position to each of the plurality of receiving stations as the transmission data bit inverting position by the transmission data inverting means 14, without providing an address part. The value of the bit position corresponding to the receiving station to be transmitted is inverted and transmitted. A plurality of receiving stations inverts at the bit position unique to the own station and receives the reception data of the CRC calculation result indicating the coincidence as the data addressed to the own station, and the reception data of the CRC calculation result indicating the disagreement is the data addressed to the other station. Discard as.

Next, a second embodiment of the present invention will be described. FIG. 5 shows a block diagram of a second embodiment of the present invention. The communication system of this embodiment includes one transmitting station (master station) shown in the block diagram of FIG. 9A and a plurality of receiving stations (slave stations) having the configurations shown in the block diagram of FIG. Therefore, the same components as those in FIG.

As shown in FIG. 5 (A), the transmitting station has a transmitting data inverting means 14, a transmitting CRC calculating means 15, a parallel / serial converting means 16, and a transmitting timing generating means 6.
1, a transmission CRC inverting means 62 and a selector 18. That is, the transmitting station of the present embodiment has a transmission CR between the parallel / serial conversion means 16 and the selector 18.
The feature is that the C inverting means 62 is provided. On the other hand, the receiving station, as shown in FIG.
6, reception CRC calculation means 25 and reception timing generation means 65.

This embodiment is similar to the first embodiment in that the transmission data reversing means 14 in the transmitting station inverts the divided transmission data at an arbitrary bit position and inputs it to the transmission CRC calculating means 15. In the present embodiment, the transmission CRC inverting means 62 also inverts the CRC code at an arbitrary position for transmission. On the other hand, in the receiving station, the divided transmission data in the received packet is taken in as it is, and only the information used for the CRC calculation is inverted at an arbitrary bit position. By setting the same inversion position or different inversion positions in the transmitting station and the receiving station, data can be selected using the error correction capability of the CRC code. This can be explained using formulas as follows.

Input data is DATA, transmission side data section inversion conversion is RT1 (), and transmission side CRC section inversion conversion is RT2.
(), The receiving side data part inversion conversion is RR1 (), the receiving side C
RC part inversion conversion is RR2 (), CRC operation is CRC ()
Shall be written. However, RT1 (RT1 ())
= 1, RT2 (RT2 ()) = 1, RR1 (RR
1 ()) = 1 and RR2 (RR2 ()) = 1. In this embodiment, the transmission packet transmitted from the transmission station can be expressed by the following equation.

DATA + RT2 (CRC (RT1
(DATA)) On the other hand, since the CRC calculation in the receiving station is performed on the data portion of the packet, the CRC calculation value in the receiving station can be expressed as follows.

CRC (RR1 (DATA)) Further, since the receiving station carries out the inversion conversion on the CRC part, the received CRC part can be expressed as follows.

RR2 (RT2 (CRC (RT1 (DATA)))) Therefore, in general, RT1 () and RR1 (), and RT
When 2 () and RR2 () are the same, the CRC calculation results match, and when they are different, the CRC calculation results also do not match.

Next, the operation of this embodiment will be described.
First, the operation of the transmitting station will be described. In the transmitting timing generating means 61 shown in FIG. 5A, the transmission clock from the input terminal 12 and the divided data start / input from the input terminal 13 are started.
Based on the end signal, a timing signal necessary for CRC calculation and generation of a packet with a CRC bit is generated, and this timing signal is transmitted data inverting means 14,
The transmission CRC calculation means 15, the parallel / serial conversion means 16, the transmission CRC inverting means 62, and the selector 18 are supplied.

On the other hand, CRC (RT1 (DAT
The CRC code represented by A)) is the transmission CRC inverting means 6
2 and is inverted at the bit position specified by the user based on the transmission timing signal,
The CRC code represented by (CRC (RT1 (DATA))) is supplied to the selector 18.

The selector 18 normally selects and outputs the divided transmission data from the input terminal 11 based on the transmission timing signal, and only after the completion of the output of the divided transmission data of one unit, the time of the CRC code length. Transmission CRC reversing means 6
Select the serial output CRC code from 2 and output terminal 6
Output to 3. As a result, DATA + RT2 (CRC (RT1 (DAT
The transmission data and CRC code represented by A))) are output serially.

Next, to explain the operation of the receiving station,
The receiving station receives the transmission data and the CRC calculation result, and supplies them to the received packet inverting means 66 from the input terminal 21 of FIG. 5 (B) through a known receiving unit (not shown), while outputting them to the output terminal. It is output to 27. Based on the output timing signal of the reception timing generation means 65, the reception packet inversion means 66 inverts the bit positions designated by the user in the divided transmission data portion and the CRC code portion in the input reception packet, respectively, and then the reception CRC calculation means. Supply to 25.

Therefore, when the bit position inverted by the reception packet inverting means 66 is the same as the bit position inverted by the transmission data inverting means 14 and the transmission CRC inverting means 62, respectively, the reception CRC is used unless there is a transmission error. The CRC calculation result by the calculation means 25 matches the predetermined value. In this way, this embodiment, like the first embodiment,
Data having different bit inversion positions can be efficiently discarded by the transmitting station and the receiving station, and the data for the desired receiving station can be selectively received by the receiving station without providing a special field.

By the way, since the end of the received packet is usually known after receiving the CRC code of the received packet, for example, when a cyclic inversion method of inverting one bit for every eight bits is adopted, the CRC code is also received at the receiving station. Including it will be reversed. According to the configuration shown in FIG. 5, if the transmitting station performs cyclic inversion including both the data area and the CRC area, the receiving station receives the data area and the CRC.
Since the regions can be cyclically inverted without distinction, the circuit configuration of the receiving station can be simplified.

Next, a third embodiment of the present invention will be described. FIG. 6 shows a block diagram of a third embodiment of the present invention. The communication system of this embodiment includes one transmitting station (master station) shown in the block diagram of FIG. 9A and a plurality of receiving stations (slave stations) having the configurations shown in the block diagram of FIG. Therefore, the same components as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIG. 6 (A), the transmitting station includes a transmitting CRC calculating means 71 and a parallel / serial converting means 1.
6, a selector 18, a transmission timing generating means 72, and a transmission packet inverting means 73. That is,
The transmitting station of the present embodiment is characterized in that a transmitting packet inverting means 73 is provided on the output side of the selector 18. On the other hand, the receiving station, as shown in FIG.
6, reception CRC calculation means 25 and reception timing generation means 26.

In the present embodiment, the transmitting station inverts the packet in which the CRC code calculated by the normal procedure is added to the divided transmission data at the bit position designated by the transmission packet reversing means 73 and transmits it. On the other hand, in the receiving station, the received packet inverting means 76 inverts the received packet at the designated bit position, and inputs the received data and the received CRC calculating means 25. By setting the same inversion position or different inversion positions in the transmitting station and the receiving station, data can be selected using the error correction capability of the CRC code.
This can be explained using formulas as follows.

Input data is DATA, transmission side data section inversion conversion is RT1 (), and transmission side CRC section inversion conversion is RT2.
(), The receiving side data part inversion conversion is RR1 (), the receiving side C
RC part inversion conversion is RR2 (), CRC operation is CRC ()
Shall be written. However, RT1 (RT1 ())
= 1, RT2 (RT2 ()) = 1, RR1 (RR
1 ()) = 1 and RR2 (RR2 ()) = 1. In this embodiment, the transmission packet transmitted from the transmission station can be expressed by the following equation.

RT1 (DATA) + RT2 (CRC
(DATA) On the other hand, since the receiving station first performs the inversion conversion on the received data, the packet after the inversion conversion at the receiving station can be expressed as follows.

RR1 (RT1 (DATA)) + RR2
(RT2 (CRC (DATA))) In addition, since the receiving station performs the inversion conversion on the CRC part, the received CRC part can be expressed as follows.

CRC (RR1 (RT1 (DATA))) Therefore, in general, RT1 () and RR1 (), and RT
When 2 () and RR2 () are the same, the CRC calculation results match, and when they are different, the CRC calculation results also do not match.

Next, the operation of this embodiment will be described.
First, the operation of the transmitting station will be described. In the transmitting timing generating means 72 shown in FIG. 6A, the transmitting clock from the input terminal 12 and the division data start / input from the input terminal 13 are started.
A timing signal required to generate a CRC operation and a packet with a CRC bit is generated based on the end signal, and the timing signal is transmitted to the CRC calculation means 71.
The parallel / serial conversion means 16, the transmission packet inverting means 73 and the selector 18 are supplied respectively.

On the other hand, while the divided transmission data from the input terminal 11 is directly supplied to the selector 18, it is also supplied to the transmission CRC calculating means 71 and here the structure shown in FIG. After being converted into a CRC code, it is serially input to the selector 18 via the parallel / serial conversion means 16.

The selector 18 normally selects the divided transmission data from the input terminal 11 on the basis of the transmission timing signal and outputs it to the transmission packet inverting means 73, and the output of the divided transmission data of one unit is completed. To the transmission packet inversion means 73 by selecting the serial output CRC code from the parallel / serial conversion means 16 for the time corresponding to the CRC code length.
Output to. As a result, the transmission data represented by DATA + (CRC (DATA)) and the CRC code are serially output to the transmission packet inverting means 73.

The transmission packet inverting means 73 inverts the values at the designated bit positions of the input transmission data portion and the CRC encoding portion, and outputs the packet represented by the following equation to the output terminal 74.

RT1 (DATA) + RT2 (CRC (DATA)) Next, to explain the operation of the receiving station, the packet of the above equation is supplied from the input terminal 21 of FIG. 6 (B) to the received packet inverting means 76, Here, after being inverted at the bit position designated by this receiving station, it is supplied to the reception CRC calculation means 76, while the data portion is output to the output terminal 27.
The reception CRC calculation means 25 performs the above-described CRC calculation on the input signal, and indicates a CR indicating whether or not it matches a predetermined value.
The C calculation result is output to the output terminal 28.

In this embodiment, the transmission packet inverting means 73
The received packet inverting means 76 at the same bit positions as the respective bit positions of the data part and the CRC code part which are respectively inverted by
When each of the received packets is inverted, a CRC matching calculation result is obtained, and the received data from the output terminal 27 can be fetched. When bit inversion is performed at a different position, the CRC mismatch is detected. Since the calculation result is obtained, the received data can be efficiently discarded as in each of the above embodiments.

Further, in this embodiment, the transmission CRC calculation means 71, the parallel / serial conversion means 16, the selector 1
8. The transmission timing generation means 72 has the same configuration as the conventional transmission station, and the transmission station can be configured by adding the transmission packet inverting means 73 to this, and the reception CRC calculation means 76 and the reception timing generation means 26. Has the same configuration as that of the conventional receiving station.
Since the receiving station can be configured by adding, the necessary circuit parts can be added externally without changing the configurations of the existing transmitting station and receiving station. You can stop to the limit.

The transmission packet inverting means 73 and the reception packet inverting means 76 perform bit inversion for both the data portion and the CRC code portion in the above embodiment, but either one may be used.

Next, the CRC code generated by the transmission CRC calculation means 15, 71 and the reception CRC calculation means 25, 6
A specific example of the CRC code calculated in 6 and 76 will be described. The generator polynomial of the CRC code is ITU-T (old CCI
And ^{x 16 + x 12 + x 5} +1 is a generator polynomial of 16-bit CRC code are recommended by TT), also "1111 input data from the input start 0000 1111
It is assumed to be 24 bits having a value of "0000 1111 1111".

The input data having the above value is transmitted without inversion C
When the RC operation is performed, the final register states of the shift registers 32 to 34 of the CRC operation means having the configuration shown in FIG.
111 1111 0100 0100 ”(note that the first value is MSB and the last value is LSB: the same applies hereinafter). As shown in steps 43 and 44 of the flowchart of FIG. 3, the 16-bit value is inverted after all bits are added in order from the LSB as the 16-bit CRC code after the input data to form a transmission packet and transmitted. It Therefore, the transmission packet is "1111 0000 1
111 000011111 1111 1101 11
01 0000 0000 ".

When this transmission packet is input to the reception CRC calculating means without being inverted, the CR having the configuration shown in FIG.
The final register states of the shift registers 32 to 34 of the C arithmetic means are “1111 0000 1011 1000”.
And matches the specific value described above. Therefore, at this time, a determination result (CRC calculation result) that CRC match (OK) is obtained.

On the other hand, when the third bit of the 24-bit input data having the same value is inverted, the transmission packet is "1101 0000 1111 0000 1111".
1111 1101 1101 0000 000
0 ". Since the CRC code in this transmission packet is the CRC code generated when the input data is not inverted, this transmission packet is transmitted to the receiving station by the C code of the configuration shown in FIG.
When input to the RC calculation means, the shift register 32 ...
The final register state of 34 is "1101 1101 1
010 1000 ". This value is different from the above-mentioned specific value, and at this time, a judgment result (CRC calculation result) that CRC mismatch (NG) is obtained, and this received packet is discarded.

In each of the above-described embodiments, the value of the designated bit of the transmission data is inverted to generate the CRC code. Therefore, when the receiving station receives the CRC code as it is, the CRC mismatch occurs. However, when the receiving station performs bit inversion at the same position as the transmitting side and inputs substantially the same data as the input of the transmitting CRC calculating means to the receiving CRC calculating means 25, C
The result of the RC match determination is obtained.

Next, the present invention is applied to a microsatellite communication earth station (V
SAT: Very Small Aperture t
A description will be given of a case where the present invention is applied to an electronic system. As shown in FIG. 7, the VSAT system includes one master station (HUB station) 81 and a plurality of slave stations (VSAT) 83 to.
85 is connected via a line with the satellite 82 as a relay station. In this VSAT system, the HUB station 81
Since the data transmitted from the VSAT stations 83 to 85 to the VSAT stations are broadcast lines, all the VSAT stations 83 to 85 are transmitted.
Will be received at. Therefore, each of the VSAT stations 83 to 85 must perform a selection process of taking in only the data that the local station needs and discarding the unnecessary data.

In addition, the VSAT station 83 of the VSAT system
Since ~ 85 is installed in a wide area, a program necessary for the device to operate by using the communication line of the HUB station 81-VSAT station 83-85 so that the program version can be easily upgraded. Down line loading (DLL: Down Lin)
It is usual that the e-loading function is provided and the program read only memory (ROM) has only the minimum function for performing DLL.

By incorporating the DLL function, RO
Since the program size of M can be reduced, this is an effective means for improving the reliability of the ROM. However, since DLL data are mixed in addition to normal communication data, each VSAT station 8
In 3-85, it is necessary to sort the received data.

In such a VSAT system, by applying the present invention, it is possible to select at the CRC check level by changing the bit inversion position between the normal operation data and the DLL data, which makes it possible to select the sequence shown in FIG. As shown in, normal communication data and DLL data can be mixedly transmitted from the HUB station 81 to the VSAT stations 83 to 85.

In FIG. 8, from the HUB station 81 to the VSAT station 8
Only data for 3 to 85 are shown, and VSAT
It is assumed that the station 83 is a station that is in normal operation after the DLL data has already been captured, and the VSAT stations 84 and 85 are stations that are capturing DLL data. In FIG. 8, HU
Normal data transmission from the B station 81 to the VSAT stations 83 to 85 (step 91), normal data transmission (step 9)
2), DLL data transmission (step 93), normal data transmission (step 94), DLL data transmission (step 9)
It is assumed that the information is transmitted in the order of 5). At this time, the data indicated by black circles are captured.

In order to realize the above sequence, the HUB station 81 as the master station performs the operation according to the flowchart shown in FIG. 9, and the VSAT stations 83 to 85 as the slave stations respectively operate according to the flowchart shown in FIG. I do.
First, as shown in FIG. 9, the HUB station 81 determines whether the data to be transmitted is DLL data or normal data (step 101). The normal operation information for inverting the value is set (step 102), and the DLL inversion information for inverting the value of the bit position different from the predetermined normal data for the DLL data is set for the DLL. (Step 103). Then, the inverted data of the bit position and the CRC based on the inverted data
A transmission process is performed to transmit the packet to which the code is added (step 104).

On the other hand, in the VSAT stations 83 to 85, the same DLL data reception inversion information as in the HUB station 81 is set in the DLL sequence after the power is turned on (step 11).
1). When DLL data is received in this state, CR
Since the C operation result indicates a match, the received data at that time, that is, the DLL data is taken in, while when the normal data is received, the bit inversion position is different from the DLL data, and the CRC operation result indicates a mismatch, so that reception Normal data is discarded (corresponding to the white circles of the VSAT stations 84 and 85 in FIG. 8).

In this way, the VSAT stations 83 to 85 selectively receive only the DLL data and receive the DLL program (step 112), and after receiving all the DLL data (step 113), switch to the normal operation inversion information (step 113). Step 114). After the normal operation, when the DLL data is received, the bit inversion position is different from the normal data, and the CRC calculation result shows a mismatch, so that the reception D
The LL data is discarded (corresponding to the white circle of the VSAT station 83 in FIG. 8).

When the present invention is applied, the probability that the same CRC calculation result will be obtained despite the setting of different inversion information is small, but not 0. Therefore, normal data is also included in DLL data, and normal operation is in progress. There is a possibility that the DLL data may be received as a CRC calculation result match.

However, even if a bit error occurs originally due to a transmission line error, the CRC error check may be bypassed. Therefore, after the transmission line CRC error check, some kind of check is usually performed.
Therefore, even if the present invention is applied and data is erroneously received, there is no problem in operation.

Next, the simplest circuit configuration will be described based on the second embodiment of the present invention. FIG. 11 is a circuit system diagram of the transmitting station. The input division transmission data is the exclusive OR circuit 12
1 and is subjected to exclusive OR operation with the inversion control bit from the inversion control bit 122. Therefore, when the inversion control bit 122 is "0", the input divided transmission data is non-inverted, and when it is "1", it is inverted and two types of inversion states can be created. Therefore, the transmission data inverting means 14 can be configured by setting the inversion control bit 122 to normally "0" and setting it to "1" only at the bit position designated by the user.

The output data of the exclusive OR circuit 121 is supplied to the CRC calculation block 123 constituting the transmission CRC calculation means 15 and the parallel / serial conversion means 16 of FIG. 5A and converted into a CRC code. After that, it is converted into a serial signal and input to the exclusive OR circuit 124, where it is subjected to exclusive OR operation with the inversion control bit from the inversion control bit 122. As a result, the inversion control bit 122 is normally set to "0" and set to "1" only at the bit position designated by the user, whereby the exclusive-OR circuit 124 can configure the transmission CRC inverting means 62.

FIG. 12 is a circuit diagram of the receiving station. The input reception packet is input to the exclusive OR circuit 131, where it is exclusive ORed with the inversion control bit (1 bit) from the inversion control bit 132. It Therefore, when the inversion control bit 132 is "0", the input division transmission data is non-inversion, and when it is "1", it is inversion, and two kinds of inversion states can be created like the transmitting station. Therefore, the inversion control bit 122 is normally set to "0" and is set to "1" only at the bit position designated by the user, whereby the reception packet inversion means 24 can be configured.

The output data of the exclusive OR circuit 131 is shown in FIG. 2 which constitutes the reception CRC calculation means 25 of FIG. 5B.
It is supplied to the CRC calculation block 133 as shown in FIG. 2 and subjected to CRC calculation to determine whether or not it matches a predetermined value, and is output as the CRC calculation result.

The present invention is not limited to the above-described embodiment. For example, the error correction code may be a known error correction code other than the CRC code (eg Hamming code, BCH).
Code, Fire code, Reed-Solomon code, etc.).

[0089]

As described above, according to the present invention,
A transmission packet added with an error correction code generated based on divided transmission data whose value was inverted at a certain bit position from the transmitting station, or a transmission packet whose value was inverted at a certain bit position of the error correction code or divided transmission data Send
When the receiving station performs bit inversion processing on the received packet at the same bit inversion position as the transmitting station, it determines that there is no error based on the operation result based on the error correction code, and performs bit inversion processing at a different bit inversion position, Alternatively, when bit inversion is not performed, it is normally determined that there is an error based on the operation result based on the error correction code.
When you do not want to receive, make the bit inversion positions of the transmitting station and the receiving station the same, and when you do not want to receive, make the bit inversion positions of the transmitting station and the receiving station different or do not perform bit inversion, and Data can be selectively received by using the error detection function of the error correction code without providing a special field for selection, and thus the line efficiency can be improved.

Therefore, according to the present invention, the bit inversion position in the transmission packet transmitted from the transmission station is
When the bit position is uniquely assigned to each of the plurality of receiving stations, the divided transmission data is transmitted to the desired receiving station through the broadcast line without providing the address part for the plurality of receiving stations in the transmission packet. Can be received. Further, when the bit inversion position in the transmission packet is set to the bit position determined according to the type of the divided transmission data to be transmitted, the receiving station does not need to provide a special field indicating the type of data in the transmission packet. Among the transmitted transmission packets, can selectively receive only the transmission packet of the desired type of data.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of an example of a CRC circuit.

FIG. 3 is a flowchart for explaining a process when transmitting a CRC.

FIG. 4 is a flowchart for explaining processing when a CRC is received.

FIG. 5 is a block diagram of a second embodiment of the present invention.

FIG. 6 is a block diagram of a third embodiment of the present invention.

FIG. 7 is a system configuration diagram of an example of a VSAT system.

8 is a sequence diagram of an example of the system of FIG.

FIG. 9 is a flowchart of data transmission of the master station.

FIG. 10 is a flowchart of data reception of a slave station.

FIG. 11 is a circuit system diagram of an example of a transmitting side of the present invention.

FIG. 12 is a circuit system diagram of an example of a receiving side of the present invention.

FIG. 13 is a schematic configuration diagram of an example of a communication system.

FIG. 14 is a diagram showing an example of a frame structure.

[Explanation of symbols]

 11 division transmission data input terminal 12 transmission clock input terminal 13 division data start / end signal input terminal 14 transmission data inverting means 15, 71 transmission CRC calculation means 16 parallel / serial conversion means 17, 61, 72 transmission timing generation means 18 selector 19 , 63, 74 transmission packet output terminal 21 reception packet input terminal 22 reception clock input terminal 23 reception packet start / end signal input terminal 24, 66, 76 reception packet inverting means 25 reception CRC calculation means 26, 65 reception timing generation means 27 reception Data output terminal 28 CRC calculation result output terminal 32-34 Shift register (CRC register) 62 Transmission CRC inverting means 73 Transmission packet inverting means 81 Master station (HUB station) 82 Satellite 83-85 Slave station (VSAT station)

Claims (5)

[Claims] 1. A transmission station comprising one transmission station and a plurality of reception stations, the transmission station generating a transmission packet in which error correction code is added to divided transmission data, and transmitting the transmission packet to the plurality of reception stations simultaneously through a broadcasting line. In the communication system, each of the plurality of receiving stations performs an error correction calculation on the received packet, takes in the received packet when there is no error, and discards the received packet when there is an error. Transmission data inverting means for inverting the value of a predetermined bit position of transmission data, transmission error correction code arithmetic means for creating the error correction code based on the output data of the transmission data inverting means, and the input divided transmission data And the output error correction code of the transmission error correction code calculation means are combined and output as the transmission packet. Is a received packet inverting means for receiving the transmitted packet and inverting the received packet at a bit position designated by its own station, and a received error correction for performing the error correction operation based on the output packet of the received packet inverting means. A communication system comprising a code calculation means. 2. A transmission station comprising a single transmission station and a plurality of reception stations, the transmission station generating a transmission packet in which error correction code is added to divided transmission data, and transmitting the packets simultaneously to the plurality of reception stations via a broadcasting line. In the communication system, each of the plurality of receiving stations performs an error correction calculation on the received packet, takes in the received packet when there is no error, and discards the received packet when there is an error. First inversion means for inverting the value of the transmission data at a predetermined bit position, transmission error correction code calculation means for creating the error correction code based on the output data of the first inversion means, and the transmission error Second inverting means for inverting the value of the bit position designated in advance of the output error correction code of the correction code calculating means, the input divided transmission data and the output error correction of the second inverting means And a synthesizing unit for synthesizing a code and outputting the packet as the transmission packet, wherein the receiving station receives the transmission packet and inverts the received packet at a bit position designated by the own station. A communication system comprising: means and a reception error correction code operation means for performing the error correction operation based on the output packet of the reception packet inverting means. 3. A transmission station comprising one transmission station and a plurality of reception stations, the transmission station generating a transmission packet in which an error correction code is added to divided transmission data and transmitting the transmission packet to the plurality of reception stations simultaneously through a broadcasting line. In the communication system, each of the plurality of receiving stations performs an error correction calculation on the received packet, takes in the received packet when there is no error, and discards the received packet when there is an error. A transmission error correction code calculation means for generating the error correction code based on transmission data, a combination means for combining the input divided transmission data and an output error correction code of the transmission error correction code calculation means, and the combination means. And a transmission packet reversing unit that inverts a value of a predetermined bit position of the output packet and outputs the packet as the transmission packet. Received packet inverting means for receiving a transmitted packet and inverting the received packet at a bit position designated by the local station, and received error correction code arithmetic means for performing the error correction operation based on the output packet of the received packet inverting means. And a communication system. 4. The bit inversion position in a transmission packet transmitted from the transmitting station is a bit position uniquely assigned to each of the plurality of receiving stations, and each of the plurality of receiving stations receives the reception signal. 4. The communication system according to claim 1, wherein the packet inverting means inverts the value of the bit position unique to the own station. 5. The bit inversion position in a transmission packet transmitted from the transmitting station is a bit position determined according to the type of the divided transmission data to be transmitted, and each of the plurality of receiving stations is 4. The communication system according to claim 1, wherein the value of the bit position determined according to the type of data to be received by the reception packet inverting means is inverted.