JPH10261970A - Error detection code generator, error detection circuit and error correction circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To quickly detect and correct presence of error in transmission data by generating an error detection code quickly. SOLUTION: Error detection code generators 611-61n are MOD 2 adders each employing an exclusive OR arithmetic unit (EX-OR), a specific bit of user data decided based on an error detection code generation polynomial is inputted to each generator from a data correction buffer circuit 500 to obtain each bit of an error detection code of the corresponding user data respectively. Then an error detection code data string generator 620 arranges each of the bits of the error detection codes with respect to the user data obtained by the error detection code generators 611-61n in a prescribed sequence so as to generate the error detection code data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection code generator, an error detection circuit, and an error correction circuit used for improving the reliability of data transmission.

[0002]

2. Description of the Related Art As is well known, when data transmission is performed,
It is important to check the reliability of the transmitted data on the receiving side. For this reason, conventionally, in order to confirm the reliability of transmission data, the transmission side generates an error detection code corresponding to user data to be transmitted using an error detection code generator, and adds this data to the user data. Perform data transmission.

[0003] The receiving side detects whether there is an error in the transmitted user data based on the error detection code. The receiving side requests the transmitting side to retransmit data or corrects the transmitted data as necessary.

[0004] Such detection of transmission data errors on the receiving side is generally performed using an error detection code generator similar to that used on the transmitting side. As an example of the error detection code generator, there is an error detection parity calculator configured from a shift register and an exclusive OR operation unit based on a predetermined error detection code generation polynomial. FIG. 3 shows an example.

As is well known, the above-described error detection parity calculator receives the received transmission data (user data and error detection code data) serially one bit at a time, and generates a parity generated by a predetermined data sequence. Whether or not an error has occurred is confirmed depending on whether or not there is an error.

Therefore, in the process of confirming the reliability of transmission data using such a conventional error detection code generator, all the transmission data received by the error detection code generator are input serially one bit at a time. However, there is a problem that it takes a very long time because only a short time is required.

When error correction is performed by an error correction circuit on the receiving side, the error correction processing of the received data and the above-described processing of confirming whether or not an error has occurred are repeated until error-free received data is obtained. . Therefore, when error correction is performed, the serial input operation of the transmission data to the error detection code generator as described above is performed by the number of repetitions, and there is a problem that it takes much more time.

[0008]

The conventional error detection code generator and error detection circuit have a problem that it takes a long time to input transmission data serially one bit at a time. . Further, in the error correction circuit using such an error detection circuit, the error correction processing and the error detection processing are repeated until there is no error, so that there is a problem that it takes much more time.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problem, and has as its object to provide an error detection code generator capable of generating an error detection code quickly. Another object of the present invention is to provide an error detection circuit capable of quickly detecting the presence or absence of an error in transmitted data. Another object of the present invention is to provide an error correction circuit capable of quickly correcting an error in transmitted data.

[0010]

In order to achieve the above object, an error detection code generator according to the present invention provides an error detection code for generating an error detection code for user data based on a predetermined error detection code generation polynomial. In the detection code generator, a mod2 addition operation is performed using a plurality of data bits.
A plurality of mod2 addition operation means are provided, and the bits specified based on the error detection code generation polynomial of the user data are input to the corresponding plurality of mod2 addition operation means, respectively, whereby the user data is based on the error detection code generation polynomial. User data input means for obtaining each bit of the error detection code of the user data.

In the error detection code generator configured as described above, each bit of the error detection code of the user data based on the error detection code generation polynomial is obtained using a plurality of mod2 addition operation means. Therefore, according to the error detection code generator configured as described above, the error detection code can be quickly generated.

[0012] In order to achieve the above object, an error correction circuit according to the present invention provides an error correction circuit for generating transmission data including user data and an error detection code of the user data generated based on a predetermined error detection code generation polynomial. In an error detection circuit that detects an error
By providing a plurality of mod2 addition operation means for performing the mod2 addition operation, and inputting the bits specified based on the error detection code generation polynomial among the user data included in the transmission data to the corresponding plurality of operation means, User data input means for obtaining each bit of an error detection code of user data based on the error detection code generation polynomial; each bit of an error detection code of user data obtained by the user data input means; An error detection means for detecting the presence or absence of an error by comparing each bit of the detection code is provided.

In the error detection circuit having the above configuration, each bit of the error detection code of the user data based on the error detection code generation polynomial is obtained using a plurality of mod2 addition operation means. Therefore, according to the error detection circuit having the above configuration, it is possible to quickly detect the presence or absence of an error in transmission data.

In order to achieve the above object, an error correction circuit according to the present invention is provided for generating transmission data including user data and an error detection code of the user data generated based on a predetermined error detection code generation polynomial. An error correction circuit that corrects the received error, compares at least two pieces of received transmission data, and detects a different data bit between the two data; A plurality of mod correction means for performing a correction, and a plurality of mod 2 addition operation means for performing a mod 2 addition operation using a plurality of data bits; and generating an error detection code among user data included in the transmission data corrected by the data comparison means. Inputting bits specified based on a polynomial to a plurality of corresponding arithmetic means More, the user data input means for obtaining the respective bits of the error detection code of the user data based on the error detection code generator polynomial, and each bit of the error detection code of the user data obtained by this user data input means,
Error detection means for detecting the presence or absence of an error by comparing each bit of the error detection code included in the transmission data,
When the error detecting unit detects an error, the data correcting unit controls the data correcting unit to perform data correction different from the correction performed by the previous data correcting unit on the data of the different data bits detected by the data comparing unit. And a control means.

In the error correction circuit having the above configuration, a data bit having a possibility of error is obtained by comparing at least two pieces of transmission data, and the data bit is corrected.
Then, each bit of the error detection code of the corrected transmission data is obtained by using a plurality of mod2 addition operation means, and each bit of the obtained error detection code and each bit of the error detection code included in the transmission data are obtained. To determine whether there is an error. Then, when an error is detected again, the data bit detected by the data comparing means is corrected differently from the correction previously performed by the data correcting means.

Therefore, according to the error correction circuit having the above configuration, the presence or absence of an error in the corrected transmission data is quickly confirmed, and if an error still exists, the correction is repeatedly performed. Can be quickly performed.

Further, in the present invention, the plurality of mod2 addition operation means performs an exclusive OR operation using a plurality of data bits, and further repeats the operation of performing the exclusive OR operation using the operation result. Is characterized in that a mod2 addition operation is performed.

According to this, each of the plurality of mod2 addition operation means obtains each bit of the error detection code of the user data based on the error detection code generation polynomial by repeating a simple operation process of exclusive OR operation. Therefore, an error detection code can be generated quickly.

Further, in the present invention, the plurality of mod2 addition calculating means includes a table for storing a result of the mod2 addition calculation corresponding to the plurality of data bits, and the mod2 addition calculating means corresponding to the data input from the user data input means. Is obtained by referring to a table.

According to this, the plurality of mod2 addition calculating means can obtain each bit of the error detection code of the user data based on the error detection code generation polynomial by merely referring to the table, so that the error detection code can be quickly obtained. Can be generated.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of an error correction circuit according to an embodiment of the present invention.

The error correction circuit includes a first reception data storage circuit 100, a second reception data storage circuit 200, a data comparison circuit 300, an error correction control section 400, a data correction buffer circuit 500, an error detection code generation circuit. 600.

The first reception data storage circuit 100 and the second reception data storage circuit 200 store transmission data received through different reception paths for one frame. Here, the different receiving paths are, for example, a diversity receiving path including a plurality of antennas and a corresponding receiver.

The data comparison circuit 300 compares one frame of transmission data stored in each of the first received data storage circuit 100 and the second received data storage circuit 200 for each corresponding bit. , A different bit is detected, and the position information (address) of the bit is notified to the error correction controller 400.

The error correction control unit 400 includes, for example, a microprocessor as a main control unit. The error correction control unit 400 writes and reads data to and from the first received data storage circuit 100 and the second received data storage circuit 200. This section controls each part of the error correction circuit.

The error correction control unit 400 includes an error correction control unit 401, an error determination unit 402, and a correction data output control unit 403, in addition to the above-described control functions. The error correction control means 401 first reads out the transmission data for one frame stored in the first received data storage circuit 100, and reads out the data correction buffer circuit 50.
0 is stored. Then, after that, of the transmission data stored in the data correction buffer circuit 500, the data bit corresponding to the error bit position information is subjected to a correction process, and the transmission data after the correction process is transmitted to the error detection code generation circuit 600. input.

The error determination means 402 compares the error detection code data generated by the error detection code generation circuit 600 described later with the error detection code data stored in the data correction buffer circuit 500, and Control means 4
In step 01, it is determined whether or not there is an error in the corrected transmission data.

The correction data output control means 403, when the error determination means 402 determines that there is no error,
The transmission data stored in the data correction buffer circuit 500 is input to a subsequent decoding circuit (not shown).

The error detection code generation circuit 600 includes error detection code generators 611 to 61n and an error detection code data sequence generator 620. Error detection code generators 611 to 6
1n is, for example, a MOD2 adder using an exclusive OR (EX-OR) as shown in FIG. Also,
The error detection code generators 611 to 61n correspond to the respective bits of the error detection code data composed of n bits, and determine the corresponding bits. The transmission data required to determine the corresponding bits Are input from the data correction buffer circuit 500.

The error detection code generators 611 to 61
n is MOD2 using the input transmission data.
The addition is performed, and the result of the addition is input to the error detection code data string generator 620.

Here, the "transmission data necessary for obtaining the corresponding bit" is a specific bit determined based on the error detection code generation polynomial used. Here, as an example, a case where an error detection code of transmission data (user data) having a data length of 255 bits is generated using a CRC-16 error detection code generation polynomial (1 + X ⁵ + X ¹² + X ¹⁶ ) will be described.

FIGS. 5 to 12 show each bit of user data and an error detection code generator 61 for inputting these bits.
It shows the correspondence with 1 to 61n, where n is 16 in this case. Each of FIGS. 5 to 12 is separated for the sake of convenience, but is one continuous in this order, and the left column of a vertical solid line indicates the address of each bit of user data.

The first to sixteenth columns from the right of the vertical solid line are 16 error detection code generators 611 to 61n, respectively.
In this column, the bit corresponding to "1" indicates an input bit, and the bit corresponding to "0" indicates a non-input bit. Note that this correspondence is obtained by decomposing the CRC-16 error detection code generation polynomial.

The error detection code data sequence generator 620 receives operation results from the error detection code generators 611 to 61n, and arranges the operation results in a predetermined order to generate error detection code data. The error detection code data generated in this manner is input to the error correction control unit 400.

Next, the operation of the error correction circuit having the above configuration will be described with reference to the flowchart shown in FIG.
First, one frame of transmission data (user data and error detection code data) received on different reception paths is input to the first reception data storage circuit 100 and the second reception data storage circuit 200, respectively (step 4a). Next, in step 4b, the data comparison circuit 300 compares the transmission data stored in the first reception data storage circuit 100 with the transmission data stored in the second reception data storage circuit 200, and determines the position of a different bit. (Address) is detected. The detected address is notified to the error correction control unit 400 as position information, and the process proceeds to step 4c.

In step 4c, the error correction control means 40
1 reads out the transmission data stored in the first reception data storage circuit 100 and stores it in the data correction buffer circuit 500, and proceeds to step 4d.

In step 4d, the error correction control means 40
1 is based on the position information of the different bits notified from the data comparison circuit 300 based on the data correction buffer circuit 50.
Correction processing is performed on the transmission data stored in 0, and the process proceeds to step 4e.

In step 4e, the error correction control means 40
1 reads the transmission data that has been subjected to the correction processing in step 4d, and inputs it to the error detection code generators 611 to 61n. At the time of this input, the error detection code generators 611 to 611
As described above, the bits of the transmission data necessary for obtaining the bits of the error detection code data assigned to the generators are input to 61n.

As a result, the error detection code generators 611-611
61n respectively perform the MOD2 addition operation, and then the error detection code data sequence generator 620 combines the calculation results to generate error detection code data. The error detection code data thus generated is input to the error correction control unit 400, and the process proceeds to step 4f.

In step 4f, the error determination means 402 compares the error detection code data generated by the error detection code generation circuit 600 with the error detection code data stored in the data correction buffer circuit 500.

As a result of the comparison, if they match, the process proceeds to step 4h assuming that the error bit has been corrected normally, and if not, the process proceeds to step 4g to perform the correction process again. .

In step 4g, the error correction control means 40
1 performs a correction process different from the previous correction process (step 4d) on the transmission data corresponding to the different bit position information notified from the data comparison circuit 300, and proceeds to step 4e.

The different correction processing here means that, for example, the address is "19", "97", "21" in the previous correction processing.
When the transmission data of “7” is corrected to “0”, “0”, and “1”, respectively, in this correction processing, “0”,
Different correction processes such as “1” and “0” are performed.

Eventually, while repeating the operations of steps 4g, 4e and 4f, the error detection code data generated by the error detection code generation circuit 600 and the error detection code data stored in the data correction buffer circuit 500 If they match, the process proceeds to step 4h assuming that the correction of the error bit has been completed.

In step 4h, the correction data output control means 403 inputs the transmission data stored in the data correction buffer circuit 500 to the subsequent decoding circuit, and ends the correction processing.

As described above, the error correction circuit having the above configuration uses the error detection code generation circuit 600 to generate the error detection code data based on the transmission data after the error correction processing.

The error detection code generation circuit 600 uses a plurality of MOD2s to determine each bit of the error detection code data.
Since it is generated in parallel using an adder,
Error detection code data can be generated more quickly than in the conventional case where error detection code data is generated by serially inputting transmission data bit by bit.

This MOD2 adder uses an exclusive OR operation unit as shown in FIG.
In the case of generating error detection code data of 55-bit user data, it can be realized by constructing several stages of repeating the exclusive OR operation.

For this reason, in the conventional configuration in which transmission data is serially input one bit at a time, several hundred clocks are required to generate error detection code data.
In this configuration, only a few clocks are required, so that error detection code data can be generated at a remarkable speed.

As described above, the error correction circuit having the above configuration can quickly generate error detection code data. Therefore, despite the configuration in which error-free transmission data is obtained by performing repeated error correction, the error correction circuit can quickly generate error detection code data. Error-free transmission data can be obtained.

The present invention is not limited to the above embodiment. For example, in the above embodiment, the generation of the error detection code data on the transmission data receiving side has been described. However, the error detection code generation circuit 600 may be provided on the transmission data transmitting side. According to this,
The transmitting side can also quickly generate error detection code data corresponding to the user data.

Further, in the above embodiment, the error detection code generators 611 to 61n are set to M
Instead of the OD2 adder, for example, it is constituted by a table for storing, for example, a binary sequence of transmission data to be input and an operation result obtained when the data is input to the MOD2 adder, 2 of input transmission data
A calculation result according to the base number sequence may be output.

Further, it has been described that the first reception data storage circuit 100 and the second reception data storage circuit 200 store transmission data received through different reception paths, but instead, for example, the same reception path may be used. However, the same transmission data transmitted (retransmitted) with a time difference may be stored in each. It goes without saying that various modifications can be made without departing from the spirit of the present invention.

[0054]

As described above, according to the present invention, a plurality of mod2 addition operation means and user data input means are newly provided, and each bit of the error detection code of the user data based on the error detection code generation polynomial is provided. , A plurality of mod2 addition calculation means respectively obtain the values. Therefore, according to the present invention, it is possible to provide an error detection code generator capable of quickly generating an error detection code.

Further, in the present invention, each bit of the error detection code of the user data based on the error detection code generation polynomial is obtained by using a plurality of mod2 addition operation means, and is used for error detection of transmission data. . Therefore, according to the present invention, it is possible to provide an error detection circuit capable of quickly detecting the presence or absence of an error in transmission data.

According to the present invention, at least two pieces of transmission data are compared to determine a data bit having a possibility of error, the data bit is corrected, and each bit of the error detection code of the corrected transmission data is replaced with: By using a plurality of mod2 addition operation means, it can be obtained quickly. Then, when each bit of the obtained error detection code is compared with each bit of the error detection code included in the transmission data and an error is detected, a different data bit detected by the data comparing means is detected. The data is modified so as to be different from the modification performed by the previous data modification means.

Therefore, according to the error correction circuit having the above configuration, the presence or absence of an error in the corrected transmission data is promptly checked, and if there is an error, the error correction is repeatedly performed. Can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a configuration of an embodiment of an error correction circuit according to the present invention.

FIG. 2 is a logic circuit diagram showing a configuration of an error detection code generator of the error correction circuit shown in FIG.

FIG. 3 is a diagram showing a configuration of a conventional error detection parity calculator.

FIG. 4 is a flowchart for explaining an error correction process of the error correction circuit shown in FIG. 1;

FIG. 5 is a diagram showing a correspondence relationship between each bit of user data and an error detection code generator that inputs these bits.

FIG. 6 is a diagram showing a correspondence relationship between each bit of user data and an error detection code generator that inputs these bits.

FIG. 7 is a diagram showing a correspondence relationship between each bit of user data and an error detection code generator that inputs these bits.

FIG. 8 is a diagram showing a correspondence relationship between each bit of user data and an error detection code generator that inputs these bits.

FIG. 9 is a diagram showing the correspondence between each bit of user data and an error detection code generator that inputs these bits.

FIG. 10 is a diagram showing a correspondence relationship between each bit of user data and an error detection code generator that inputs these bits.

FIG. 11 is a diagram showing a correspondence relationship between each bit of user data and an error detection code generator that inputs these bits.

FIG. 12 is a diagram showing a correspondence between each bit of user data and an error detection code generator that inputs these bits.

[Explanation of symbols]

 Reference Signs List 100 first reception data storage circuit 200 second reception data storage circuit 300 data comparison circuit 400 error correction control unit 401 error correction control unit 402 error determination unit 403 correction data output control unit 500 data Correction buffer circuit 600 ... Error detection code generation circuit 611-61n ... Error detection code generator 620 ... Error detection code data string generator

Claims (9)

[Claims] 1. An error detection code generator for generating an error detection code for user data based on a predetermined error detection code generation polynomial, comprising: a plurality of mod2 addition operation means for performing a mod2 addition operation using a plurality of data bits. And inputting the bits specified based on the error detection code generation polynomial of the user data to the plurality of mod2 addition operation means respectively corresponding to the user data, whereby the user data based on the error detection code generation polynomial is An error detection code generator comprising: user data input means for obtaining each bit of the error detection code. 2. The mod2 addition operation means performs an exclusive OR operation by using a plurality of data bits, and repeats an operation of performing an exclusive OR operation by using the operation result. The error detection code generator according to claim 1, wherein 3. The mod2 addition operation means includes a table for storing a mod2 addition operation result according to the plurality of data bits, and a mod2 addition operation result according to data input from the user data input means. The error detection code generator according to claim 1, wherein is obtained by referring to the table. 4. An error detection circuit for detecting an error occurring in transmission data including user data and an error detection code of the user data generated based on a predetermined error detection code generation polynomial, comprising: A plurality of mod2 addition operation means for performing a mod2 addition operation by using the plurality of mod2 addition operation means, and inputting bits specified based on the error detection code generation polynomial among user data included in the transmission data to the plurality of corresponding operation means, respectively. By doing, user data input means for obtaining each bit of the error detection code of the user data based on the error detection code generation polynomial, each bit of the error detection code of the user data obtained by the user data input means, Error is compared with each bit of the error detection code included in the transmission data. An error detection circuit, comprising: 5. The mod2 addition operation means performs an exclusive OR operation using a plurality of data bits, and repeats an operation of performing an exclusive OR operation using the operation result. 5. The error detection circuit according to claim 4, wherein 6. The mod2 addition operation means includes a table for storing a mod2 addition operation result according to the plurality of data bits, and a mod2 addition operation result according to data input from the user data input means. The error detection circuit according to claim 4, wherein the value is obtained by referring to the table. 7. An error correction circuit for correcting an error generated in transmission data including user data and an error detection code of the user data generated based on a predetermined error detection code generation polynomial, comprising: Comparing the transmission data,
Data comparing means for detecting different data bits between the two data; data correcting means for correcting data of different data bits detected by the data comparing means; mod2 addition for performing mod2 addition operation using a plurality of data bits A plurality of arithmetic means are provided, and bits specified based on the error detection code generation polynomial among the user data included in the transmission data corrected by the data comparing means are input to the corresponding plurality of arithmetic means, respectively. By this, user data input means for obtaining each bit of the error detection code of the user data based on the error detection code generation polynomial, each bit of the error detection code of the user data obtained by the user data input means, To compare each bit of the error detection code included in the transmission data Error detection means for detecting the presence or absence of an error, and when the error detection means detects an error, the data of different data bits detected by the data comparison means is different from the correction previously performed by the data correction means. An error correction circuit, comprising: data correction control means for controlling the data correction means so as to perform data correction. 8. The mod2 addition operation means performs an exclusive OR operation using a plurality of data bits and repeats an operation of performing an exclusive OR operation using the operation result. The error correction circuit according to claim 7, wherein 9. The mod2 addition operation means includes a table for storing a mod2 addition operation result according to the plurality of data bits, and a mod2 addition operation result according to data input from the user data input means. The error correction circuit according to claim 7, wherein?