JPH0816649A - Layout method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To accurately design an integrated circuit for the standard cell or building block system of an analog system in a short time. CONSTITUTION:This method is provided with a process A for performing logical design based on a specification, process B for performing circuit design at a transistor level based on this logical design, process C for preparing a symbol drawing at a microlevel based on this circular diagram information, process D for performing floor planning for arranging the blocks of macro assemblies of the chips of the assemblies of these blocks based on this symbol drawing, process E for performing macro layout based on the result of the process B, process G for arranging the chips of plural macro assemblies based on this layout, and process H for comparing the layout result from the process E to G with the result of the process D and performing correction when both the results are not matched.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for laying out a standard cell type or building block type semiconductor integrated circuit in an analog system. Unlike logic-based semiconductor integrated circuits, where layout automation is advancing, analog-based semiconductor integrated circuits that are susceptible to electrical or thermal influences during operation must take these effects into consideration, so various layouts are required. There is a restriction of, and a layout by manual placement and routing is required.

In the layout of analog semiconductor integrated circuits, there is a demand for a method that can be performed accurately by a simple method without requiring skill.

[0003]

2. Description of the Related Art FIG. 6 is a flow chart showing a conventional semiconductor integrated circuit layout method. First, logic design is performed based on the specifications. It implements a function level design using logical symbols such as MIL symbols so that the expected output for the input is obtained. (Step A ′) Next, based on the logic design diagram in step A ′, an optimum circuit is designed at the transistor level in consideration of the operation timing of the circuit, power consumption, and the like. (Process B ′) After the circuit design, an overall layout plan such as a block that is a set of macros or a chip layout that is a set of blocks, that is, a floor plan is determined based on the logic design drawing in the process A ′. (Process C ') In parallel with the floor plan, or when the floor plan is almost decided, the arrangement direction of the transistor and the resistor, the wiring length, etc. are taken into consideration based on the transistor level circuit design drawing in the process B'. Macro level layout is performed with emphasis on performance. (Process D ′) Since the floor plan in process C ′ is based on the logical design drawing, the initial floor plan and the size of the macro layout often differ greatly as the macro layout in process D ′ progresses. . Therefore, it is necessary to reexamine the floor plan (process E ′) while performing the macro layout.

After the macro layout is completed, a layout of a plurality of aggregates in the macro layout, that is, a block layout (step F ') is performed. In this case as well, there are differences in dimensions and the like from the floor plan performed in advance, so it is necessary to reexamine the floor plan (step G ′). Further, a layout of a plurality of aggregates in the block layout, that is, a chip layout (process H ′) is performed. Even when the chip layout is performed, the floor plan needs to be reexamined (step I ′) because the dimensions and the like are different from those of the floor plan.

When the chip layout is completed, step C '
In addition, it is verified whether the result of the layout by the process I ′ matches the circuit design drawing, and if it does not match, the correction is performed. (Process J ')

[0006]

As described above,
According to the conventional semiconductor integrated circuit layout method, the floor plan in the step C ′ is based on the logical design drawing of the step A ′ created by using the MIL symbol which is a mere logical symbol and is completely different from the actual pattern. Since it is difficult to recognize the actual dimensions at this stage, the initial floor plan will be rough.

Therefore, as the macro layout (process D '), the block layout (process F'), and the chip layout (process H ') performed on the basis of the transistor-level circuit design drawing in process B', are advanced. Since the dimensional layout and the initial floor plan do not match, review the floor plan (process E ', G',
By proceeding with the layout while performing I '),
It was necessary to improve the degree of perfection.

According to such a conventional method, the design period is prolonged and only a skilled person can perform a highly accurate layout. SUMMARY OF THE INVENTION It is an object of the present invention to solve the above problems and provide a layout method that enables an unskilled person to design an accurate semiconductor integrated circuit in a short period of time.

[0009]

According to a layout method of a semiconductor integrated circuit of the present invention for solving the above problems, a function level logic design using logic symbols is performed so that a desired output can be obtained based on a specification. Based on the result of the circuit design at the transistor level based on the result of the logic design in the process A, and the result of the circuit design in the process B, according to the layout rule of the actual circuit pattern. And a step D of creating a macro-level symbol diagram, and a step D of creating a floor plan of a block layout that is a set of macros and a chip layout that is a set of blocks based on the macro-level symbol diagram in the step C. And a step E of performing macro-level layout based on the result of the circuit design in the step B, and the step E Step F of laying out a block that is an aggregate of a plurality of macros based on the result of the macro layout, and a layout of a chip that is an aggregate of a plurality of blocks based on the result of the block layout in Step F. The verification is performed by comparing the step G to be performed, the layout result from the steps E to G, and the floor plan result in the step D, and if the two do not match, a step H to make a correction is sequentially performed. It is characterized by doing.

[0010]

According to the semiconductor integrated circuit layout method of the present invention, a symbol diagram is created in accordance with the layout rule of the actual pattern, and the floor plan is performed based on this symbol diagram. Therefore, an easy and accurate floor plan is possible. Becomes That is, since a symbol diagram conforming to the actual pattern, for example, a symbol diagram conforming to a layout rule such as a constant height, a lateral width proportional to the number of elements, and a terminal lead up and down, is used, a floor plan can be easily performed. Macro layout can be easily and quickly performed according to this floor plan.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A semiconductor integrated circuit layout method according to an embodiment of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a flow chart for explaining the layout method of the present invention, and FIG. 2 is a plan view showing a symbol diagram of this embodiment and an example of actual pattern arrangement of macro layout.

First, logic design is performed based on the specifications. This is MI so that the expected output for the input is obtained.
Perform function level design using logical symbols such as L symbols. (Process A) Next, based on the logic design drawing in Process A, an optimum circuit in consideration of the operation timing of the circuit, power consumption, etc. is designed at the transistor level. (Process B) As described above, the process A and the process B are the same as the conventional technique,
After that, a macro-level symbol diagram is created based on the circuit diagram information of the process B and the layout rule of the actual pattern. (Step C) This symbol diagram is created in accordance with the layout rule of the actual pattern, for example, the height is constant and it extends in the lateral direction according to the number of elements, and the terminal lead-out direction is up and down. As shown in FIG. 2 (a), the terminals of the power source and other electrode parts and the macro name are described.
The shape is similar to the actual pattern.

FIG. 2B is an arrangement example of the actual pattern of the macro layout corresponding to the symbol diagram of FIG. 2A. As shown in FIG. 2B, in the actual pattern, the power supply aluminum wiring 3 and the GND aluminum wiring are formed on the upper and lower sides, and a plurality of terminals 1, a transistor 5, a resistor 6, and a capacitor 7 are formed in this wiring portion and inside. These elements are arranged and connected to each other by a predetermined wiring pattern.

This actual pattern can be almost recognized by the symbol diagram shown in FIG. 2A, that is, the positions of the plurality of terminals 1, the macro name 2 and the outer shape. Based on such a macro-level symbol diagram, an overall floor plan of a block that is a group of macros and a chip layout that is a group of blocks is created. (Process D) According to this embodiment, since the floor plan is determined based on the symbol diagram according to the layout rule of the actual pattern,
At this point, a block-level or chip-level macro wiring diagram as shown in FIG. 3 can be created. Therefore, an almost accurate chip plan can be determined at this point.

FIG. 3 is a block-level macro wiring diagram created at the time of floor plan. Wiring is drawn out vertically from a plurality of terminals 1 of each macro 8 and arbitrarily connected. There is. Although such blocks are gathered to form a chip, according to this embodiment, it is possible to create a chip level macro wiring diagram at the time of floor plan.

When the floor plan in step D is determined, a macro level layout is performed with emphasis on performance, taking into consideration the transistor and resistor arrangement direction, wiring length, etc., based on the transistor level circuit design drawing of step B. To do. (Process E) In the present embodiment, the floor plan is decided based on the symbol diagram created according to the layout rule of the actual pattern, in contrast to the conventional technique in which the floor plan had to be reexamined when the macro layout was completed. Therefore, it is not necessary to review the floor plan after the macro layout, and the man-hour can be reduced.

After the macro layout is completed, a layout of a plurality of aggregates in the macro layout, that is, a block layout (step F) is performed. In this case as well, there is no difference in dimensions and the like from the floor plan performed in advance, so it is not necessary to reexamine the floor plan. Further, a layout of a plurality of aggregates in the block layout, that is, a chip layout (process G) is performed. Even when the chip layout is performed, there is no difference in dimensions and the like from the floor plan, and therefore it is not necessary to reexamine the floor plan.

After the chip layout is completed, it is verified whether the layout results of the steps D to G match the circuit design drawing, and if they do not match, the correction is performed. (Process H) Although a circuit diagram is required to perform the check in this process H, the macro connection diagram (see FIG. 3) created during the floor plan of this embodiment can also be used for this check. That is, since the verification circuit diagram required for verification is created in the form of macro symbol at the time of floor plan and is used, it is possible to save the trouble of creating the verification circuit diagram at the time of verification. .

According to the present embodiment, the number of steps for creating a symbol diagram is increased as compared with the prior art, but the number of steps for verification and correction from macro layout is less than half, so that the total number of steps can be suppressed. Becomes In the symbol diagram of this embodiment, the terminal 1 and the macro name 2 are displayed as shown in FIG. 2A, but the symbol diagram of the present invention is not limited to this.

4 (a) to 4 (c) and 5 (a) to
Various examples of symbol diagrams used in the present invention are shown in (c). FIG. 4A shows the information of each terminal and the drawing direction of the terminal. The type of this terminal can be recognized by the shape of the terminal 11, and by displaying the drawing direction 12 on each terminal 11, The layout can be done more accurately.

FIG. 4B shows an example in which the number of elements is reflected in the symbol size, and the symbol size is determined for the display of 13 elements. That is, when the number of elements is 30, the size is, for example, three times as wide as that when the number of elements is 10. FIG. 4C is an example in which the power consumption is reflected on the symbol size, and the symbol size is determined so as to correspond to the display of the power consumption 14. For example, a 0.2 watt symbol will double its size for a 0.1 watt symbol.

Further, FIG. 5A is an example in which the number of terminals is reflected in the symbol size, and the symbol size is determined so as to correspond to the display of 15 terminals. For example, for a symbol with 4 terminals, a symbol with 8 terminals is
Its size doubles. FIG. 5B shows a logical symbol displayed in the symbol. By displaying the logical symbol 16, it is possible to easily recognize what kind of circuit the macro is.

FIG. 5C shows an example in which several types of information are displayed. The type can be recognized by the number of elements 13, the power consumption 14, the logic symbol 16 and the number of terminals 15, and the shape of the terminal 11, and the extraction can be performed. Direction 12 is displayed. By displaying a plurality of pieces of information in one symbol in this way, the subsequent floor plan becomes easier and more reliable, and the dimension may differ from the floor plan even in the macro layout to the chip layout. There is no.

The combination of information displays is not limited to the embodiment shown in FIG. 5 (c), and may be appropriately set according to the specification situation.

[0025]

According to the semiconductor integrated circuit layout method of the present invention described above, a symbol diagram is created according to a layout rule of an actual pattern, and a floor plan is performed based on this symbol diagram. Therefore, the floor plan is easy and accurate. Is possible. That is, since a symbol diagram conforming to the actual pattern, for example, a constant height, a lateral width proportional to the number of elements, and a terminal lead up and down, which are similar to the actual pattern, are used, the floor plan can be easily performed. According to this floor plan, macro layout can be performed easily and in a short period of time even if it is not an expert.

[Brief description of drawings]

FIG. 1 is a flowchart illustrating a layout method of the present invention.

FIG. 2 is a diagram showing an example of a real pattern arrangement of a symbol diagram and a macro layout according to the present invention.

FIG. 3 is a block-level macro wiring diagram according to the present invention.

FIG. 4 is a diagram for explaining a first embodiment of a symbol diagram according to the present invention.

FIG. 5 is a diagram for explaining a second embodiment of a symbol diagram according to the present invention.

FIG. 6 is a flowchart illustrating a conventional layout method.

Claims (5)

[Claims] 1. A step (A) of performing function level logic design using logic symbols so that a desired output can be obtained based on specifications, and a transistor based on the result of the logic design in the step (A). A step (B) of designing a circuit at a level, and a step (C) of creating a macro-level symbol diagram according to an actual circuit pattern layout rule based on the result of the circuit design in the step (B). A step (D) of creating a floor plan of a block layout that is a set of macros and a chip layout that is a set of blocks based on the macro-level symbol diagram in the step (C); On the basis of the result of the macro layout in the step (E) of performing the macro-level layout based on the result of the circuit design, A step (F) of laying out a block which is an aggregate of a plurality of macros, and a step (G) of laying out a chip which is an aggregate of a plurality of blocks based on the result of the block layout in the step (F). And verifying by comparing the result of the layout in the steps (E) to (G) with the result of the floor plan in the step (D), and performing a correction if the two do not match. A method for laying out a semiconductor integrated circuit, wherein (H) is sequentially performed. 2. The symbol diagram in the step (C) is
2. The semiconductor integrated circuit layout method according to claim 1, wherein a pattern having a similar relationship to an actual macro layout pattern is created. 3. The symbol diagram in the step (C) is
Position and type of terminal (11) and its pulling direction (1
2. The method for laying out a semiconductor integrated circuit according to claim 1, wherein the display of 2) is created. 4. The symbol diagram in the step (C) is
2. The semiconductor integrated circuit layout method according to claim 1, wherein the size is determined based on the number of elements (13), the power consumption (14), or the number of terminals (15). 5. The symbol diagram in the step (C) is
2. The semiconductor integrated circuit layout method according to claim 1, wherein a logical symbol corresponding to the symbol diagram is displayed.