JP3925679B2 - Semiconductor device and semiconductor design device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device capable of shortening a design period and a semiconductor design device.
[0002]
[Prior art]
At present, many semiconductor devices are equipped with hard macros such as RAM and ROM as the scale of semiconductor devices increases. However, when the area occupied by the hard macro in the semiconductor chip increases, the wiring to be connected across the hard macro becomes long, and the delay time becomes a problem. For example, as shown in FIG. 2, a wiring 28 from a primitive cell 24 such as a logic circuit other than the hard macro 22 to an I / O cell 26 that is an external terminal of the semiconductor device 20 may be very long.
[0003]
On the other hand, conventionally, by adding a normal buffer (repeater) as a relay point for driving the wiring 28 in the middle of the wiring 28, that is, between the areas where the hard macros 22 are arranged, wiring delay is reduced. Reductions are being made.
[0004]
In this case, in the conventional semiconductor device, as shown in FIG. 3, between the areas where the hard macros 22 are arranged, logic circuit arrangement columns (generally, ROW () 30) called 30)) is newly provided or provided in advance, a required number of additional buffers 32 are arranged in the arrangement row 30, and a power supply line for supplying power to these additional buffers 32 The VDD and the ground line VSS were connected to reconnect the wiring.
[0005]
However, such a task of providing a new arrangement row region or connecting a wiring for supplying power to an additional buffer particularly requires a short TAT (design period) such as an ASIC (use-limited IC). This is a serious adverse effect in the design form. Also, depending on the placement of the hard macro, the placement row may not be provided, or even if the placement row can be provided, the placement of the hard macro may have to be changed due to a problem in operation timing. .
[0006]
On the other hand, it is possible to provide an arrangement row around the hard macro in advance. However, since the configuration of the arrangement row changes according to the type and arrangement of the hard macro, the number of work steps increases accordingly. In addition, if the placement of the hard macro is changed, the arrangement sequence must be redesigned in consideration of the influence, so that the design man-hour increases in the conventional semiconductor device using the hard macro. was there.
[0007]
[Problems to be solved by the invention]
An object of the present invention is to provide a semiconductor device and a semiconductor design device capable of shortening the design period even when a hard macro is used in view of the problems based on the conventional technology.
[0008]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is a semiconductor device having a hard macro having a predetermined function and an external terminal for using this function,
The hard macro includes at least one buffer independent of a function of the hard macro, and an input terminal and an output terminal of the buffer have the hard macro independent of an external terminal for using the function of the hard macro. The present invention provides a semiconductor device characterized by being formed as an external terminal.
Here, it is preferable that an input terminal and an output terminal of the at least one buffer are connected to a wiring passing through the periphery of the hard macro and used as a repeater for driving the wiring.
Here, the external terminal of the hard macro means a terminal for connecting to a circuit other than the hard macro in the semiconductor device, an I / O cell, or the like.
[0009]
Further, the present invention provides means for generating the hard macro described above , means for generating a netlist of the semiconductor device described above including the hard macro, and the semiconductor device using the generated netlist. Means for performing layout and wiring of the layout and generating a layout pattern;
Means for analyzing the operation timing of the semiconductor device based on the layout wiring information of the layout pattern after layout, means for detecting a wiring passing through the periphery of the hard macro and having an error in the operation timing; and Detecting a position of a buffer included in the hard macro, and detecting a buffer having an optimum operation timing of the wiring;
Provided is a semiconductor design apparatus comprising means for updating the net list and means for correcting the layout pattern so as to reconnect the wirings through the detected buffer. is there.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a semiconductor device and a semiconductor design apparatus of the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.
[0011]
FIG. 1 is a conceptual diagram of an embodiment of a semiconductor device of the present invention.
The semiconductor device 10 in the illustrated example includes a hard macro 12 having a predetermined function and an external terminal for using the function, such as a RAM and a ROM. The hard macro 12 is automatically generated with a layout pattern corresponding to, for example, a size, an aspect ratio, and the like inputted as parameters by a generator as one of semiconductor design apparatuses.
[0012]
As shown in the figure, the hard macro 12 includes a plurality of buffers 14 that are completely independent of the functions thereof, and the input terminal and the output terminal of each buffer 14 use the original functions of the hard macro 12. Therefore, the external terminals of the hard macro 12 are completely independent from the external terminals for the purpose. That is, the hard macro 12 is provided with an external terminal for using the original function of the hard macro 12 and an external terminal for using the buffer 14.
[0013]
In the semiconductor device 10 of the present invention, a buffer 14 independent of the original function of the hard macro 12 is incorporated in the hard macro 12. For this reason, by using the buffer 14 as a repeater for driving the wiring, the wiring generated in the wiring 16 passing through the periphery of the hard macro 12 can be detected for the first time at the verification stage of the operation timing after the layout design is completed. The delay error can be solved in a short time, and the design period of the semiconductor device 10 can be shortened.
[0014]
Note that the hard macro mounted on the semiconductor device of the present invention is not limited to one automatically generated by a generator, for example, a custom-designed hard macro such as a CPU core or an analog circuit, or a hierarchical macro in the hierarchical placement and routing method. May be. The buffer serving as a repeater is preferably arranged at the periphery of the hard macro 12 if the wiring cannot pass over the hard macro 12, but if the wiring can pass over the hard macro 12, You may arrange | position in arbitrary positions.
[0015]
Next, the semiconductor design apparatus of the present invention will be described.
The semiconductor design apparatus of the present invention is basically a software program such as a CAD tool that operates on hardware such as a workstation. However, the semiconductor design apparatus of the present invention is not limited to a specific hardware configuration or software program, and other means for realizing the operation of the semiconductor design apparatus of the present invention described below may be used. It is feasible.
[0016]
Hereinafter, a procedure for designing the semiconductor device of the present invention using the semiconductor design device of the present invention will be described.
[0017]
First, as Step 1, a necessary hard macro such as a RAM is generated using the above-described generator.
Then, as step 2, a logic list other than the hard macro is performed together to create a net list of the entire semiconductor device. Then, using this net list, an automatic placement and routing tool is used to place and route the layout of the semiconductor device, and a layout pattern corresponding to the net list is generated.
[0018]
After the layout is finished, as step 3, from the placement information of the hard macro on the semiconductor chip and the information of the external terminals of the hard macro itself, the position of the buffer incorporated in the hard macro, that is, each buffer. Correspondingly, the position of the external terminal formed in the hard macro is extracted and stored.
On the other hand, as step 4, the wiring passing through the periphery of the hard macro is extracted from the layout wiring information of the layout pattern and stored.
[0019]
After that, as step 5, RC (resistance component and capacitance component) information is extracted from the layout wiring information of the layout pattern, delay calculation is performed based on the information, and operation timing is analyzed based on the delay calculation.
As a result, in step 6, it is searched whether or not the wiring causing the error includes a wiring passing through the periphery of the hard macro stored in step 4, and the corresponding wiring is selected.
[0020]
Then, in step 7, it is judged that the buffer that can be used as a repeater in the hard macro stored in step 3 can use the one closest to the wiring path causing the timing error in step 6. Then, the most suitable one is adopted as a repeater. At this time, one buffer is not necessarily used for one wiring, and a necessary number of buffers may be used as necessary. Note that the input terminals of unused buffers are connected to the ground or the power supply.
[0021]
Subsequently, in step 8, the netlist information is updated so that the wiring having an error is reconnected through the buffer employed in step 7. Then, in the same way as the updated netlist information, wiring on the layout is performed again.
Finally, in step 9, the wiring other than the wiring that can be corrected as described above is corrected by arranging a buffer in an existing arrangement row as before and using it as a repeater.
[0022]
In the above embodiment, the buffer is disposed in the peripheral portion of the hard macro on the assumption that the wiring cannot pass over the hard macro. However, the present invention is not limited to this, and the multilayer wiring layer is provided. If the wiring can pass over the hard macro, a buffer may be arranged at an arbitrary position of the hard macro. In this case, the external terminals of the buffer may also be appropriately changed as necessary, such as forming from one side to the other side opposite to this, or providing a plurality of external terminals for one buffer.
[0023]
The semiconductor device and semiconductor design device of the present invention are basically as described above.
Although the semiconductor device and the semiconductor design device of the present invention have been described in detail above, the present invention is not limited to the above embodiments, and various improvements and modifications may be made without departing from the spirit of the present invention. Of course.
[0024]
【The invention's effect】
As described above in detail, the semiconductor device of the present invention includes a buffer that is independent of its original function, and a hardware device that includes an external terminal for a buffer that is independent of the original external terminal for using the function. It is equipped with a macro.
The semiconductor design device of the present invention generates a layout pattern from the net list of the semiconductor device of the present invention, analyzes the operation timing of the semiconductor device based on the layout wiring information of the layout pattern after layout, Detect wiring that has an error in the operation timing from the wiring that passes through the periphery, and detect the buffer with the optimal wiring operation timing from the buffers included in the hard macro. Then, the netlist is updated and the layout pattern is corrected so that the wiring connection is performed again.
Therefore, according to the semiconductor device and the semiconductor design apparatus of the present invention, even when a hard macro occupying a relatively large layout area is mounted, wiring delay errors of wiring to be connected across the hard macro can be reduced in a short time. The design period can be greatly shortened. In addition, according to the semiconductor device and the semiconductor design device of the present invention, since the buffer serving as a repeater is mounted inside the hard macro, even if the hard macro is re-arranged, the corresponding processing is performed thereafter. Can be performed in a short time.
[Brief description of the drawings]
FIG. 1 is a conceptual diagram of one embodiment of a semiconductor device of the present invention.
FIG. 2 is a conceptual diagram of an example of a semiconductor device.
FIG. 3 is a conceptual diagram of an example of an arrangement row.
[Explanation of symbols]
10 Semiconductor device 12 Hard macro 14 Buffer 16, 28 Wiring 20 Semiconductor device 22 Hard macro 24 Primitive cell 26 I / O cell 30 Arrangement column 32 Buffer VDD Power supply line VSS Ground line

Claims (3)

A semiconductor device having a hard macro having a predetermined function and having an external terminal for using this function,
The hard macro includes at least one buffer independent of a function of the hard macro, and an input terminal and an output terminal of the buffer have the hard macro independent of an external terminal for using the function of the hard macro. A semiconductor device formed as an external terminal.   2. The semiconductor device according to claim 1, wherein an input terminal and an output terminal of the at least one buffer are connected to a wiring passing through the periphery of the hard macro and used as a repeater for driving the wiring. 2. A means for generating a hard macro according to claim 1, a means for generating a net list of the semiconductor device according to claim 1 including the hard macro, and a layout of the semiconductor device using the generated net list. Means for performing the placement and routing of, and generating a layout pattern,
Means for analyzing the operation timing of the semiconductor device based on the layout wiring information of the layout pattern after layout, means for detecting a wiring passing through the periphery of the hard macro and having an error in the operation timing; and Detecting a position of a buffer included in the hard macro, and detecting a buffer having an optimum operation timing of the wiring;
A semiconductor design apparatus comprising: a means for updating the netlist and a means for correcting the layout pattern so as to reconnect the wirings through the detected buffer.

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