JP3221567B2 - Semiconductor integrated circuit and clock supply method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a structure of a macro block and a technique for supplying a clock to the macro block.

[0002]

2. Description of the Related Art With the increase in the degree of integration of semiconductor integrated circuits, macros are often used in the development of microcomputers and ASICs. Among these products, a macro having a relatively large circuit size and size, such as a CPU macro, is also used.

FIG. 10 is a diagram schematically showing an example of a layout of a conventional semiconductor chip. Referring to FIG. 10, when designing the semiconductor chip 1010 using the macro 1000 having the clock input terminal 1004, if the macro 1000 is arranged at a position as shown in FIG.
Since the macro 1000 is bypassed, the wiring length increases, and accordingly, the wiring capacity also increases.

When a design is required to adjust the clock phase between macros and elements, a buffer 1005 for delay adjustment is added.

[0005] Such a wiring delay is a problem to be improved in semiconductor chip design.

Also, with the increase in the design of semiconductor chips that handle macros, shortening the design period of the macros themselves has become an issue, and contrivances for facilitating macro design are required.

As a method for solving the problem of an increase in wiring capacitance due to an unnecessary wiring length when a clock wiring bypasses a macro when designing a semiconductor chip, for example, Japanese Patent Application Laid-Open No. 7-20200
Japanese Patent Application Laid-Open No. 1-2005-124294 proposes a configuration in which a clock input terminal of a macro is arranged on the periphery of the macro as shown in FIG. ing. Referring to FIG. 11, the macro cell 11 includes a clock wiring 21 for supplying a clock signal to the elements in the macro cell 11, and a wiring path 22 connected to the clock wiring 21 from each input terminal 12, 13, 14, 15 of the macro cell 11. , 23, 24, and 25, and a connection point 26 between the clock wiring 21 and the wiring paths 22, 23, 23, and 25.

[0008]

However, the semiconductor integrated circuit described in Japanese Patent Application Laid-Open No. Hei 7-202001 has the following problems.

In the macro cell, a wiring path connected to each clock input terminal is wired at a connection point 26 and treated as the same signal, and the clock input signal wiring is the same wiring inside the macro. According to this, the same electrical characteristics can be obtained regardless of which terminal is connected.

However, in the configuration shown in FIG.
As a result, the wiring capacity of all the clock input signals inside the macro affects the clock signal at the time of designing the semiconductor chip, so that a substantial improvement in reducing the wiring capacity cannot be achieved.

Further, Japanese Patent Application Laid-Open No. Hei 7-202001 also discloses a method of short-circuiting immediately before the first stage clock signal element on each side in order to eliminate unnecessary capacity of an unused clock signal. .

However, according to this method, for example, in the macro layout step 458 shown in FIG. 8, each of the input terminals and the signals of the respective two systems connecting the terminal and the first-stage element have the same electrical characteristics. It is necessary to pay attention to the wiring, and also in the stage of designing a semiconductor chip, a step of operating the internal wiring of the macro occurs at the time of layout design.

As described above, Japanese Patent Application Laid-Open No. 7-202001 discloses
In the configuration of the macro cell described in Japanese Patent Application Laid-Open Publication No. H10-209, manual work such as correction of circuit information is required when laying out using an automatic layout tool during layout design.

FIG. 8 is a flowchart showing a conventional design process for designing a layout of a macro. FIG. 8 is a diagram showing a process of arranging clock input signals of the same logic as terminals on each side of the macro on a logic circuit. .

In step 450, terminal arrangement information is extracted and created from the logic circuit.

In step 451, a terminal is added so that a single clock signal as a logic circuit is arranged on each side of the macro.

In step 452, a dummy I /
Add O terminal.

In step 453, the netlist is modified so that the clock input terminals arranged on each side of the macro and the clock signal having the same logic on the logic circuit are associated with each other.

In a step 458 after the floor planning step 454, the power ring wiring step 455, the primitive primitive forcible placement step 456, and the macro primitive placement step 457, the clock wiring is corrected after the automatic wiring. This is to correct the wiring so that the wiring from each clock input terminal to the first stage element has the same delay so that the electrical characteristics are the same regardless of which clock input terminal is selected. In addition,
In the primitive initial compulsory arrangement step 456, elements to be connected first are arranged manually by taking into consideration that each clock input signal has the same electrical characteristics in the macro. In a macro primitive placement step 457, elements are automatically placed in a macro.

In the GDS creation step 459, data which is the basis for creating mask pattern data is created from the coordinate information of wirings and elements obtained by the automatic placement and routing processing.

Step 461: DRC (Design Rule Check)
Checks the design rules (eg, wiring pitch, etc.) of the GDS file, and checks the LVS (Layout Versus
Schematic) compares the netlist (circuit connection information) used by the automatic placement and routing tool with the GDS. The misplaced wiring in the wiring process, etc. in the automatic placement and routing rules, and the incorrect wiring at the time of manual correction are performed. Check if there is any. At step 460, the netlist is modified for LVS.

Step 460 and wiring capacitance data correction step 4
63 is a process for eliminating the difference between the netlist used in the layout and the netlist used in the logic design.

In the configuration of the macro cell described in the above-mentioned Japanese Patent Application Laid-Open No. Hei 7-202001, one signal is divided into four at the time of layout in terms of logical design.

For this reason, as shown in the macro layout process of FIG. 8, it is necessary to perform terminal arrangement information correction and netlist correction 451 and 453, in which one signal is assigned to different terminals.

Since the netlist at the time of logic design is different from the netlist at the time of layout, after the layout is completed, the data for delay verification is corrected for delay verification.
Then, a circuit information correction step 460 for matching processing between the figure data after the placement and routing and the circuit information occurs.

FIG. 9 is a diagram showing steps in a case where a layout design of a semiconductor chip is performed using a conventional macro. A method of short-circuiting unused clock wiring in the macro to reduce the wiring capacitance inside the macro is used. In this method, the state of the wiring is checked when the layout and the wiring are all completed by the automatic layout tool in the semiconductor chip design (step 650), and the layout graphic data is completed.

That is, by modifying the layout graphic data manually or the like, clock connection such as unused clock wiring of the macro is performed (step 651), and the DRC / LV is connected.
When the S processing is performed (step 652) and a connection error occurs in the clock connection (step 653), the layout graphic data is corrected again (step 651), and the TAT (turn around time) increases.

Accordingly, the present invention has been made in view of the above problems, and an object of the present invention is to reduce an increase in wiring capacitance due to a macro bypass of a clock signal when designing a semiconductor chip, and to simplify the design. An object of the present invention is to provide a circuit and a clock supply method thereof.

[0029]

In order to achieve the above object, the present invention comprises a plurality of clock input terminals which are arranged in a balanced manner around the macroblock in accordance with the shape of the macroblock. Includes a selection element in which a plurality of signal wirings respectively connected to the plurality of clock input terminals are connected to input terminals, respectively.
An output terminal of the selection element is connected to an input terminal of a circuit element to which a clock signal is supplied, and a clock signal from a terminal selected as an input terminal of the clock signal at the time of design, among the plurality of clock input terminals, is The clock signal is selectively supplied to the circuit element to which the clock signal is supplied through the selection element. In the present invention, each side of the macro block is provided with at least one clock input terminal. In the present invention, an unused clock input terminal that is not selected as a clock input terminal among the plurality of clock input terminals is supplied with a fixed potential of either a power supply potential or a ground potential.

Further, in the clock supply method for a semiconductor integrated circuit according to the present invention, at least one clock input terminal is provided in each periphery of the macro block, and the macro block is connected to the plurality of clock input terminals. With a selection circuit that connects each of the wires to the input end,
In supplying a clock signal to a circuit element to which a clock signal is supplied inside the macro block, without bypassing the macro block, an optimal clock input terminal is selected from the viewpoint of a clock supply source, and the selected clock input terminal is selected. Is selectively supplied to the circuit element to which the clock signal is supplied via the selection circuit.

According to the present invention having such a configuration, in the layout design of a semiconductor chip, in a macro terminal configuration capable of reducing the wiring capacity and delay time of a clock signal, the layout automation of the macro design and the layout design of the semiconductor chip are realized. It will make it easier.

[0032]

Embodiments of the present invention will be described. The present invention, in one of its preferred embodiments,
Referring to FIG. 1, the macro (120) has a plurality of clock input terminals (101, 102, 103, 104) around the macro. In the example shown in FIG. 1, one clock input terminal is provided for each side of the macro. The clock input signal of the macro 120 is supplied to terminals (101, 102, 10
3, 104), and signal lines (105, 106, 107, 108) connecting the terminals (101, 102, 103, 104) and the first-stage element (100). The signals are electrically independent of each other and have different electrical characteristics. Unused clock input terminals other than the clock input terminal selected at the time of semiconductor chip design are set to a fixed potential such as a power supply potential, and a clock signal from the selected clock input terminal supplies a clock via the first-stage element (100). It is selectively supplied to the buffer circuit 110.

In one embodiment of the present invention, the macro has a plurality of clock input terminals in the periphery, and the optimum clock input terminal is provided regardless of the position of the macro at the time of layout design of the semiconductor chip. , And only the wiring capacitance of the signal connected to the selected clock input terminal is added to the clock signal wiring capacitance inside the macro.

In the present invention, a plurality of clock input terminals provided in a macro are logically independent. Therefore, during layout design, there is no need to pay special attention to the wiring of clock input signals, so that automatic The layout can be performed using a layout tool. Also, no special consideration is required for the clock input signal for generating the delay information data when performing the delay verification. Further, according to the present invention, connection of a clock signal to a macro when designing a semiconductor chip is facilitated.

[0035]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram for explaining an embodiment of the present invention, and is a diagram showing a layout image. FIG.
Referring to FIG. 2, the macro 120 has four clock input terminals 1
01, 102, 103, 104, signals 105, 106, 107, 107 connected to terminals 101, 102, 103, 104, and signals 105, 106, 10
Element 100 to which 7, 107 is connected, and output signal 10 of element 100
It has a clock supply buffer 110 connected through the interface 9 and a clock signal 111 inside the macro.

In the logic design of the macro, the clock input signal is logically divided into a predetermined number according to the physical shape of the macro on the layout.

In the macro having the shape as shown in FIG. 1, preferably, a total of four clock input terminals are provided, one for each side of the macro. This arrangement of the clock input terminal enables the clock wiring to be connected to the clock input terminal in the shortest time without circumventing the macro, regardless of where the macro is placed on the chip during layout design of the semiconductor chip. .

In the input portion of the clock signal, the logic circuit includes the signal lines 105, 106,
It is composed of elements 100 to which the signal lines 105, 106, 107 and 108 are connected. The element 100 is an AND circuit (AN
D) or a NAND circuit (NAND), of course, may be replaced by an OR or an arbitrary circuit element capable of selecting any of a plurality of signals. For example, the element 100 may be configured by an OR circuit (OR) or a NOR circuit (NOR), and an unused clock input terminal may be set to the ground potential.

Note that the internal delay of the element 100 is taken into account when designing the logic of the macro 120 and is resolved inside the macro, so that it does not affect the delay of the clock signal in the semiconductor chip design.

In the layout design process of the logic circuit, when the layout designer arranges the macro terminals, as shown in FIG. 1, the terminals 101, 102, 103 and 104 corresponding to the clock input signal The terminal arrangement information data is created in consideration of the arrangement on each side of 120.

Thereafter, each of the clock input signals 105, 106, 10
The layout of the element 100 to which the clock input signals 7, 108 and the clock input signals 105, 106, 107, and 108 and other macro internal elements are arranged, and the wiring of signals are performed using an automatic layout tool.

FIG. 2 is a diagram showing a layout image when the semiconductor chip 210 is designed using the macro of one embodiment of the present invention shown in FIG. Referring to FIG. 2, on a semiconductor chip 210, a macro 200, another macro 205, and an element 206 for receiving a clock signal are arranged, and each of the macros 200, 205 and the element 206 includes a clock driver 201. Is connected to a clock signal 202 driven by

In the design of the semiconductor chip 210, when wiring the clock signal 202, the clock input terminal 203 is selected and connected so that the wiring of the clock 202 has the shortest wiring delay without bypassing the macro 200. I do.

The macro 200, other macros 205, and a clock receiving element for suppressing a wiring delay due to a bypass of the wiring of the clock signal 202 and an increase in wiring capacitance.
The position adjustment of each of the 206 and the phase adjustment of the clock signal are also performed.

FIG. 3 is a flowchart showing a series of steps in layout designing a macro to which the present invention is applied.

Referring to FIG. 3, the layout designer
Based on the information of the clock input signal determined in the logic design stage according to the shape of the macro, the terminal arrangement information is determined in consideration of where to place the terminal of the clock input signal in the macro (step 300).

Next, a dummy I / O buffer is added to input circuit information to the automatic layout tool (step 301).

Since each terminal of the clock input and the signal connected to the terminal are logically divided, a floor plan process 302, a power ring wiring process 303, a first-stage primitive automatic placement process 304, a macro The primitive placement step 305 and the automatic wiring step 306 can be executed by an automatic layout tool without performing manual work.

The first-stage primitive refers to an element (100 in FIG. 1) to which the clock input terminal of the macro is connected first. In this embodiment, this primitive and the clock input terminal arranged on each side of the macro Since it is not necessary to make the distances between the signal wirings the same, automatic placement can be performed using an automatic placement tool in step 304. In the macro primitive placement step 305, elements in the macro are automatically placed. On the other hand, in the layout design using the conventional macro (see FIG. 11), the wiring length from the primitive at the first stage to the terminal arranged on each side of the macro needs to be the same. Must be located in the center and on the CAD terminal,
The placement is done manually.

In one embodiment of the present invention, there is no need to manually correct the signal connected to each clock input terminal after wiring is completed by the automatic layout tool. The GDS step 307, the DRC / LVS step 308, and the wiring capacitance extraction step 309 can also be processed by a tool for each step without performing any special manual work.

FIG. 4 is a flowchart showing a series of steps in designing a layout of a semiconductor chip using a macro to which the present invention is applied.

When the layout designer determines the layout position of the macro on the semiconductor chip, the layout designer asks the logic designer how the clock terminal of the macro should be connected to the clock signal in the semiconductor chip. contact.

Based on the information from the layout designer, the logic circuit designer connects the clock signal and the macro clock input terminal in the circuit information (net list) of the logic circuit, and supplies the unused clock input terminal to the power supply. The connection is processed (step 500).

Next, a clock connection check is performed by a circuit wiring information check tool (step 501).
After confirming that there is no connection error or the like, placement / wiring is performed using an automatic layout tool (step 502).

In the layout designing process, each clock input terminal of the macro has already been treated and can be left to an automatic layout tool.

Next, a second embodiment of the present invention will be described. FIG. 5 is a diagram showing a layout image of the second embodiment of the present invention. Referring to FIG. 5, when the shape of the macro 720 is rectangular, the clock input terminals 700, 701, 702, 703, 704, and 705 of the macro 720 are As shown in FIG. 7, it is preferable to arrange two long sides and one short side. In such an arrangement of the clock input terminals, the clock input signals 706, 707, 708, 709,
Since 710 and 711 are independent of each other, the layout designer can rely on the automatic layout tool processing without paying special attention to the wiring of each clock input signal.

Next, a third embodiment of the present invention will be described. FIG. 6 is a diagram showing a layout image of the third embodiment of the present invention. Referring to FIG. 6, the macro 820 includes clock terminals 801, 802, 803, and 804 and a clock input signal 80.
5, 806, 807, 808, and buffers 809, 810, 811, 812,
Buffer output signals 813, 814, 815, 816 and signal signal 81
3, 814, 815, 816, a device 800 to which the device is connected, and a clock driver 818 connected via an output signal 817 of the device 800.
And a clock signal 819 inside the macro 820.

The internal delay in the buffers 809, 810, 811, and 812 and the subsequent signal propagation time are taken into account at the time of logic synthesis of the macro, and are solved at the macro design stage.

FIG. 7 is a diagram showing a layout image when the semiconductor chip 910 is designed using the macro of the third embodiment of the present invention shown in FIG. Referring to FIG. 9, in the design stage of the semiconductor chip 910, the clock wiring 9
The wiring capacity of the clock input terminal 903 of the macro 900 added to 02 is the wiring capacity of the wiring 904 from the terminal 903 in the macro 900 to the input terminal of the buffer 907.
It will be very small.

The buffer 901 on the semiconductor chip 910
In the case where the clock wiring 902 is configured to perform phase adjustment using a clock tree or the like, the skew between the clock terminals of the elements 905 and 906 to which the clock signal 902 including the macro 900 is supplied is “0”. Is adjusted to
The clock phase between the macro 900 and the other clock-supplied elements 905 and 906 can be adjusted with high accuracy.

[0061]

As described above, according to the present invention,
The following effects are obtained.

A first effect of the present invention is that, when designing a semiconductor chip, it is possible to suppress and reduce an increase in wiring capacity due to a macro signal bypass of a clock signal.

The reason is that, in the present invention, the macro has a plurality of terminals around the macro, and when designing the layout of the semiconductor chip, the optimum clock terminal is set regardless of the position of the macro. This is because it is possible to select and connect. In addition, this is because only the wiring capacitance of the signal connected to the selected clock input terminal is added to the wiring capacitance of the clock signal inside the macro.

A second effect of the present invention is that when designing a semiconductor chip, a macro layout design is simplified in a macro configuration capable of suppressing and reducing an increase in wiring capacitance due to a macro bypass of a clock signal. It is.

The reason is that, in the present invention, since a plurality of clock input terminals provided in a macro are configured to be logically independent, circuit information handled in a logical design is equivalent to circuit information handled in a layout design. That is because.

With this configuration, the layout operator can
The macro can be laid out without paying special attention to the wiring of the clock input signal. Also, there is no need to pay special attention to the clock input signal when creating the delay information data when performing the delay verification.

A third effect of the present invention is that a clock signal can be easily connected to a macro at the time of designing a semiconductor chip. It also facilitates correction when a change is required in the clock signal connection.

The reason is that, in the present invention, a plurality of clock input terminals provided in a macro are logically independent. This is because connection information for supplying a clock to a macro at the time of designing a semiconductor chip can be easily set by logic circuit information such as a logic description language.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a macro according to an embodiment of the present invention.

FIG. 2 is a diagram schematically illustrating a layout of a semiconductor chip using a macro according to an embodiment of the present invention.

FIG. 3 is a diagram showing a macro layout design process in one embodiment of the present invention.

FIG. 4 is a diagram showing a semiconductor chip design process using a macro according to an embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of a macro according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a macro according to a third embodiment of the present invention.

FIG. 7 is a diagram showing a layout image of a semiconductor chip using a macro according to a third embodiment of the present invention.

FIG. 8 is a diagram showing a conventional macro layout design process.

FIG. 9 is a diagram showing a conventional design process.

FIG. 10 is a diagram schematically showing a layout of a semiconductor chip using a conventional macro.

FIG. 11 is a diagram showing a configuration of a semiconductor integrated circuit described in Japanese Patent Application Laid-Open No. 7-202001.

[Explanation of symbols]

100, 800 First-stage element 120, 200, 205, 820, 900, 905 Macro 101-104, 203, 700-705, 801-8
04, 903 Clock input terminal 105-108, 706-711, 813-816, 9
08 Clock signal wiring in macro 110, 809 to 812, 818, 901, 907 Clock buffer (driver) circuit 111 Clock signal 206 Element 210, 910 Semiconductor chip

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 G06F 1/10 H01L 21/822 H01L 27/04

Claims (10)

(57) [Claims] A plurality of clock input terminals arranged in a balanced manner around the macro block in accordance with the shape of the macro block, wherein the macro block is internally connected to the plurality of clock input terminals, respectively. A plurality of signal wirings , a selection element having a plurality of input terminals connected to each of the plurality of signal wirings, and a clock signal having an output terminal of the selection element connected to the input terminal. and a circuit element of the supply destination, the one of the plurality of clock input terminals of the peripheral macroblocks, at design time, the clock signal from the selected terminal as an input terminal for a clock signal, the clock through the selection device A semiconductor integrated circuit selectively supplied to a circuit element to which a signal is supplied. 2. The macro block according to claim 1, further comprising at least one clock input terminal on each side of the macro block.
A selection element in which a plurality of signal wirings respectively connected to the plurality of clock input terminals are respectively connected to input terminals.
When, and a circuit element connected to the clock signal supply destination to the output terminal the input terminal of the selection element, the plurality of clock input terminal, a clock signal from the selected terminal as an input terminal for a clock signal Is selectively supplied to the circuit element to which the clock signal is supplied through the selection element. 3. A fixed potential of a power supply potential or a ground potential is supplied to an unused clock input terminal that is not selected as a clock input terminal among the plurality of clock input terminals. 3. The semiconductor integrated circuit according to 1 or 2. 4. The unused element which is not selected as a clock input terminal among the plurality of clock input terminals, wherein the selection element comprises an AND circuit or an AND circuit having an input terminal connected to the plurality of clock input terminals. The power supply potential is supplied to the clock input terminal.
Or the semiconductor integrated circuit according to 2. 5. The unused element which is not selected as a clock input terminal among the plurality of clock input terminals, wherein the selection element comprises an OR circuit or a NOR circuit whose input terminal is connected to the plurality of clock input terminals. 2. The clock input terminal is supplied with a ground potential.
Or the semiconductor integrated circuit according to 2. 6. The macro block includes a plurality of buffer circuits each having an input terminal connected to the plurality of clock input terminals, and output terminals of the plurality of buffer circuits are connected to input terminals of the selection circuit. 3. The semiconductor integrated circuit according to claim 1, wherein: 7. At least one clock input terminal is provided on each side of the macro block. A plurality of signal lines connected to the plurality of clock input terminals are connected to input terminals of the macro block, respectively. When a semiconductor chip is designed, a clock signal is supplied from a clock input terminal of the macro block to a circuit element to which a clock signal is supplied inside the macro block. Without detouring, selecting an optimal clock input terminal from the viewpoint of a clock supply source, and selectively supplying a clock signal from the selected clock input terminal to the circuit element to which the clock signal is supplied via the selection element A clock supply method for a semiconductor integrated circuit. 8. A fixed potential of a power supply potential or a ground potential is supplied to an unused clock input terminal not selected as a clock input terminal among the plurality of clock input terminals. 8. A clock supply method for a semiconductor integrated circuit according to claim 7. 9. A plurality of clock input terminals arranged in a balanced manner around the macro block in accordance with the shape of the macro block are prepared, and in the macro block, a signal from the clock input terminal is first supplied. A primitive element connected to a plurality of signal wirings respectively connected to the plurality of clock input terminals, for selectively outputting a clock signal from a selected used clock input terminal to a next-stage circuit element A macroblock, comprising: 10. A plurality of clock input terminals arranged in a balanced manner around a macro block, wherein a primitive element to which a signal from the clock input terminal is first connected in the macro block is a plurality of primitive elements. A method of designing a semiconductor integrated circuit device using a macro block including an element for selectively outputting a clock signal from a selected used clock input terminal to a next stage among a plurality of signal wirings respectively connected to a clock input terminal In (a), after determining the arrangement of the macro blocks on the semiconductor integrated circuit device, determining the connection between a clock input terminal of the macro block and a clock signal in the semiconductor integrated circuit device, In the circuit information of the logic circuit of the integrated circuit device, a plurality of clock input terminals of the macro block are provided. Connecting a clock input terminal selected to be used to a clock signal of the semiconductor chip and setting an unused clock input terminal to a fixed potential; and (b) checking the clock connection using a wiring check system. And (c) when there is no connection error in the clock connection, a step of arranging and wiring by an automatic arrangement and wiring system.