JPH08154207A - Solid-state image pickup element and its drive method - Google Patents

Abstract

PURPOSE: To obtain a solid-state image pickup element and its drive method reading charges of all pixels without charging the order of them regardless of provision of two vertical transfer register electrodes per one photodiode. CONSTITUTION: Two electrodes of vertical transfer registers (VCCD) 3 are provided for one photodiode(PD) 4; the charges in odd number lines of PDs 4 are transferred to the VCCDs 3, received by a storage area 2; and the period of the transfer clock for VCCDs 8 in the storage area 23 is selected half a period T0 of the transfer clock for the VCCDs 3 in an image pickup area 1 (That is, the drive frequency is doubled). Thus, a charged packet and an idle packet are alternately transferred in the storage area 2 and the charged packet of an odd number line is saved and stored in a temporary save CCD 9. Similarly since the charged packets of an even number line with an idle packet in between are transferred similarly in the VCCD 8, after the charged packet of an odd number line read from the temporary save CCD 9 is moved to the position of the idle packet, the resulting charged packets are transferred to a horizontal transfer register (HCCD) 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and a method of driving the same, and more particularly to transferring a charge obtained by photoelectric conversion by a light receiving section on a semiconductor substrate to a horizontal transfer register via a vertical transfer register. Furthermore, the present invention relates to a solid-state imaging device that outputs an image signal from a horizontal transfer register via an amplifier, and a driving method for driving the vertical transfer register and the horizontal transfer register.

[0002]

2. Description of the Related Art In a solid-state imaging device using a charge-coupled device (CCD), a charge obtained by photoelectrically converting incident light at a light receiving portion on a semiconductor substrate is transferred to a horizontal transfer register via a vertical transfer register. It is output as an image signal from the horizontal transfer register via an amplifier. However, if the charge by photoelectric conversion is to be transferred in the same order (full frame transfer), four electrodes of the vertical transfer register are required for each photodiode constituting the light receiving section in the imaging region, and Both the photoelectric area and the transfer capacity of each of the vertical and horizontal transfer registers had to be sacrificed.

Therefore, conventionally, an interline transfer type solid-state image pickup device in which the number of electrodes of a vertical transfer register is two for each photodiode and charges of odd rows are transferred first and then charges of even rows are transferred is known. Better known.

FIG. 8 is a view for explaining the operation of an example of the conventional solid-state image pickup device. This solid-state imaging device is shown in FIGS.
As shown in (f), a photodiode (PD) 4 composed of m vertically and n horizontally arranged imaging regions 1 in a matrix, and m photodiodes PD arranged vertically in the PDs 4 are shown. A vertical transfer register (hereinafter, referred to as VCCD) 3 disposed between the PDCD 4 and a horizontal transfer register (hereinafter, referred to as HCCD) 5 which is connected to the VCCD 3 and transfers charges in a horizontal direction;
And an amplifier 6 for amplifying the output charge of the HCCD 5.

To explain the operation of this solid-state image pickup device, if it is assumed that charges are accumulated in all PDs 4 as shown in FIG. 8A, first, as shown in FIG. The charge accumulated in the PD4 in the odd row indicated by is VCCD
3 is read. Subsequently, as shown in FIG.
The read charge packet 15 converts the VCCD 3 to the HCCD.
5 and further transferred to the HCCD 5 where it is amplified by the amplifier 6 and output. As a result, as shown in FIG. 8D, the accumulated charges indicated by black circles remain only in the PDs 4 in the even-numbered rows.

[0008] Next, as shown in FIG. 8 (e), after the accumulated charges of the PD 4 in the even-numbered row are read out to the VCCD 3, as shown in FIG. The VCCD 3 is transferred to the HCCD 5, further transferred to the HCCD 5, amplified by the amplifier 6, and output.

According to the interline transfer type solid-state imaging device, since the stored charges in the odd rows and the stored charges in the even rows are alternately transferred and output, a television for displaying an image by an interlace method such as the NTSC system. It is suitable for displaying on a signal display device.

[0008]

However, the display of a display device for a television signal for displaying an image by the interlacing method has little flicker but lower resolution, so that a display device used for a computer or the like is not an interlaced display. There is a need for a non-interlaced system that draws all pixels at high speed without performing interlaced scanning.

Therefore, it is required that the charge obtained by the photoelectric conversion be transferred in the same order (full frame transfer) even in the solid-state imaging device. In order to satisfy this requirement, conventionally, an area for storing the odd-numbered charge packets and the even-numbered charge packets is formed on the HCCD 5 side of the imaging area 1, and after the output of the solid-state imaging device, the odd-numbered rows and the even-numbered rows are alternately arranged. Although the sorting is performed, there is a problem that an external memory is required and the processing system becomes complicated.

[0010] The present invention has been made in view of the above points,
It is an object of the present invention to provide a solid-state imaging device capable of reading out all pixels in the same order and a driving method thereof, even though each photodiode has two electrodes of a vertical transfer register.

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a photodiode arrayed on a plurality of matrices for converting incident light into electric charges, and a photodiode arrayed in a vertical direction among the plurality of photodiodes. An imaging region including a first vertical transfer register that is provided adjacent to each of the photodiodes and transfers charges read from the adjacent photodiode in the vertical direction, and a charge packet input from the first transfer register. A second vertical transfer register that transfers the packet in the vertical direction while sandwiching the packet; and a charge packet that is provided adjacent to the second vertical transfer register and that is transferred in advance of the charge packets transferred through the second vertical transfer register. A predetermined number of charge packets are temporarily evacuated and stored, and the second vertical packet is interposed between the subsequently read charge packets from the photodiode. An accumulation area including a temporary evacuation storage unit that reads and moves the accumulated charge packet to the position of the empty packet to be transferred to the transfer register, and a horizontal transfer that transfers the charge packet from the second vertical transfer register in the horizontal direction. And a register.

In the driving method according to the present invention, the second vertical transfer register is driven by the second transfer clock having a frequency twice as high as the first transfer clock of the first vertical transfer register in the imaging region in the storage region. In the accumulation region, when all the charge packets from the photodiodes of the odd-numbered rows or even-numbered rows input from the first vertical transfer register are transferred and input to the second vertical transfer register, they are temporarily saved. An accumulation signal for accumulating charge packets from the odd-numbered row or even-numbered row photodiodes is input to the storage unit, and all the charge packets from the even-numbered row or odd-numbered row photodiodes are transferred and input to the second vertical transfer register. When the return signal is input when the charge packet is read from the temporary save storage unit, the charge packet is moved to the second vertical transfer register and synthesized in time series. A.

[0013]

According to the present invention, a storage area is provided between the conventional image pickup area and the horizontal transfer register, and packets having accumulated charges and empty packets are alternately transferred in the storage area. A predetermined number of charge packets read from the photodiode are temporarily stored in the temporary save storage unit, and subsequently the charge packets read from the photodiode are transferred to the second vertical transfer register with an empty packet sandwiched therebetween. At this time, since the charge packet stored in the temporary storage unit is read and moved to the position of the empty packet, the preceding charge packet can be combined with the subsequent charge packet in time series.

Therefore, in particular, the charge packets from the photodiodes in the odd-numbered or even-numbered rows input from the first vertical transfer register are transferred to the second vertical transfer register with an empty packet interposed therebetween, and are stored in the temporary save storage unit. After accumulating the transfer charge packets, the charge packets from the photodiodes in the even-numbered rows or the odd-numbered rows are transferred to the second vertical transfer register with the empty packets interposed therebetween, and read out from the temporary save storage unit at the positions of the empty packets. By moving the charge packets and synthesizing them in chronological order, the charges from the photodiodes arranged in a plurality of matrices can be changed to odd rows without using a memory for rearranging the charges in odd rows and even rows. All even-numbered charge packets can be transferred alternately.

Further, in the driving method according to the present invention, the second vertical transfer register is driven by the second transfer clock having a frequency twice as high as the first transfer clock of the first vertical transfer register in the imaging region in the accumulation region. Since charges are transferred in such a manner, empty packets can be formed, and control can be performed such that charge packets of the odd-numbered and even-numbered photodiodes are alternately transferred to the horizontal transfer register without being mixed.

[0016]

Next, an embodiment of the present invention will be described. 1 to 3 show the configuration and operation of the embodiment of the present invention. As shown in FIGS. 1 to 3, this embodiment includes an imaging area 1, an accumulation area 2, a horizontal transfer register (HCCD) 5, and an amplifier 6. The imaging area 1 has the same configuration as that of the related art, and includes m (n) vertical photodiodes (n) and n (n) horizontal photodiodes arranged in a matrix, and m PDs 4 arranged in the vertical direction among the PDs 4. And a vertical transfer register (VCCD) 3 arranged between the two.

The storage area 2 is a characteristic area of the present embodiment.
A structure including a vertical transfer register (VCCD) 8 for transferring the charge from D3 in the vertical direction and inputting the charge to the HCCD 5; and a temporary save area (temporary save CCD) 9 for temporarily saving and storing the transfer charge of the VCCD 8. Have been.

Next, the operation of this embodiment will be described with reference to FIGS. FIG. 1A shows a state in which accumulated charges 7 exist in all PDs 4. In this state, first, FIG.
As shown in (b), the PDs 4 in the odd rows of the imaging region 1
The accumulated charges 7 schematically shown by white circles are transferred to the VCCD 3, and then the VCCD 3 is transferred in the vertical direction to the VCCD 3.
The charge packets 10 in the odd rows are input to the VCCD while the empty packets 11 are interposed therebetween, as shown in FIG.
8 are transferred vertically.

Subsequently, as shown in FIG. 2D, the charge packets 10 are moved to the temporary save CCD 9 as shown in FIG. 2D from the state in which all of the odd-numbered charge packets 10 have been transferred to the VCCD 8, and as shown in FIG. Stored as shown. Next, the accumulated charges 7 of the PDs 4 in the even-numbered rows of the imaging region 1 which are schematically shown by black circles are transferred to the VCCD 3, and then the VCCDs 3 are transferred in the vertical direction and input to the VCCD 8, and furthermore, FIG.
As shown in (f), the even numbered rows of charge packets 12 are vertically transferred through the VCCD 8 while sandwiching the empty packet 13.

Subsequently, as shown in FIG. 3 (g), the even-numbered charge packets 10 stored in the temporary save CCD 9 are read out from the state in which all of the even-numbered charge packets 12 have been transferred to the VCCD 8. Then, it is moved to the position of the empty packet 13 of the VCCD 8. This allows the VCCD8
, The odd-numbered charge packets 10 and the even-numbered charge packets 12 are alternately synthesized in time series.

Next, as shown in FIG. 3 (h), the VCCD 8
And the first odd-numbered charge packet 1
When 0 is input to the HCCD 5, it is transferred in the horizontal direction. Subsequently, as shown in FIG. 3I, after the next even-numbered charge packet 12 is input to the HCCD 5, it is transferred in the horizontal direction. Hereinafter, the same operation as described above is repeated, and the accumulated charges of all the pixels are output from the amplifier 6 as an image pickup signal synthesized in time series in the same order.

FIG. 4 shows a plan view and a sectional view of a main part of an embodiment of the present invention. In the figure, the same components as those in FIGS. 1 to 3 are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 4, regions 31 and 3 of regions 31 to 34 of VCCD 3 are shown.
3 are transfer clocks φI1 and φI for the first layer electrode 21.
Driven by I3, regions 32 and 34 are second layer electrodes 2
It is driven by transfer clocks φI2 and φI4 for 2.

The areas 35 and 36 of the VCCD 3 are connected to a connection signal φT for the first layer electrode 21 and the second layer electrode 22.
1 and φT2. Further, among the areas 37 to 51 of the VCCD 8 and other four areas (for example, 37, 38, 39, 40, or 41, 42, 43,
44) is the transfer clock φ for the electrode 21 or 22.
It is driven by S3, φS4, φS1 and φS2. Further, areas 41 and 42 and 4 adjacent to the primary retract CCD 9
Third layer electrodes 23 are provided at positions corresponding to 9 and 50, for example. This third layer electrode 23 is connected to a transfer clock φ.
T3 is applied.

Next, the driving method of this embodiment will be described with reference to FIGS. In FIG. 4, the odd-numbered rows of PD4
The charge is read out from the second layer electrode 22 to which the clock φI4 is applied by setting the level of the clock φI4 higher than that during normal transfer. Further, the charge reading from the PDs 4 on even-numbered rows is performed by making the level of the clock φI2 higher than that at the normal transfer in the second layer electrode 22 to which the clock φI2 is applied.

Next, the operation of the VCCDs 3 and 8 shown in FIGS. 1B and 1C or FIGS. 2E and 2F at the time of charge transfer will be described with reference to FIGS. Figure 5
(A), (b) and (c) show the transfer clock φI1
.Phi.I2, the connection signals .phi.T1 and .phi.T2, and the four-phase double-speed transfer clocks .phi.S1 to .phi.S4 of the storage area 2 are represented by the time axis in FIG. Further, FIG. 5E shows the charge transfer position on the time axis of FIG. 5D, and the numbers on the vertical axis show the regions of FIG. Here, T0 in FIG. 5D indicates the cycle of the transfer clocks φI1 to φI4 for four-phase driving of the imaging region 1.

As shown in FIGS. 5D and 5E, FIG.
Regions 31 and 32, 35 and 36, 43 and 4 shown in FIG.
Assuming that a charge packet exists in T = 0 at T = 0, after 1/8 T0, the charge packets in the regions 31 and 32 are transferred to the regions 32 and 33, and the charge packets in the regions 35 and 36 are transferred to the regions 36 and 37, the charge packets in regions 43 and 44 are transferred to regions 44 and 45. At this time, empty packets in the areas 39 and 40 and the areas 47 and 48 are transferred to the areas 40 and 41 and the areas 48 and 49.

In the same manner as described above, each time 1 / 8T0 elapses, based on the signals shown in FIGS.
As shown in FIG. 5E, the charge packet and the empty packet are transferred.

Next, the primary retraction CCD shown in FIG.
9 will be described with reference to FIGS. 4 and 6. FIG. FIG. 6A shows the signal φT3 applied to the third electrode 23, FIG. 6B shows the four-phase double-speed transfer clocks φS1 to φS4 of the storage region 2, and the time axis of FIG. Expressed by FIG. 6D shows the charge transfer position on the time axis of FIG.

As shown in FIGS. 6 (c) and 6 (d), FIG.
It is assumed that charge packets exist in the regions 39 and 40, 47 and 48 shown in FIG. 4 when T = 0, respectively, and the charge packets in the regions 39 and 40 are the last charge packets in the odd rows. Immediately thereafter, as shown in FIG. 6 (a), the level of the signal φT3 applied to the third electrode 23 is made higher than that at the time of accumulation, and the transfer clock having a cycle half the cycle T0 of the transfer clocks φI1 to φI4. When φS4 falls, the voltage at the time of accumulation is applied.

Thus, immediately after １ ／ T0, the charge packets in the regions 39 and 40 are transferred to the regions 40 and 41 and the charge packets in the regions 47 and 48 are transferred to the regions 40 and 41, as shown in FIG. Are transferred to the evacuation CCD 9 and then stored. At this time, the empty packets in the areas 44 and 45 remain unmoved.

Next, the temporary retract CCD shown in FIG.
The operation for reading out the charges stored in the memory 9 will be described with reference to FIGS. 7A shows the signal φT3 applied to the third electrode 23, and FIG. 7B shows the four-phase double speed transfer clocks φS1 to φS4 of the storage region 2, respectively, on the time axis of FIG. 7C. It is represented by. FIG. 7D shows the charge transfer position on the time axis of FIG.

As shown in FIGS. 7C and 7D, FIG.
In the areas 43 and 44 shown in FIG. 3, the charge packet P3 of the even-numbered row immediately before the end of the odd-numbered row exists when T = 0, and 1 /
Assume that the last charge packet P4 of the odd-numbered row has entered the area 37 shown in FIG. 4 after 8T0.

Then, immediately after that, as shown in FIG. 7 (a), the level of the signal φT3 applied to the third electrode 23 is reduced, and as shown in FIG. 7 (b), the transfer clock φI1 A transfer clock φS4 having a period half the period T0 of φI4 is a signal (return signal) larger than that during normal transfer.

As a result, as shown in FIG. 7D, charges P1 and P2 are read out from the temporary save CCD 9 and transferred to the areas 49 and 50 and the areas 41 and 42, respectively, immediately after that. Here, the charge P1 is the charge packet immediately before the end of the odd row, and the charge P2 is the last charge packet of the odd row. With this operation, all the charges in the odd rows return to the VCCD 8 and are combined with the charges in the even rows in a time-series manner.

As described above, according to the present embodiment, with two electrodes of the VCCD 3 per photodiode, the charges of the photodiodes in the odd rows are read out, transferred to the VCCD 3 and input to the storage region 2. Then, the cycle of the transfer clocks φS1 to φS4 of the VCCD 8 in the accumulation area 2 is set to half (the driving frequency is doubled) the cycle T0 of the transfer clocks φI1 to φI4 of the VCCD 3 in the imaging area 1. Then, the odd-numbered charge packets and the empty packets are alternately transferred, and the odd-numbered charge packets are temporarily saved and stored in the evacuation CCD 9. After that, in the same manner as described above, the even-numbered row charge packets transferred from the imaging region 1 to the VCCD 8 are transferred across the empty packet in the VCCD 8, and the temporary save CCD is placed at the position of the empty packet.
By moving the charges in the odd rows read from 9, the charge packets are combined in time series. After that, these are HCD
Since D5 is transferred, full frame transfer can be performed with a simple configuration.

The present invention is not limited to the above-described embodiments. For example, first, all the charges of the photodiodes in the even rows are transferred and temporarily stored in the CCD 9, and then the photodiodes in the odd rows are stored. Transfer the electric charge of V
In the CCD 8, the charge packet read from the temporary save CCD 9 may be moved to the position of the empty packet between the charge packets in the odd rows.

[0037]

As described above, according to the present invention,
Mixing the charge packets of the photodiodes in the odd and even rows without using a memory for rearranging the charges from the plurality of photodiodes arranged in a matrix in the imaging area into the odd and even rows Without
Since control can be performed such that all data are alternately transferred to the horizontal transfer register, full-frame transfer required for high-resolution images can be performed with simpler control than in the related art.

[Brief description of drawings]

FIG. 1 is an operation explanatory diagram of one embodiment of the present invention (part 1).

FIG. 2 is an operation explanatory diagram of one embodiment of the present invention (part 2).

FIG. 3 is a diagram for explaining the operation of the embodiment of the present invention (No. 3).

FIG. 4 is a plan view and a sectional view of a main part of an embodiment of the present invention.

FIG. 5 is a diagram for explaining the operation of FIG. 4 (No. 1).

FIG. 6 is an operation explanatory diagram of FIG. 4 (part 2).

FIG. 7 is an operation explanatory diagram of FIG. 4 (part 3).

FIG. 8 is a diagram illustrating an operation of an example of the related art.

[Explanation of symbols]

 Reference Signs List 1 imaging area 2 accumulation area 3 first vertical transfer register (VCCD) 4 photodiode (PD) 5 horizontal transfer register (HCCD) 6 amplifier 7 accumulated charge 8 second vertical transfer register (VCCD) 9 temporary save CCD 10, 12 Charge packet 11, 13 Empty packet 21 First layer electrode 22 Second layer electrode 23 Third layer electrode

Claims (3)

[Claims] 1. A photodiode arrayed on a plurality of matrices for converting incident light into an electric charge, and a photodiode arrayed adjacent to a photodiode arrayed vertically in the plurality of photodiodes. An imaging region including a first vertical transfer register for vertically transferring the charges read from the diode, and a second for vertically transferring the charge packet input from the first transfer register while sandwiching an empty packet. A vertical transfer register and a second vertical transfer register are provided adjacent to the second vertical transfer register, and temporarily store and store a predetermined number of charge packets that are transferred in advance of the charge packets transferred through the second vertical transfer register. , An empty packet transferred through the second vertical transfer register while sandwiching a charge packet from the photodiode that is read out subsequently. A storage area including a temporary save storage unit that reads and moves the stored charge packet to a position, and a horizontal transfer register that horizontally transfers the charge packet from the second vertical transfer register. Solid-state image sensor. 2. In the imaging region, after moving the charges from the photodiodes arranged in one of the even-numbered row and the odd-numbered row of the plurality of photodiodes to the first vertical transfer register, The charges are transferred in the vertical direction, and then the charges from the photodiodes arranged in the other row are transferred to the first vertical transfer register and then transferred in the vertical direction. The charge packet from the photodiode of the one row input from the transfer register is transferred to the second vertical transfer register with an empty packet interposed, and the charge from the photodiode of the one row is stored in the temporary save storage unit. After accumulating the packets, the charge packets from the photodiodes in the other row are transferred to the second vertical transfer register with an empty packet sandwiched between them. Solid-state imaging device according to claim 1, wherein the time series synthesized moving the charge packets said read from temporary saving memory unit in the position of the air packet. 3. In the storage area, the second vertical transfer register is driven by a second transfer clock having a frequency twice that of the first transfer clock of the first vertical transfer register in the imaging area to charge the second vertical transfer register. In the storage region, when all the charge packets from the photodiodes in the odd-numbered rows or even-numbered rows input from the first vertical transfer register are transferred and input to the second vertical transfer register, An accumulation signal for accumulating charge packets from the photodiodes of the odd-numbered rows or even-numbered rows is input to the save storage unit,
When all the charge packets from the photodiodes of the even-numbered or odd-numbered rows are transferred to the second vertical transfer register, a return signal is input to transfer the charge packets read from the temporary save storage unit to the second vertical transfer register. 2. The method for driving a solid-state imaging device according to claim 1, wherein the data is moved to a register and synthesized in chronological order.