JP4078741B2 - Solid-state imaging device, driving method thereof, and camera system - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state imaging device, a driving method thereof, and a camera system, and more particularly to a solid-state imaging device capable of obtaining both a still image and a moving image, a driving method thereof, and a camera system using the solid-state imaging device as an imaging device. .
[0002]
[Prior art]
In a still image imaging technique represented by a still camera, a solid-state imaging device such as an IT (interline transfer) type CCD (Charge Coupled Device) imager is used as an imaging device, and a mechanical shutter (hereinafter abbreviated as a mechanical shutter). There is known a method of forming a still image by performing frame readout by using and combining pixel information for two fields in a signal processing system. In order to increase the resolution, a CCD imager having a larger number of pixels is used.
[0003]
On the other hand, when monitoring a subject, a monitoring mode (moving image mode) for displaying a moving image on a monitor is set. However, in the output part of the CCD imager, since there is a constraint between the cutoff frequency of the source follower constituting the output part and the CCD drive frequency, the output part cannot be made very fast, so the CCD imager has a large number of pixels. As the number of pixels increases, the frame rate in the monitoring mode decreases.
[0004]
By the way, in auto focus and auto iris, a frame rate of 30 frames / second is required. On the other hand, for example, in a 2 million pixel CCD imager, the frame rate is about 5 frames / second. For this reason, in a camera system using a CCD imager with 2 million pixels, when the monitoring mode is set, a frame rate of 30 frames / second is realized by performing so-called thinning-out reading driving that reads out pixel information by thinning out. I have to.
[0005]
[Problems to be solved by the invention]
However, as described above, in the conventional technique in which frame readout driving is performed in the all-pixel mode (still image mode) for obtaining a still image while thinning readout driving is performed in the monitoring mode, signal charge is read and transferred. Because the driving for the difference between the all-pixel mode and the monitoring mode, there is a problem that the configuration of the driving system including the clock becomes complicated.
[0006]
In the monitoring mode, since the exposure time is shorter than that in the all-pixel mode, the sensitivity is lowered accordingly. The decrease in sensitivity due to the shortening of the exposure time can be suppressed by adding the signal charges of adjacent pixels. However, in the color CCD imager, in the case of color coding in which adjacent colors are different as in the Bayer array, signals of adjacent pixels cannot be added to each other. Therefore, the sensitivity associated with shortening the exposure time in the monitoring mode. However, there is a problem that the sensitivity in the monitoring mode is lower than the sensitivity in the all-pixel mode.
[0007]
The present invention has been made in view of the above problems, and an object of the present invention is to provide a solid-state imaging device capable of sharing a driving system in all pixel mode and monitoring mode, a driving method thereof, and imaging the solid-state imaging device. It is to provide a camera system used as a device.
[0008]
[Means for Solving the Problems]
A solid-state imaging device according to the present invention includes a color coding color filter in which the same color is repeatedly arranged every n pixels (n is an integer of 2 or more) in a row direction with respect to pixels arranged in a matrix, and (n + 1) ): 1 interlaced, 1 frame is composed of (n + 1) fields, and a drive system that performs vertical transfer of signal charges with a clock of (n + 1) × m phase (m is a natural number). Yes.
[0009]
The solid-state imaging device driving method according to the present invention includes a color coding color filter in which the same color is repeatedly arranged in every n pixels in the row direction with respect to pixels arranged in a matrix. n + 1): 1 interlace is performed to form one frame with (n + 1) fields, and signal charges are vertically transferred by a clock of (n + 1) × m phases.
[0010]
The camera system according to the present invention uses the solid-state imaging device having the above configuration as an imaging device, and includes a mode setting unit that selectively sets the all-pixel mode and the monitoring mode. The timing controller controls the timing of the solid-state imaging device and the opening / closing control of the mechanical shutter according to the imaging mode set by the mode setting unit, while the image based on the signal processed by the signal processing circuit when the all-pixel mode is set. Information is recorded on the recording medium as still image information, and a moving image based on the signal processed by the signal processing circuit is displayed on the monitor when the monitoring mode is set.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram showing, for example, an IT type color CCD imager according to a first embodiment of the present invention.
[0012]
In FIG. 1, a large number of sensor units (pixels) 11 that convert incident light into signal charges having a charge amount corresponding to the amount of light and store the same are arranged in a two-dimensional matrix in the vertical (row) direction and horizontal (column) direction. Has been. Further, a plurality of vertical CCDs 12 are provided for each vertical row of the sensor units 11, and a read gate unit 13 is interposed between the vertical CCDs 12 and the sensor units 11.
[0013]
The signal charges accumulated in the plurality of sensor units 11 are read out to the vertical CCD 12 by applying a read pulse XSG described later to the read gate unit 13 and increasing the potential of the read gate unit 13. The vertical CCD 12 is driven to transfer by, for example, six-phase vertical transfer clocks Vφ1 to Vφ6, and sequentially transfers the read signal charges. One sensor unit 11, a transfer stage of the vertical CCD 12 corresponding to the sensor unit 11, and a read gate unit 13 constitute a unit cell 14.
[0014]
In the six-phase drive vertical CCD 12, for example, the transfer electrodes to which the second-phase, fourth-phase and sixth-phase vertical transfer clocks Vφ 2, Vφ 4 and Vφ 6 are applied also serve as the gate electrode of the read gate unit 13. It has become. Therefore, among the six-phase vertical transfer clocks Vφ1 to Vφ6, the vertical transfer clocks Vφ2, Vφ4, Vφ6 are low level (hereinafter referred to as “L” level), intermediate level and high level (hereinafter referred to as “H” level). The third value “H” level pulse is the read pulse XSG applied to the read gate section 13.
[0015]
FIG. 2 is a plan pattern diagram showing a specific structure of the unit cell 14. In FIG. 2, transfer electrodes 22-1 to 22-6 to which 6-phase vertical transfer clocks Vφ1 to Vφ6 are respectively applied are overlapped on the side of the sensor unit 11 above the transfer channel 21 of the vertical CCD 12. These are arranged repeatedly in order in the vertical transfer direction. Of these transfer electrodes 22-1 to 22-6, transfer electrodes 22-1, 22-3 and 22-5 to which vertical transfer clocks Vφ1, Vφ3 and Vφ5 are applied are the first layer polysilicon (one point The transfer electrodes 22-2, 22-4, and 22-6 that are formed by the vertical transfer clocks Vφ2, Vφ4, and Vφ6 are formed of the second layer polysilicon (shown by the two-dot chain line in the figure). Is formed.
[0016]
In FIG. 1 again, the horizontal CCD 15 extends in the left-right direction in the drawing adjacent to the respective transfer destination side ends of the plurality of vertical CCDs 12. Signal charges corresponding to one line (one scanning line) are sequentially transferred from the plurality of vertical CCDs 12 to the horizontal CCD 15. The horizontal CCD 15 is driven to transfer by, for example, two-phase horizontal transfer clocks Hφ 1 and Hφ 2, and sequentially transfers signal charges for one line shifted in line from the plurality of vertical CCDs 12.
[0017]
At the end of the horizontal CCD 15 on the transfer destination side, for example, a charge detection unit 16 having a floating diffusion amplifier configuration is arranged. The charge detection unit 16 includes a floating diffusion FD, a reset drain RD, and a reset gate RG positioned between the two. The charge detection unit 16 converts the signal charges transferred horizontally by the horizontal CCD 15 and injected into the floating diffusion FD into signal voltages. Output.
[0018]
Various timing pulses such as the six-phase vertical transfer clocks Vφ1 to Vφ6 including the read pulse XSG for transferring and driving the vertical CCD 12 and the two-phase horizontal transfer clocks Hφ1 and Hφ2 for transferring and driving the horizontal CCD 15 are generated by a timing generator (TG). 17 is generated. The timing generator 17 constitutes a drive system for a CCD imager together with a driver (not shown) and the like, and supplies various generated timing pulses to the vertical CCD 12 and the horizontal CCD 15 through the driver.
[0019]
Thus, the IT-type CCD imager 10 is configured. The CCD imager 10 has a large number of pixels in order to obtain a high-resolution still image. Furthermore, since it is a color imaging system, the same color is vertically (row) as shown in FIG. 3, for example, above the imaging area 18 in which a large number of sensor units 11 are arranged in a two-dimensional matrix. In addition, the so-called 2 × 2 repeating primary color Bayer array color filter 19 arranged repeatedly every two pixels in the horizontal (column) direction is assigned one color to one sensor unit (pixel) 11. For example, it is formed on-chip.
[0020]
FIG. 4 is a schematic configuration diagram showing a camera system according to the present invention using the color CCD imager 10 having the above configuration as an imaging device.
[0021]
In FIG. 4, the camera system includes a color CCD imager 10 that is an imaging device, a lens 23 that captures incident light (image light) from a subject on the imaging surface of the CCD imager 10, and captures the image light. A mechanical shutter 24 for selectively performing the processing, a signal processing circuit 25 for processing an output signal of the CCD imager 10, an image recording device 26 for recording the output signal of the signal processing circuit 25 on a recording medium, and an output signal of the signal processing circuit 25. The image display device 27 displayed on the monitor, a timing controller 28 for controlling the timing of the entire system, and a mode setting unit 29 for setting the imaging mode of the CCD imager 10 are provided.
[0022]
In the camera system configured as described above, incident light (image light) from the subject is imaged on the imaging surface of the CCD imager 10 through the lens 23, the mechanical shutter 24, and the like. The CCD imager 10 is appropriately set by the mode setting unit 29 as an imaging mode, an all-pixel mode for independently obtaining signals of all pixels and a monitoring mode for displaying a moving image on a monitor.
[0023]
The timing controller 28 performs timing control of the timing generator 17 (see FIG. 1) for driving the CCD imager 10 and opening / closing control of the mechanical shutter 24 according to the imaging mode set by the mode setting unit 29. The timing generator 17 composes one frame with three fields by performing 3: 1 interlace for the vertical two-repetition color coding.
[0024]
Therefore, 6-phase (= 3 fields × 2) vertical transfer clocks Vφ1 to Vφ6 are generated, and the vertical CCD 12 is driven in 6 phases. However, it is not limited to 6-phase driving, and 3-phase (= 3 fields × 1) driving or 9-phase (= 3 fields × 3) driving may be used. The case of three-phase driving will be described later in detail.
[0025]
In this example, color coding of the color filter 19 is repeated twice in the vertical direction, and 3: 1 interlace is performed on this, so that one frame is composed of 3 (= 2 + 1) fields and the transfer drive of the vertical CCD 12 is performed. Is performed with a 3 × m (m is a natural number) phase clock. In short, one frame is obtained by performing (n + 1): 1 interlace for vertical n repetitions (n is an integer of 2 or more). Any configuration may be used as long as it is configured with (n + 1) fields and the transfer drive of the vertical CCD 12 is performed with a clock of (n + 1) × m phases.
[0026]
For example, as shown in FIG. 5, the signal processing circuit 25 includes three field memories 31 to 33 and three pieces of pixel information output from the CCD imager 10 and digitized by the A / D converter 34 in units of fields. Are supplied from each of the field memories 31 to 33 through the selection switch 36 and a selector switch 36 for selectively extracting the pixel information stored in the field memories 31 to 33. The color signal processing circuit 37 performs processing for generating two color difference signals Cr and Cb based on the R (red), G (green), and B (blue) color signals.
[0027]
In the signal processing circuit 25, switching control of the selector switch 35 and the selection switch 36 is also performed by the timing controller 28 according to the imaging mode set by the mode setting unit 29.
[0028]
The image recording device 26 records the image signal processed by the signal processing circuit 25 on a recording medium such as a memory or a floppy disk when the all-pixel mode is set by the mode setting unit 29. The image information recorded on the recording medium is hard copied by a printer or the like. When the mode setting unit 29 sets the monitoring mode, the image display device 27 displays the image signal processed by the signal processing circuit 25 on a monitor such as a CRT (cathode ray tube) or LCD (liquid crystal) as a moving image.
[0029]
The number of vertical scanning lines of the monitor used in the monitoring mode is set to 1/3 of the number of rows (number of vertical scanning lines) of the CCD imager 10 corresponding to 3: 1 interlace. Yes.
[0030]
Next, in the camera system having the above configuration, each operation when the all pixel mode is set by the mode setting unit 29 and when the monitoring mode is set will be described. In the timing chart of the vertical transfer clocks Vφ1 to Vφ6 used in the following description of each operation, the timing relationship of each clock is omitted for simplicity of explanation, and only the timing relationship of the read pulse XSG is shown. .
[0031]
[All pixel mode]
First, the operation when the all-pixel mode is set will be described with reference to the timing chart of FIG. 6. The mechanical shutter 24 is exposed for a predetermined time with the mechanical shutter 24 opened, and then the mechanical shutter 24 is closed at time t0. At time t1, the read pulse XSG is set only for the vertical transfer clock Vφ2 of the second phase. Then, in the pixel array of FIG. 7, for example, the signal charges (1), (4), (7),... Of the pixels in the first row, the fourth row, the seventh row,. Read to the vertical CCD 12.
[0032]
These pixel information {circle over (1)}, {circle over (4)}, {7},... Are vertically transferred by the vertical CCD 12 and further horizontally transferred by the horizontal CCD 15 as the pixel information of the first field, and then are signaled by the charge detector 16. It is converted into a voltage and supplied to the signal processing circuit 25. In the signal processing circuit 25, the pixel information of the first field is supplied to the field memory 31 through the changeover switch 35 and is sequentially stored in the memory 31.
[0033]
Next, at time t2, the read pulse XSG is raised only for the fourth-phase vertical transfer clock Vφ4. Then, in the pixel array of FIG. 7, the signal charges (2), (5), (8),... Of the pixels in the second row, the fifth row, the eighth row,. Read out. These pixel information (2), (5), (8),... Are vertically and horizontally transferred as pixel information of the second field, converted to a signal voltage, and supplied to the signal processing circuit 25. The data are sequentially stored in the field memory 32 through the changeover switch 35.
[0034]
Subsequently, at time t3, the read pulse XSG is raised only for the vertical transfer clock Vφ6 of the sixth phase. Then, in the pixel array of FIG. 7, the signal charges (3), (6), (9),... Of the pixels in the third row, the sixth row, the ninth row,. Read out. These pieces of pixel information are {3}, {6}, {9},..., And are transferred to the signal processing circuit 25 after being vertically and horizontally transferred, converted into signal voltages, The data are sequentially stored in the field memory 33 through the changeover switch 35.
[0035]
After the pixel information for three fields is stored in the field memories 31, 32, and 33, these are read out. In this reading, first, the pixel information (1) of the first row of the field memory 31 is sequentially read, and then the pixel information (2) of the first row of the field memory 32 is sequentially read, Subsequently, the pixel information {circle over (3)} in the first row of the field memory 33 is sequentially read out, then the pixel information {circle over (4)} in the second row of the field memory 31 is read out sequentially, and so on. Switching control of the selection switch 36 is performed so as to sequentially read from the field memories 31, 32, and 33 line by line.
[0036]
With the series of controls described above, one frame (one screen) is configured by three fields, and the read pixel information corresponds to the pixel arrangement in FIG. Thereby, the pixel information of all the pixels of the CCD imager 10 can be obtained independently. The pixel information of all the pixels is subjected to predetermined color signal processing by the color signal processing circuit 37, supplied to the image recording device 26, recorded on a recording medium such as a memory, and then hard-copied by a printer or the like. Is done.
[0037]
In this all-pixel mode, in each field, vertical thinning readout is performed in which two pixels are thinned out every three vertical pixels. After the pixel information of each field is stored in the field memories 31, 32, and 33, these are read out. By sequentially reading from the memories 31, 32, and 33 line by line, a line-sequential still image can be formed using the pixel information of all pixels of the CCD imager 10. As a result, a high-resolution still image can be obtained.
[0038]
[First example of monitoring mode]
Next, the operation of the first specific example when the monitoring mode is set will be described based on the timing chart of FIG. In the monitoring mode, since a moving image is obtained, the mechanical shutter 24 is continuously open. In this state, the first specific example employs a configuration in which only the pixel information of the first field is repeatedly read out three times (for three fields).
[0039]
That is, the read pulse XSG is raised only at the second phase vertical transfer clock Vφ2 at time t1. Then, in the pixel array of FIG. 7, for example, the signal charges (1), (4), (7),... Of the pixels in the first row, the fourth row, the seventh row,. Read to the vertical CCD 12. These pixel information (1), (4), (7),... Are vertically transferred and horizontally transferred as pixel information of the first field, converted to a signal voltage, and supplied to the signal processing circuit 25. And sequentially stored in the field memory 31 through the changeover switch 35.
[0040]
The pixel information of the first field stored in the field memory 31, that is, the pixel information (1), (4) of the first row, fourth row, seventh row,... , {Circle over (7)},... Are sequentially read out through the selection switch 36 in the order of storage, subjected to predetermined color signal processing by the color signal processing circuit 37, and then supplied to the image display device 27 for vertical scanning. It is projected on a monitor with 1/3 lines.
[0041]
Next, at time t2, the read pulse XSG is set again only for the vertical transfer clock Vφ2 of the second phase. Then, as in the previous case, the pixel information of the first field, that is, the signal charges (1), (4), (7) of the pixels of the first row, the fourth row, the seventh row,. Are read out and sequentially stored in the field memory 31. Then, the pixel information (1), (4), (7),... In the first field are sequentially read out through the selection switch 36 in the storing order, and predetermined color signal processing is performed by the color signal processing circuit 37. Then, it is supplied to the image display device 27 and displayed on the monitor.
[0042]
Subsequently, at time t3, the read pulse XSG is set again only for the vertical transfer clock Vφ2 of the second phase. Then, the signal charges (1), (4), (7),... Of the pixels in the first row, the fourth row, the seventh row,. Are sequentially stored in the field memory 31. Then, the pixel information (1), (4), (7),... In the first field are sequentially read out through the selection switch 36 in the storing order, and predetermined color signal processing is performed by the color signal processing circuit 37. Then, it is supplied to the image display device 27 and displayed on the monitor.
[0043]
Through the above-described series of controls, vertical thinning-out reading is performed by thinning out two pixels into three vertical pixels by repeatedly reading out only the first field, so that the frame rate is three times that of the case where vertical thinning-out reading is not performed. it can. In particular, since driving for reading and transferring signal charges in each field is the same as in the all-pixel mode, there is no need to change the clock timing or the like according to the imaging mode.
[0044]
In the first specific example, only the pixel information (1), (4), (7),... Of the first field is repeatedly read, but the pixel information (2), (5) of the second field is read. Of course, it is possible to repeatedly read out only the pixel information (3), (6), (9),...
[0045]
[Second specific example of monitoring mode]
Next, the operation of the second specific example when the monitoring mode is set will be described based on the timing chart of FIG. In the state where the mechanical shutter 24 is continuously opened, the second specific example employs a configuration in which the pixel information of the first, second, and third fields is sequentially read out, as in the case of the all pixel mode.
[0046]
That is, the read pulse XSG is raised at the second phase vertical transfer clock Vφ2 at time t1. Then, in the pixel array of FIG. 7, for example, the signal charges (1), (4), (7),... Of the pixels in the first row, the fourth row, the seventh row,. Read to the vertical CCD 12. These pixel information (1), (4), (7),... Are vertically transferred and horizontally transferred as pixel information of the first field, converted to a signal voltage, and supplied to the signal processing circuit 25. And sequentially stored in the field memory 31 through the changeover switch 35.
[0047]
The pixel information of the first field stored in the field memory 31, that is, the pixel information (1), (4) of the first row, fourth row, seventh row,... , (7),... Are sequentially read out through the selection switch 36 in the order of storage, and after a predetermined color signal processing is performed by the color signal processing circuit 37, they are supplied to the image display device 27 and displayed on the monitor. .
[0048]
Next, at time t2, a read pulse XSG is set on the fourth-phase vertical transfer clock Vφ4. Then, in the pixel array of FIG. 7, the signal charges (2), (5), (8),... Of the pixels in the second row, the fifth row, the eighth row,. Read out. These pixel information (2), (5), (8),... Are sequentially stored in the field memory 32 as the pixel information of the second field.
[0049]
The pixel information of the second field stored in the field memory 32, that is, the pixel information of the second row, the fifth row, the eighth row,... In the pixel arrangement of FIG. , {Circle over (8)},... Are sequentially read out through the selection switch 36 in the order of storage, are subjected to predetermined color signal processing by the color signal processing circuit 37, and are then supplied to the image display device 27 for the first field. It is displayed on the monitor as in the case.
[0050]
Subsequently, at time t3, a read pulse XSG is set on the sixth-phase vertical transfer clock Vφ6. Then, in the pixel array of FIG. 7, the signal charges (3), (6), (9),... Of the pixels in the third row, the sixth row, the ninth row,. Read out. These pixel information (3), (6), (9),... Are sequentially stored in the field memory 33 as the pixel information of the third field.
[0051]
The pixel information of the third field stored in the field memory 33, that is, the pixel information (3), (6), (9),..., (3), (6) in the pixel array of FIG. , {Circle over (9)},... Are sequentially read out through the selection switch 36 in the order of storage, and after the predetermined color signal processing is performed by the color signal processing circuit 37, they are supplied to the image display device 27 and supplied to the first and first. It is displayed on the monitor as in the case of 2 fields.
[0052]
With the series of controls described above, one frame is composed of three fields of the first, second, and third fields. In each field, vertical thinning readout is performed in which two pixels are thinned out into three vertical pixels. As in the case, a frame rate three times that in the case where vertical thinning readout is not performed can be realized. In particular, since driving for reading and transferring signal charges in each field is the same as in the all-pixel mode, there is no need to change the clock timing or the like according to the imaging mode.
[0053]
Further, since the pixel information of the first, second, and third fields are sequentially read out, the signal in each pixel is compared with the case of the first specific example in which only the pixel information of the same field is repeatedly read out. Since the charge accumulation time (exposure time) is tripled, the sensitivity can be improved compared to the case of the first specific example, and in the monitoring mode, it is equivalent to the all pixel mode without adding the signal charges of adjacent pixels. Can be obtained.
[0054]
As described above, in the camera system using the CCD imager 10 having the color filter 19 of the primary color Bayer array of two vertical repetitions as an imaging device, 3: 1 interlace is performed to form one frame by three fields. The vertical transfer clocks Vφ1 to Vφ6 of the phases perform the vertical transfer of signal charges, so that the timing of the clocks in the drive system does not have to be changed in all pixel modes and the monitoring mode, thereby simplifying the configuration of the drive system it can.
[0055]
In addition, not only in the all pixel mode but also in the monitoring mode, each field can obtain the pixel information of the Bayer array, so that a high-quality moving image can be displayed and the signal processing system can be shared. The configuration of the signal processing system can be simplified.
[0056]
Further, since the vertical CCD 12 is driven in six phases, the amount of charge handled by the vertical CCD 12 is increased, so that the dynamic range can be increased. That is, taking the case of reading signal charges in the first field as an example, in the first field, the six-phase vertical transfer clocks Vφ1 to Vφ6 have the timing relationship shown in FIG. That is, four consecutive clocks among the six-phase vertical transfer clocks Vφ1 to Vφ6 are always in the “H” level state.
[0057]
For example, immediately after the read pulse XSG is set on the vertical transfer clock Vφ2 of the second phase, that is, immediately after the signal charge is read out, the vertical transfer clocks Vφ1 and Vφ6 of the first phase and the sixth phase are at the “L” level. “H” level. Therefore, as shown in the potential diagram of FIG. 11, signal charges are stored in the packets P for four consecutive transfer stages corresponding to the vertical transfer clocks Vφ2 to Vφ5, so that the amount of charge handled by the vertical CCD 12 can be increased. It is.
[0058]
When this is set to the normal mode in the all-pixel mode and the monitoring mode, smear components generated when light is directly mixed into the vertical CCD 12 or charges generated inside the semiconductor substrate are spread by diffusion and mixed into the vertical CCD 12. It is also possible to realize a low smear mode that reduces the above. The operation in the low smear mode will be described below.
[0059]
In order to realize the low smear mode, first, in the CCD imager shown in FIG. 12, the transfer stage of the horizontal CCD 15 'is doubled with respect to the number of horizontal pixels, and the six-phase vertical transfer clocks V.phi. Let Vφ6 be the timing relationship shown in FIG. That is, the six transfer stages corresponding to the six-phase vertical transfer clocks Vφ1 to Vφ6 are always separated into two packets by a transfer stage having a shallow potential.
[0060]
For example, in the period T0 immediately after the read pulse XSG is raised in the second-phase vertical transfer clock Vφ2, the first-phase and fourth-phase vertical transfer pulses Vφ1 and Vφ4 are at the “L” level, and the others are at the “H” level. It is in. Therefore, as shown in the potential diagram of FIG. 14, the packet P1 for two transfer stages corresponding to the second-phase and third-phase vertical transfer clocks Vφ2 and Vφ3, and the fifth-phase and sixth-phase vertical transfer clocks Vφ5. , Vφ6 is separated from the packet P2 for two transfer stages by a transfer stage having a shallow potential corresponding to the vertical transfer pulse Vφ4 of the fourth phase.
[0061]
In principle, it can be considered that the same amount of smear component is generated in these two packets P1 and P2. The signal charge is read from the pixel to the packet P1 by setting the read pulse XSG at the vertical transfer clock Vφ2 of the second phase. Thereby, the charge of the signal component + smear component is accumulated in the packet P1, and the charge of only the smear component is accumulated in the packet P2. As a result, the charge of the signal component + smear component and the charge of only the smear component are alternately present on the vertical CCD 12 in the transfer direction.
[0062]
Then, due to the transfer operation of the vertical CCD 12, for example, the charge of only the smear component is line shifted to the horizontal CCD 15 'by one line. At this time, since the transfer stage of the horizontal CCD 15 'has a double density with respect to the number of horizontal pixels, the charge of only the smear component shifted from the vertical CCD 12 is one packet (one transfer stage) in the horizontal CCD 15'. It exists every other. After this line shift, the horizontal CCD 15 'is shifted by one bit (one packet).
[0063]
Thereafter, the charge for the next line, that is, the charge of the signal component + smear component is line-shifted from the vertical CCD 12 to the horizontal CCD 15 '. At this time, since the horizontal CCD 15 'has been shifted by 1 bit, the charge of the signal component + smear component is accumulated in an empty packet between packets in which only the charge of the smear component exists. As a result, only the smear component charge and the signal component + smear component charge exist alternately on the horizontal CCD 15 '.
[0064]
These charges are sequentially transferred horizontally by the horizontal CCD 15 ', converted into a signal voltage by the charge detector 16, and then supplied to the signal processing circuit 25 shown in FIG. In the case of this example, the signal processing circuit 25 has a 1-bit delay circuit 41 having a delay time equivalent to 1 bit and a subtractor 42 as shown in FIG. By performing a process of subtracting a signal based only on the smear component charge that has passed through the 1-bit delay circuit 41 from the signal based on this charge, the smear component can be canceled and a signal component without smear can be obtained.
[0065]
In this example, the transfer stage uses a horizontal CCD 15 'having a double density with respect to the number of horizontal pixels. However, as shown in FIG. 16, the transfer stage has two horizontal CCDs 15 having the same density as the number of horizontal pixels. The low smear mode can also be realized by adopting a configuration in which -1 and 15-2 are juxtaposed. That is, two horizontal CCDs 15-1 and 15-2 are juxtaposed, and an HH gate 43 for appropriately transferring signal charges from the horizontal CCD 15-1 to the horizontal CCD 15-2 is disposed between the horizontal CCDs 15-1 and 15-2. The composition which was made is taken.
[0066]
In this configuration, when charges are transferred from the vertical CCD 12 to the horizontal CCDs 15-1 and 15-2, for example, the charge of only the smear component is line-shifted to the horizontal CCD 15-1 by one line and further passed through the HH gate 43. It is transferred to the CCD 15-2. Subsequently, the charge for the next line, that is, the charge of the signal component + smear component is line-shifted from the vertical CCD 12 to the horizontal CCD 15-1. As a result, a signal component + smear component charge is present on the horizontal CCD 15-1, and a smear component charge is present on the horizontal CCD 15-2.
[0067]
Thereafter, the horizontal CCDs 15-1 and 15-2 are synchronously driven to transfer, so that the charges of the horizontal CCDs 15-1 and 15-2 are horizontally transferred in parallel, and the charge detectors 16-1 and 16-2. Is converted to a signal voltage and supplied to the signal processing circuit 25 shown in FIG. In this example, as shown in FIG. 17, the signal processing circuit 25 has a subtractor 44. In this subtractor 44, the signal based on the charge of the signal component + smear component is converted to only the smear component charge. By performing the process of subtracting the signal based on the smear component, it is possible to cancel the smear component and obtain a signal component without smear.
[0068]
FIG. 18 is a schematic configuration diagram showing, for example, an IT type color CCD imager according to the second embodiment of the present invention.
[0069]
In FIG. 18, sensor units (pixels) 51 are arranged in a two-dimensional matrix, and a plurality of vertical CCDs 52 are arranged for each vertical column of the sensor units 51, and between the vertical CCDs 52 and the sensor units 51. Is provided with a horizontal CCD 55 adjacent to each transfer destination side end of the plurality of vertical CCDs 52, and at the end thereof, for example, a charge detection unit 56 of a floating diffusion amplifier configuration. The basic configuration in which is arranged is the same as that of the CCD imager 10 according to the first embodiment.
[0070]
However, the CCD imager 50 according to the present embodiment is configured such that the vertical CCD 52 is driven in three phases by three-phase vertical transfer clocks Vφ1 to Vφ3. The three-phase vertical transfer clocks Vφ1 to Vφ3 and the two-phase horizontal transfer clocks Hφ1 and Hφ2 for driving the horizontal CCD 55 are generated by a timing generator (TG) 57. Also in this CCD imager 50, for example, a primary color Bayer array color filter shown in FIG. 3 is mounted.
[0071]
FIG. 19 is a plan pattern diagram showing a first specific example of the structure of the unit cell 54 including one sensor unit 51, the transfer stage of the vertical CCD 52 corresponding thereto, and the read gate unit 53.
[0072]
In FIG. 19, above the transfer channel 61 of the vertical CCD 52, transfer electrodes 62-1 to 62-3 to which three-phase vertical transfer clocks Vφ1 to Vφ3 are respectively applied are in the vertical transfer direction at a rate of one electrode per pixel. In FIG. These transfer electrodes 62-1 to 62-3 are alternately formed by a first layer of polysilicon (indicated by a one-dot chain line in the figure) and a second layer of polysilicon (indicated by a two-dot chain line in the figure). ing. In the figure, the area indicated by hatching is the channel stop portion 63.
[0073]
Also in the CCD imager 50 according to the second embodiment having the above-described configuration, the vertical CCD 52 is three-phase driven with respect to two vertical vertical color codings, and satisfies the above-described driving conditions, so that 3: 1 interlace is performed. Thus, by configuring one frame with three fields, the all-pixel mode and the monitoring mode can be realized in the same manner as in the case of six-phase driving.
[0074]
Furthermore, in the CCD imager 50 according to the second embodiment, in the first specific example of the unit cell, each pixel is configured by two transfer electrodes by adopting a unit cell structure in which each pixel is configured by one transfer electrode. Since the cell structure becomes simpler than in the case of the six-phase driving, it is advantageous for miniaturization of the device.
[0075]
FIG. 20 is a plan pattern diagram showing a second specific example of the unit cell structure. In FIG. 20, above the transfer channel 64 of the vertical CCD 52, transfer electrodes 65-1 to 65-3 to which three-phase vertical transfer clocks Vφ1 to Vφ3 are respectively applied are in the vertical transfer direction at a rate of one electrode per pixel. The transfer electrodes 65-1 to 65-3 are sequentially formed of one layer of polysilicon. In the figure, the area indicated by hatching is the channel stop portion 66.
[0076]
As described above, in the second specific example of the unit cell, the transfer electrodes 65-1 to 65-3 arranged at a rate of one electrode per pixel are formed of one layer of polysilicon, so that the first specific example. In addition to obtaining the same effect as the case, there is an advantage that the number of steps for forming the electrode can be reduced as compared with the case of the first specific example.
[0077]
In each of the above embodiments, the case where the primary color Bayer array is used as the color filter has been described. However, the color coding is not limited to the primary color Bayer array, and may be a complementary color Bayer array, for example. In short, if the same color has n repetitions in the row (vertical) direction (n is an integer of 2 or more), (n + 1): 1 interlace is performed to constitute one frame by (n + 1) fields. At the same time, the all-pixel mode and the monitoring mode can be realized by performing the vertical transfer of the signal charges with the clock of (n + 1) × m phase (m is a natural number).
[0078]
【The invention's effect】
As described above, according to the present invention, in a solid-state imaging device including a color coding color filter in which the same color is repeatedly arranged every n pixels in the row direction with respect to pixels arranged in a matrix, (N + 1): 1 interlace is performed to form one frame with (n + 1) fields, and vertical transfer of signal charges is performed by a clock of (n + 1) × m phase, so that all pixel mode and monitoring mode are used. Since it is not necessary to change the timing of the clock in the drive system, the configuration of the drive system can be simplified, and not only in the all pixel mode but also in the monitoring mode, pixel information of the Bayer array can be obtained for each filter. The video processing system can be projected and the signal processing system can be shared, simplifying the configuration of the signal processing system It will also be reduced.
[Brief description of the drawings]
FIG. 1 is a schematic configuration diagram illustrating an IT color CCD imager according to a first embodiment of the present invention.
FIG. 2 is a plan pattern diagram showing an example of a unit cell structure according to the first embodiment.
FIG. 3 is a diagram showing a 2 × 2 repeated primary color Bayer arrangement;
FIG. 4 is a schematic configuration diagram showing a camera system according to the present invention.
FIG. 5 is a block diagram illustrating an example of a specific configuration of a signal processing circuit.
FIG. 6 is a timing chart for explaining the operation in the all-pixel mode.
FIG. 7 is a conceptual diagram illustrating a procedure for reading pixel information.
FIG. 8 is a timing chart for explaining the operation of the first specific example of the monitoring mode.
FIG. 9 is a timing chart for explaining the operation of the second specific example of the monitoring mode;
FIG. 10 is a timing chart of six-phase vertical transfer clocks Vφ1 to Vφ6 in a normal mode.
FIG. 11 is a potential diagram of each transfer stage of the vertical CCD in the normal mode.
FIG. 12 is a schematic configuration diagram showing an example of a CCD imager compatible with a low smear mode.
FIG. 13 is a timing chart of six-phase vertical transfer clocks Vφ1 to Vφ6 in the low smear mode.
FIG. 14 is a potential diagram of each transfer stage of the vertical CCD in the low smear mode.
FIG. 15 is a block diagram showing an example of a configuration of a signal processing circuit corresponding to a low smear mode.
FIG. 16 is a schematic configuration diagram showing another example of a CCD imager compatible with a low smear mode.
FIG. 17 is a block diagram showing another example of the configuration of the signal processing circuit corresponding to the low smear mode.
FIG. 18 is a schematic configuration diagram showing an IT color CCD imager according to a second embodiment of the present invention.
FIG. 19 is a plan pattern diagram showing an example of a unit cell structure according to the second embodiment.
FIG. 20 is a plan pattern diagram showing another example of the unit cell structure according to the second embodiment.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10,50 ... Color CCD imager, 11, 51 ... Sensor part, 12, 52 ... Vertical CCD, 14, 54 ... Unit cell, 15, 15 ', 15-1, 15-2, 55 ... Horizontal CCD, 16, 16 -1, 16-2, 56 ... charge detection unit, 17, 57 ... timing generator, 19 ... color filter, 24 ... mechanical shutter, 25 ... signal processing circuit, 26 ... image recording device, 27 ... image display device, 28 ... Timing controller, 29 ... mode setting section

Claims (11)

A color filter for color coding in which the same color is repeatedly arranged for every n pixels (n is an integer of 2 or more) in the row direction with respect to the pixels arranged in a matrix;
(N + 1): 1 interlaced, one frame is composed of (n + 1) fields, and a drive system that performs vertical transfer of signal charges with a clock of (n + 1) × m phases (m is a natural number) is provided. A solid-state imaging device. 2. The solid-state imaging device according to claim 1, wherein the driving system independently transfers and drives signal component + smear component charge and smear component charge during vertical transfer. The solid-state imaging device according to claim 2,
A solid-state imaging device having a horizontal transfer unit having a transfer stage having a double density with respect to the number of pixels in the column direction. The solid-state imaging device according to claim 2,
Two horizontal transfer units having transfer stages of the same density with respect to the number of pixels in the column direction and juxtaposed to each other, and a transfer gate for selectively transferring charges between the two horizontal transfer units A solid-state imaging device comprising: 2. The solid-state imaging device according to claim 1, wherein the drive system is a three-phase drive and has a unit cell structure in which one transfer electrode is assigned to one pixel. 6. The solid-state imaging device according to claim 5, wherein the transfer electrode is formed of two layers of polysilicon. 6. The solid-state imaging device according to claim 5, wherein the transfer electrode is formed of a single layer of polysilicon. A driving method of a solid-state imaging device including a color coding color filter in which the same color is repeatedly arranged for every n pixels (n is an integer of 2 or more) in a row direction with respect to pixels arranged in a matrix. ,
(N + 1): 1 solid-state imaging device characterized in that one frame is formed by (n + 1) fields by performing interlace, and signal charges are vertically transferred by a clock of (n + 1) × m phases (m is a natural number). Driving method. 9. The driving of a solid-state imaging device according to claim 8, wherein in the (n + 1) times monitoring mode, only the pixel information of any one of (n + 1) fields is repeatedly read to display a moving image. Method. 9. The method for driving a solid-state imaging device according to claim 8, wherein in the (n + 1) times monitoring mode, the pixel information of the (n + 1) field is sequentially read to display a moving image. A color coding color filter in which the same color is repeatedly arranged for every n pixels (n is an integer of 2 or more) in the row direction with respect to pixels arranged in a matrix, and (n + 1): 1 interlace is provided. A solid-state imaging device configured to perform vertical transfer of signal charges with a clock of (n + 1) × m phase (m is a natural number),
A mechanical shutter that selectively captures incident light from a subject onto the imaging surface of the solid-state imaging device;
A mode setting section for selectively setting all pixel mode and monitoring mode;
A timing controller that performs timing control of the solid-state imaging device and opening / closing control of the mechanical shutter according to the imaging mode set by the mode setting unit;
A signal processing circuit for processing an output signal of the solid-state imaging device;
An image recording apparatus for recording image information on a recording medium based on the signal processed by the signal processing circuit;
A camera system comprising: an image display device that displays image information based on a signal processed by the signal processing circuit on a monitor.

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