JPH08137785A - Dma controller - Google Patents

Abstract

PURPOSE: To enable high-speed transferring without completely stopping CPU, corresponding to a wide-range transfer request of a DMA device. CONSTITUTION: A DMA controller 102 obtains the usage right of busses 105, 106 and 107 at the time of a DMA request and starts transferring. In this case, a transfer interval timer 211 is started, transfer is interrupted when the prescribed time elapses and returns control to CPU. During transfer, transferred data quantity is counted by a temporary counter 210. Transfer speed is calculated by data quantity and passage time, time according to the transfer speed is set in the timer 211 again and succeeding transfer is executed. Thus, since control is returned to CPU at every prescribed time, a system where a processing by CPU is not completely stopped without slowing down DMA speed more than necessity is constituted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA for controlling a DMA transfer in, for example, a microcomputer system.
Regarding the control device.

[0002]

2. Description of the Related Art An example of a data transfer procedure by DMA is shown below. 1. Issuing a DMA execution command from the CPU to the DMA request device. 2. Request of bus right from the DMA request device to the bus master. 3. Securing the bus use right of the DMA request device by bus arbitration. 4. Data transfer by DMA sequence. 5. Data transfer completed. 6. Abandonment of bus usage rights. 7. Ensuring the bus master's right to use the bus.

The bus master is generally a CPU, but in a bus having a plurality of devices that can be bus masters, the device that will be the bus master next to the DMA request device is determined by their priority. The DMA data transfer mode includes a burst mode and a cycle steal mode.

In the burst mode, the DMA is executed until the transfer of the data amount set at the time of issuing the DMA execution command is completed.
The requesting device continues to reserve the bus. In this mode, high-speed data transfer is possible, but devices using the bus other than the DMA request device cannot function during the transfer period.

In the cycle steal mode, D is set only when the bus master other than the DMA request device does not use the bus.
Perform MA transfer. Basically, the bus exclusive right is released every time one word is transferred. In this mode, the bus masters other than the DMA request device can function even during the data transfer period, but the transfer rate is considerably reduced.

[0006]

In the burst transfer mode, the transfer can be executed at high speed, but other bus masters cannot function during that period. For example, another bus master is the CPU
If the bus is an address bus or data bus directly connected to the CPU, the CPU stops. If D
If the MA requested device transfer rate is governed by an external I / F, etc., if the external I / F is slow CP
U may stall for an extended period of time causing serious problems with system functionality.

In the cycle steal mode, the CPU functions in the above case as well, but even if the external I / F is high speed, the hardware of the I / F cannot be fully used and the data transfer rate is lowered. Reduce system efficiency.

The present invention has been made in view of the above-mentioned conventional example, and can cope with a wide range of transfer requests of the DMA device and can perform high-speed transfer without completely stopping the CPU.
MA control can be performed.

[0009]

[Means for Solving the Problems] and

In order to achieve the above object, the DMA controller of the present invention has the following structure. That is, although the DMA transfer is basically performed by the burst transfer, the bus exclusive right is abandoned every predetermined transfer amount or transfer time. If the data transfer is slow, the amount of continuous DMA transfer is reduced to increase the CPU bus right. If the transfer speed is high, the continuous DMA transfer charge is increased to prevent the system performance from being deteriorated due to the data transfer. In this way, D can be used at any bus occupation rate.
By executing the MA transfer, it is possible to cope with a wide range of transfer speeds of the DMA request device, and to cope with the speedup without completely stopping the CPU.

A DMA control device for controlling a DMA transfer from a transfer source to a transfer destination via a bus managed by a bus master, and acquiring means for acquiring the right to use the bus from the bus master and the acquiring means. The period in which the DMA transfer is continuously performed via the specified bus is limited to a predetermined period, and when the period elapses, the limiting means for abandoning the right to use the bus, and the acquiring means and the limiting means determine the data to be transferred. Control means for controlling the DMA transfer until it is completed.

Further, a DMA controller for performing a DMA transfer using a bus managed by the bus master, a bus arbiter for arbitrating the bus use right with the bus master to obtain the bus use right, and a continuous DMA data transfer of a plurality of words A read / write sequencer for controlling the sequence, a bus control means for controlling the bus obtained the right of use by the bus arbiter in accordance with the instructions of the read / write sequencer, and limiting the length of continuous DMA data transfer under a predetermined condition, When the condition is exceeded, a transfer limiting means is provided for instructing the RAID write sequencer to stop the DMA transfer, and at the same time instructing the bus arbiter to abandon the bus use right.

[0012]

【Example】

[Embodiment 1] FIG. 1 shows a configuration example of a CPU peripheral circuit including a DMA controller. The access from the CPU 101 to the peripheral circuits is performed by the address bus 105, the data bus 106, and the control signal 107. Normally, the CPU 101 serves as a bus master and controls these buses. When the DMA request signal 108 from the DMA transfer source device 103 is generated, that is, when there is a DMA request, the DMA controller 102 stops the CPU 101 with the bus arbitration signal 109 and becomes a bus master to control the bus. In this state, data transfer is performed between the DMA transfer source device 103 and the DMA transfer destination device 104. The DMA transfer source device mentioned here is a device that issues a DMA request, and
The MA transfer destination device is a memory or a register,
This is a device that is the target of data transfer with the DMA transfer source device. The DMA transfer source device performs data transfer with the external I / F 112, and controls the data transfer at a transfer speed according to the transfer capability of the I / F standard or another device or host (not shown) connected to this I / F. To do.

The DMA transfer may be performed in a 2-access / transfer cycle mode in which transfer between a DMA transfer source and a transfer destination is performed in read / write-specific bus cycles, or in a 1-access / transfer cycle mode in which the other is simultaneously written during the read period. Good. However, in the former case, data is temporarily stored in a temporary register inside the DMA controller as a bus cycle, and in the latter case, a read / write control signal line (not shown) dedicated to DMA is required.

When the DMA transfer is completed, the DMA transfer source device 103 extinguishes the DMA request signal 108 and DMs.
A withdraw the request. In response to this, the DMA controller 102 returns the bus control right to the CPU 101. Also D
Interrupt signal 110 or 1 in response to MA transfer completion
11 is generated and the completion is notified to the CPU 101.

A configuration example of the DMA controller 102 is shown in FIG.
Shown in In a normal operation state in which the CPU 101 is a bus master, the control signal control circuit 201 and the address bus control circuit 203 function as input circuits and operate to access the registers inside the DMA controller 102 via the read / write control circuit 206. .

The bus arbiter 208 receives the DMA request signal 1
When 08 occurs, arbitration is performed with the CPU 101, the CPU is stopped, and the read / write sequence circuit 204 is activated after becoming a bus master. The read / write sequence circuit 204 is a control signal control circuit 201.
The control signal 107 is controlled via the control signal to control the read / write of the DMA transfer source device 103 and the DMA transfer destination device 104, and the DMA transfer is executed. An address generation circuit 207 generates addresses for accessing these devices. In the operation mode of 2 access / transfer cycles, the data read in the read cycle is temporarily stored in the temporary register 205 and written to the device in the write cycle.

The transfer counter 209 counts the number of transfer bytes. When the transfer of a preset value is completed, the read / write sequence circuit 204 is stopped, the bus arbiter 208 returns the bus control right to the CPU 101, and the interrupt control circuit 212. Via CPU 101
Generates an interrupt signal 110 for requesting a transfer end process. If the DMA transfer source device has a transfer byte count function, this interrupt request is D
The DMA controller does not have to issue an interrupt request, since the MA transfer source device performs the interrupt signal 111.

Like the transfer counter 209, the temporary counter 210 counts the number of transfer bytes, which is reset when the DMA transfer is restarted after the transfer interval timer 211 gives up the bus control right temporarily. That is, the CPU 101 uses the temporary counter 21
The DMA transfer rate can be calculated from the value of 0 and the set value of the transfer interval timer 211.

The transfer interval timer 211 holds the maximum continuous DMA transfer time designated by the CPU 101, stops the read / write sequence when this set time elapses after the read / write sequence circuit 204 is activated, and via the bus arbiter circuit 208. Bus control right to CPU 101
Return to. This puts the CPU 101 into an operating state,
If the DMA transfer request signal 108 is asserted, the bus arbiter 208 performs the bus arbitration again immediately after the CPU 101 becomes the bus master, and obtains the bus control right.

These operations are shown in the timing diagram of FIG. A waveform 301 is a bus request signal in the bus arbitration signal 109, a waveform 302 is a bus master, and a waveform 303 is a DMA transfer state. DMA request signal 10
When 8 occurs, the bus request signal 30 is correspondingly generated.
1 is asserted (timing t1). This makes D
The MA controller 102 becomes a bus master as shown by the waveform 302, and performs DMA transfer as shown by the waveform 303 (timing t2). As described above, transfer interval timer 2
When the continuous maximum DMA transfer time p1 set by the CPU 101 elapses after the read / write sequence circuit 204 is activated, the read / write sequence 11 stops the read / write sequence and controls the bus control right via the bus arbiter circuit 208.
Return to U101. This is the timing t3. Immediately after the CPU 101 becomes the bus master, the bus arbiter circuit 208 asserts the bus request 301 again to obtain the bus control right again (timing t4). Here, if the continuous maximum DMA transfer time p1 set in the transfer interval timer 211 is shortened, the operation approaches a complete burst transfer if the continuous maximum DMA transfer time p1 is shortened to a cycle steal mode in which a CPU access cycle enters every byte or word transfer. . If the transfer set in the transfer counter is completed before the time set in the transfer interval timer 211 is completed or the DMA request signal 108 is negated (timing t5), the bus request 301 is negated at that time and the bus control is performed. Is returned to the CPU 101 and the DMA sequence is stopped. At this point, if necessary, the interrupt signal 110 is asserted to cause the CPU 101 to perform the DMA stop process.

The CPU 101 has a temporary counter 21.
By reading a value of 0, the number of bytes transferred during the set transfer interval can be known during the DMA transfer period as described above, and the transfer rate can be estimated from this. If it is judged from this transfer rate that the transfer efficiency should be further increased, the transfer interval is lengthened to operate in a state close to burst transfer, and in the opposite case, the transfer interval is shortened to operate in a state close to cycle steal transfer. Let This processing procedure is shown in FIG.

Control is transferred from the DMA to the CPU, and D
If the MA transfer is not yet completed, the transfer interval is first read from the transfer interval timer 211 (step S70).
1) The transfer data amount is read from the temporary counter 210 (step S702). The transfer rate is calculated from these values (step S703), and it is determined whether the set transfer interval is appropriate (step S704). If it is appropriate, the value remains as it is, but if it is not appropriate, an appropriate value is reset in the transfer interval timer 211 (step S705).
For the determination in step S705, a table or the like that compares transfer rates and transfer intervals may be stored in advance in the memory. Finally, for the next transfer sequence,
The temporary counter 210 is reset to 0 (S7).
06).

As described above, by changing the continuous maximum DMA transfer time set in the transfer interval timer 211, when the external I / F transfer rate is high and the DMA transfer rate is high, continuous bus monopolization by DMA is performed. It is possible to increase the transfer efficiency by increasing the time, and conversely, if it is small, shorten the continuous bus occupation time to increase the operation efficiency of the CPU. That is, data can be transferred at an arbitrary DMA bus occupation rate.

[Second Embodiment] FIG. 4 shows a DMA controller according to the second embodiment. The configuration of the entire device is as shown in FIG. In the first embodiment, the transfer interval timer 21
Although the maximum continuous DMA transfer time is controlled by 1, the transfer interval timer 211 and the temporary counter 210 are used in this embodiment.
The transfer interval counter 401 is provided instead of
The bus occupation time of DMA is controlled by the number of MA transfer bytes. The transfer interval counter 401 holds the maximum number of continuous DMA transfer bytes designated by the CPU 101, and when the number of continuous transfer bytes reaches this set value even when the DMA request signal 108 is asserted, the bus control right is given through the bus arbiter 208. Return to CPU 101. The CPU 101 can calculate the time required to transfer the set number of bytes from a system clock (not shown), and controls the setting of the maximum number of continuous DMA transfer bytes according to this result. This control may be performed in the same manner as in FIG. However, since the temporary counter 210 is not used, step S706 is unnecessary, and the point that the transfer interval is set not by time but by the amount of data is different. If the set value of the time required for transfer is increased, it will be closer to burst transfer, and if it is set smaller, it will be closer to cycle steal transfer. That is, similarly to the first embodiment, data transfer can be performed at an arbitrary DMA bus occupation rate.

[Third Embodiment] FIG. 5 shows a DMA controller according to a third embodiment. In this configuration example, DMA is continuously
The count control circuit 501 controls the maximum number of continuous DMA transfer bytes, which is the maximum value that can be transferred. This is performed according to the setting of the transfer count table 502. CPU1
In 01, the relationship between the bus occupation rate and the transfer rate according to the transfer rate is downloaded to the transfer count table 502 prior to the DMA transfer. The count control circuit 501 is the second
In the same manner as in the first embodiment, when the number of continuous DMA transfer bytes reaches a certain number of transfer bytes, the transfer sequence is interrupted and the bus control right is returned to the CPU. At that time, the timer 503 is started at the start of the DMA transfer and stopped at the time of interruption. In this way, the transfer time is calculated from the elapsed time by the timer 503,
The transfer speed is calculated from the time required for the transfer. The transfer count table 502 stores the maximum number of continuous DMA transfer bytes with the transfer rate as an index, and the count control circuit 501 stores the conversion result as the maximum continuous D of the next DMA transfer.
It operates as the number of MA transfer bytes. With the above operation, the DMA controller 102 operates by automatically controlling the bus occupancy rate according to the characteristics set in advance by the CPU in the transfer count table.

[Fourth Embodiment] FIG. 6 shows a DMA controller according to a fourth embodiment. In this configuration example, the count control circuit 601 operates by setting the maximum number of continuous DMA transfer bytes to the value registered in the host I / F table 602.
The DMA transfer source device 103 operates according to the transfer speed of the external I / F 112 and the transfer speed of the DMA controller 102. However, the transfer speed of the host (not shown) connected to the external I / F 112 is the host and the I / F. It can be roughly estimated according to the type. The host I / F table 6 is a correspondence table of the estimated transfer speed and the maximum number of continuous transfer bytes corresponding to the bus occupation rate by the corresponding DMA.
02. Prior to the DMA transfer, the CPU 101 inputs the host and the I / F type ID code as an index into the host I / F table, and the count control circuit 601 reads the value corresponding to the index from the table and outputs it as the maximum continuous transfer byte. The number is set in the count control circuit, and DMA control is performed. As a result, the CPU 101 can perform optimum DMA transfer simply by designating a simple index.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of a single device. Further, it goes without saying that the present invention can be applied to the case where it is achieved by supplying a program to a system or an apparatus.

[0028]

As described above, the DM according to the present invention
The A control device has an effect that it can handle a wide range of transfer requests from the DMA device and can perform DMA control that enables high-speed transfer without completely stopping the CPU.

[0029]

[Brief description of drawings]

FIG. 1 is a configuration example of a system including a DMA controller.

FIG. 2 is a block diagram showing a first configuration example of a DMA controller.

FIG. 3 is a waveform diagram during operation of the DMA controller.

FIG. 4 is a block diagram showing a second configuration example of a DMA controller.

FIG. 5 is a block diagram showing a third configuration example of a DMA controller.

FIG. 6 is a block diagram showing a fourth configuration example of a DMA controller.

FIG. 7 is a flowchart showing a procedure for controlling a bus occupancy rate by DMA.

[Explanation of symbols]

 101 CPU 102 DMA controller 103 DMA source device 104 DMA destination device 201 Control signal control circuit 202 Data bus control circuit 203 Address bus control circuit 204 Read / write sequence circuit 205 Temporary register 206 Read / write control circuit 207 Address generation circuit 208 Bus arbiter 209 Transfer counter 210 Temporary counter 211 Transfer interval timer 401 Transfer interval counter 501 Count control circuit 502 Transfer count table 503 Timer 602 Host I / F table

Claims (9)

[Claims] 1. A DMA control device for controlling a DMA transfer from a transfer source to a transfer destination via a bus managed by a bus master, the acquiring means acquiring the bus use right from the bus master, and the acquiring means. DMA continuously through the bus
Limiting means for limiting the transfer period to a predetermined period and for relinquishing the right to use the bus when the period elapses, and controlling means for performing the DMA transfer by the acquiring means and the limiting means until the data to be transferred is completed. And a control unit for controlling the DMA control unit. 2. The method according to claim 1, further comprising means for calculating a transfer rate from the predetermined period and the amount of data transferred during the predetermined period, and resetting the predetermined period according to the transfer rate. The DMA controller according to item 1. 3. DM using a bus managed by a bus master
A DMA controller for A transfer, which is used by a bus arbiter for arbitrating a bus mastership with a bus master to obtain a bus mastership, a read / write sequencer for controlling an execution sequence of continuous DMA data transfer of a plurality of words, and the bus arbiter. Bus control means for controlling the acquired bus according to the instructions of the read / write sequencer, and limiting the length of continuous DMA data transfer under a predetermined condition, and stopping the DMA transfer when the condition is exceeded. A DMA controller, comprising: a read / write sequencer and transfer limiting means for instructing the bus arbiter to relinquish the bus use right. 4. The DMA controller according to claim 3, further comprising means for externally setting a condition for limiting a length of the DMA data transfer. 5. The DMA control device according to claim 4, wherein the transfer limiting means limits the length of continuous DMA data transfer on condition that the elapsed time from the start of the read / write sequence operation by the read / write sequencer. 6. The transfer limiting means limits the length of continuous DMA data transfer on the condition of the number of transfer words from the start of the read / write sequence operation by the read / write sequencer. DMA controller. 7. The transfer limiting means measures the transfer speed of continuous DMA data transfer, and the number of words continuously transferred with DMA data based on the measurement result by the measuring means and the elapsed time. And a conversion means for converting to
4. The DMA controller according to claim 3, wherein the number of words obtained by the converting means is set as the predetermined condition. 8. The transfer limiting means comprises a setting means for setting an ID code for identifying a device performing a DMA transfer,
4. A conversion means for converting the number of words to be continuously DMA-transferred based on the set ID code, and the number of words obtained by the conversion is the predetermined condition.
The DMA controller described. 9. The transfer control means further includes an ID code setting means for performing DMA data transfer control with a DMA request device having an I / F connected to an external host machine and for identifying the external host machine. 9. The DMA control device according to claim 8, wherein: